JP2004039170A - Semiconductor storage - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor storage for setting a rewriting prohibition region. <P>SOLUTION: The semiconductor storage comprises a low writing prohibition region setting register (12) for storing low address information in a rewriting prohibition region; a low decoder (10) for asserting a write protect signal on the basis of the setting information; a column rewriting prohibition region setting register (16) for storing column address information in the writing prohibition region; a column decoder (15) for asserting a column system write protect signal on the basis of the setting information; and a control logic (19) for prohibiting data writing to a specific region on the basis of the low system write protect signal, the column system write protect signal and a write enable signal. The rewriting prohibition region can be set thereby. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor memory device, particularly to a random access RAM (random access memory), and more particularly to a technique effective when applied to a main memory mounted on a computer system.
[0002]
[Prior art]
For example, in an SRAM in which a plurality of static memory cells are arranged in a matrix, a selection terminal of the memory cell is coupled to a word line in each row direction, and a data input / output terminal of the memory cell is connected to a complementary data line ( (Also referred to as complementary bit lines).
[0003]
When one word line is driven to a selected level based on the output of a row decoder that decodes a row address, all memory cells coupled to the selected word line are coupled to the corresponding complementary data lines. Each complementary data line is commonly connected to a complementary common data line via a column selection circuit including a plurality of column selection switches coupled one-to-one to the complementary data line. The plurality of column selection switches are selectively turned on based on the output of a column decoder that decodes a column address.
[0004]
A decoder for decoding a row address and a column address decoder for decoding a column address are configured by a combination of a NAND gate, a NOR gate, and a plurality of decode lines.
[0005]
An example of a document describing SRAM is “LSI Handbook (from page 500)” issued by Ohmsha on November 30, 1984.
[0006]
[Problems to be solved by the invention]
In a conventional SRAM, a write-protected area cannot be set, so that data can be freely written and read in all address spaces of the memory. Therefore, when an SRAM is applied as a main memory of a personal computer system or the like, a problematic program is executed in an environment where an operating system (OS) or a plurality of application programs operating on the OS operates. In such a case, the execution of the program rewrites the system management area in the main memory, which may adversely affect the operation of the entire system.
[0007]
SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor memory device in which a rewrite prohibited area can be set.
[0008]
The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
[0009]
[Means for Solving the Problems]
The outline of a representative invention among the inventions disclosed in the present application will be briefly described as follows.
[0010]
That is, when a semiconductor memory device is configured including a memory cell array in which a plurality of memory cells are arranged in an array, control for inhibiting data writing to a specific area in the memory cell array in response to a write protect signal Provide logic.
[0011]
According to the above means, the control logic inhibits data writing to a specific area in the memory cell array in response to the write protect signal. This makes it possible to set a rewrite prohibited area.
[0012]
A first register capable of storing row address information about a rewrite prohibited area in the memory cell array; and a row write protect signal when the input row address signal matches the set address information of the first register. , A second register capable of storing column address information about a non-rewritable area in the memory cell array, and an input column address signal coincides with set address information of the second register. In this case, a logical operation is performed between the second determination means capable of asserting a column-based write protect signal, the row-based write protect signal, the column-based write protect signal, and a write enable signal indicating an external write instruction. It can be configured as follows.
[0013]
Further, instead of providing the first register and the second register, a first external input terminal and a second external input terminal for taking in the rewrite prohibited area information from outside can be provided.
[0014]
Further, in order to enable external processing of the write protection signal, a terminal capable of externally outputting the signal can be provided.
[0015]
In order to facilitate debugging of the malfunction program when data is written in the non-rewritable area in the memory cell array, the data input for writing in the non-rewritable area can be held. Means can be provided.
[0016]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 shows a computer system including a RAM as an example of a semiconductor memory device according to the present invention.
[0017]
Although not particularly limited, the computer system 300 shown in FIG. 1 includes a CPU (central processing unit) 31, an SRAM 32, a peripheral device control unit 35, a hard disk 38, a keyboard 39, and a display system 36. The CPU 31, the SRAM 32, the peripheral device control unit 35, and the display system 36 are connected so that signals can be exchanged by a system bus BUS.
[0018]
The CPU 31 performs arithmetic processing according to a preset program. The SRAM 32 is, but not limited to, a static memory, into which an operating system and various application programs are loaded. The operating system and various application programs loaded into the SRAM 32 are executed by the CPU 31. Here, a rewrite-protected area is set in the SRAM 32 so that the information stored in the area is not destroyed by subsequent undesired writing.
[0019]
The peripheral device control unit 35 controls peripheral devices such as a hard disk 38, which is an example of an external storage device, and a keyboard 39 for inputting various information. The display system 36 is not particularly limited, but is a liquid crystal display or the like, and the CPU 31 displays arithmetic processing results and various information.
[0020]
FIG. 1 shows a configuration example of the SRAM 32.
[0021]
The memory cell array 11 is arranged such that a plurality of word lines and a plurality of data lines intersect, and static memory cells are arranged at the intersections. The row decoder 10 decodes the input row address and generates a signal for selectively driving one of the plurality of word lines. A row rewrite prohibited area setting register 12 capable of holding row related rewrite prohibited area information is provided. Here, the row rewrite inhibition area setting register 12 is an example of a first register in the present invention. The row decoder 10 determines whether or not the input row address matches the address set in the row rewrite protection area setting register 12, and if the two addresses match, the write protect signal / WPR (/ Indicates that the signal is active low) to a low level. Here, the row decoder 10 is an example of a first determination unit in the present invention.
[0022]
The input / output circuit 14 includes a column selection switch for selectively connecting a plurality of data lines in the memory cell array to a common line, and a sense amplifier for amplifying data transmitted to the common line via the column selection switch. And a write circuit for transmitting write data to a corresponding data line via the column selection switch. The write data is transmitted via the input buffer 17 and the input data controller 13. Read data from the memory cell is output to the outside via the output buffer 18.
[0023]
The column decoder 15 generates a signal for driving the column selection switch by decoding the input column address. A column rewrite prohibited area setting register 16 capable of holding column type rewrite prohibited area information is provided. Here, the column rewrite prohibited area setting register 16 is an example of a second register in the present invention. The column decoder 15 determines whether or not the input address matches the address set in the column rewrite inhibition area setting register 16. If the two addresses match, the column protector 15 outputs the write protect signal / WPC. Assert low level. Here, the column decoder 15 is an example of a second determination unit in the present invention.
[0024]
Further, a logic gate 19 for generating an operation control signal for each unit based on a write enable signal indicating an external write instruction, a chip select signal / CS, and an output enable signal / OE indicating validity of data output. , 20, 21, and 22 are provided. The chip select signal / CS input from the outside is inverted by the logic gate 22, and then transmitted to the row decoder 10 and the column decoder 15. The row decoder 10 and the column decoder 15 operate in a state where the chip select signal CS is asserted at a high level.
[0025]
The logic gate 19 performs a logical operation of a write protect signal / WPR from the row decoder 10 and a write protect signal / WPC from the column decoder 15 and a write enable signal indicating an external write instruction. The result of this logical operation is transmitted to the subsequent logic gate 20. The logic gate 20 performs a logic operation on the output signal of the logic gate 19 and the chip select signal / CS. The result of this logical operation is used as an operation control signal for the input buffer 17.
[0026]
The logic gate 21 performs a logic operation on the output signal of the logic gate 19, the chip enable signal / CS, and the output enable signal / OE. The result of this logical operation is used as an operation control signal for the output buffer 18.
[0027]
Normally, if the write enable signal / WE is asserted to a low level, data writing to the memory cell array 11 is instructed. In this example, however, the write protect signal / WPR from the row decoder 10 and the column decoder 15 Only when both write protect signals / WPC are negated to a high level, data writing is allowed. That is, when the write enable signal / WE is asserted to a low level and both the write protect signal / WPR from the row decoder 10 and the write protect signal / WPC from the column decoder 15 are negated to a high level. , The output logic of logic gate 19 is at a high level. At this time, if chip select signal / CS is asserted at a low level, the output logic of logic gate 20 is at a high level and input buffer 17 is turned on. . In this state, it is possible to take in the write data.
[0028]
On the other hand, as shown in FIG. 2, when at least one of the write protect signal / WPR from the row decoder 10 and the write protect signal / WPC from the column decoder 15 is asserted to a low level. Since the output logic of the logic gate 19 is at a low level and the output logic of the logic gate 20 is at a low level, the input buffer 17 is not conducted. That is, the write data is not transmitted to the node 100. As described above, when at least one of the write protect signal / WPR from the row decoder 10 and the write protect signal / WPC from the column decoder 15 is asserted to a low level, the input buffer is not turned on and the write operation is not performed. Since no data is taken in, no data is rewritten in the corresponding memory area.
[0029]
On the other hand, at the time of data reading, since the write enable signal / WE is negated to the high level, even if the write protect signals / WPR and / WPC are asserted to the low level in this state, the output node of the logic gate 19 remains at the low level. Since the data input buffer 17 is fixed at the low level, the data input buffer 17 is not turned on and data is not written. However, even if the write protect signals / WPR and / WPC are asserted to a low level by the row decoder 10 and the column decoder 15, the data output buffer 18 is turned on in response to the output of the logic gate 21, so that the write-protection area is disabled. It is possible to read data from.
[0030]
According to the above example, the following effects can be obtained.
[0031]
(1) When at least one of the write protect signal / WPR from the row decoder 10 and the write protect signal / WPC from the column decoder 15 is asserted to low level, the output logic of the logic gate 19 becomes low level. Since the output logic of logic gate 20 is at a low level, input buffer 17 is not conducted. Thereby, data rewriting is prohibited, so that a rewriting prohibited area can be formed in the SRAM 32.
[0032]
(2) In the computer system 300, since the SRAM 32 having the operation and effect (1) is applied as a main memory, the write-protection area is formed separately from the SRAM 32 by a dedicated chip such as a read-only memory. In comparison, the number of chips can be reduced.
[0033]
Although the invention made by the present inventors has been specifically described above, the present invention is not limited thereto, and it goes without saying that various modifications can be made without departing from the gist of the invention.
[0034]
For example, in the above-described example, the one including the row rewrite prohibited area setting register 12 and the column rewrite prohibited area setting register 16 has been described, but these can be omitted. For example, as shown in FIG. 4, a first external input terminal 201 for taking in row address information about a non-rewritable area in the memory cell array 11 from outside the chip and column address information about a non-rewritable area in the memory cell array 11 are stored. If a second external input terminal 202 for taking in from outside the chip is provided, and row address information and column address information on the above-mentioned rewriting prohibited area are taken in from outside the chip, the row rewriting prohibited area setting register 12 and the column It is not necessary to provide the rewrite prohibited area setting register 16 in the SRAM 32.
[0035]
Further, the write protect signal / WPR or / WPC may be externally output. For example, as shown in FIG. 4, a first external output terminal 101 capable of outputting a write protect signal / WPR to the outside of the SRAM 32, and a second external output terminal capable of outputting a write protect signal / WPC to the outside of the SRAM 32 102 are provided. Thus, the write protect signal / WPR can be externally output via the first external output terminal 101, and the write protect signal / WPC can be externally output via the second external output terminal 102. Thus, when an undesired write is attempted to be performed in the rewrite prohibited area, external monitoring of the undesired write is enabled, so that it is possible to easily debug a program for performing such write.
[0036]
Further, when an undesired write is attempted to be performed in the overwrite-protected area, the data itself relating to the undesired write is held in an appropriate holding unit, thereby facilitating debugging of a program for performing such write. Can be achieved. For example, as shown in FIG. 4, a register 103 capable of holding write data is provided, and a write operation of the register 103 is controlled according to an output signal of the logic gate 20. That is, the write data is written to the register 103 in a state where the input buffer 17 is turned off. By analyzing the information held in the register 103 when an undesired write is attempted to be performed on the overwrite-protected area, it is possible to facilitate the debugging of a program that performs such a write.
[0037]
In the above description, the case where the invention made by the present inventor is mainly applied to the SRAM, which is the background of the application, has been described. However, the present invention is also applied to a DRAM having dynamic memory cells arranged in an array. Can be applied. Further, the present invention can be applied to a RAM built in a single-chip microcomputer or the like.
[0038]
The present invention can be applied on the condition that it includes at least a memory cell array.
[0039]
【The invention's effect】
The following is a brief description of an effect obtained by a representative one of the inventions disclosed in the present application.
[0040]
That is, when a semiconductor memory device is configured to include a memory cell array in which a plurality of memory cells are arranged in an array, control for inhibiting data writing to a specific area in the memory cell array in response to a write protect signal By providing the logic, it is possible to set a rewrite prohibited area. In a computer system equipped with such a semiconductor memory device, the number of chips can be reduced as compared with the case where the rewrite prohibited area is formed separately by a dedicated chip such as a read-only memory.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a configuration example of an SRAM which is an example of a semiconductor storage device according to the present invention.
FIG. 2 is an operation timing chart of a main part in the SRAM.
FIG. 3 is a block diagram of an overall configuration example of a computer system including the SRAM.
FIG. 4 is a block diagram illustrating another configuration example of the SRAM.
[Explanation of symbols]
Reference Signs List 10 Row decoder 11 Memory cell array 12 Row rewrite prohibited area setting register 13 Input data controller 14 Input / output circuit 15 Column decoder 16 Column rewrite prohibited area setting register 17 Input buffer 18 Output buffer 19-22 Logic gate

Claims (5)

A semiconductor memory device including a memory cell array in which a plurality of memory cells are arranged in an array,
Determining means for determining that the input address signal corresponds to the rewrite prohibited area and asserting the write protect signal;
And a control logic for prohibiting data writing to a specific area in the memory cell array in response to the write protect signal. A semiconductor memory device including a memory cell array in which a plurality of memory cells are arranged in an array,
A first register capable of storing row address information about a non-rewritable area in the memory cell array;
First determination means capable of asserting a row write protect signal when the input row address signal matches the set address information of the first register;
A second register capable of storing column address information about a non-rewritable area in the memory cell array;
A second determining unit capable of asserting a column-based write protect signal when the input column address signal matches the set address information of the second register;
Control logic for prohibiting data writing to a specific area in the memory cell array based on the row write protect signal, the column write protect signal, and a write enable signal indicating an external write instruction. A semiconductor memory device characterized by including: A semiconductor memory device including a memory cell array in which a plurality of memory cells are arranged in an array,
A first external input terminal that enables external input of row address information for a non-rewritable area in the memory cell array;
First determining means capable of asserting a row write protect signal when the input row address signal matches input address information from the first external input terminal;
A second external input terminal for enabling external input of column address information for the non-rewritable area in the memory cell array;
A second determination unit capable of asserting a column-based write protect signal when the input column address signal matches input address information from the first external input terminal;
Control logic for prohibiting data writing to a specific area in the memory cell array based on the row write protect signal, the column write protect signal, and a write enable signal indicating an external write instruction. A semiconductor memory device characterized by including: 4. The semiconductor memory device according to claim 1, further comprising a terminal capable of externally outputting said write protect signal. 5. The semiconductor memory device according to claim 1, further comprising a holding unit capable of holding data input for writing into a non-rewritable area in said memory cell array.

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