KR20200067418A - Semiconductor memory device having closed cell and address decoder - Google Patents

Abstract

The present invention relates to a semiconductor memory device which comprises: a memory cell consisting of a plurality of open cells that allow access to read or write and a closed cell that allows access to read or write only when a protection key signal is received; and an address decoder which can access the closed cell only by transmitting a protection key signal. By allowing only a specific user or manufacturer to access the closed cell, reliability of unique information or specification information of the semiconductor memory device can be maintained.

Description

Semiconductor memory device having closed cell and address decoder

This document relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having a closed cell and an address decoder in which access to the memory cell area is blocked.

Semiconductor memory devices, which are widely used in high-performance electronic systems, include volatile memory chips (eg, RAM, DRAM) or non-volatile memory chips (eg, ROM, hard disk, NAND, NOR). controller) and data. The semiconductor memory device is composed of a plurality of blocks (Blocks) and a cell area that stores specific information and an interface that can selectively access the cell area to read ("Read") or write ("Write") It consists of an address decoder that functions as a circuit. As an example, the semiconductor memory device may perform a processing operation according to a command type provided from the memory controller, or read data stored therein and provide the data to the memory controller.

The cell area stores specification information (eg, manufacturer name, production information, capacity, and speed) of the semiconductor memory device in addition to various data for driving the electronic system. If a general user easily accesses this information and reads or writes to damage the semiconductor memory device or electronic system, the semiconductor memory device manufacturer or electronic system manufacturer becomes difficult to manage its products. Production and sales may be adversely affected. In order to solve this problem, the function (protection) of the specification information so that only the semiconductor memory device manufacturer or a specific user can access the cell (block) in which the product specification information of the semiconductor memory device is stored. Needs to be added.

Korean Patent Publication (Publication No.: 10-2008-0017836, “Block State Storage Device of Flash Memory”) discloses a technology having a common internal channel shared among a plurality of memory cell groups, but it is disclosed No technology is disclosed for protecting information by blocking access.

The present invention relates to a semiconductor memory device, and product specification information stored in a specific cell in a memory cell area allows access to a specific user, thereby modifying or damaging the semiconductor memory device. ) Or to prevent copying.

A semiconductor memory device according to an aspect for achieving this object,

Memory cell array constituting a plurality of cells (Cells) for storing a plurality of information (Memory cell array),

In order to selectively access a specific cell among a plurality of cells for reading or writing, an input bus for providing a combined input to a plurality of logic gates and a plurality of logic gates connected to each of the plurality of cells ( Address decoder including an Input bus, and

Memory cell array,

Multiple open cells that can be accessed to read or write, and allow access to read or write only when a protection key signal is received. Consisting of a closed cell (Closed cell),

The address decoder,

Among the plurality of logic gates, only the logic gate connected to the closed cell is connected to configure a protection bus line for transmitting a protection key signal to the closed cell.

The present invention is connected to only a logic gate connected to a closed cell among a plurality of logic gates, and provides a protected bus line for transmitting a protection key signal to the closed cell, so that the closed cell can be accessed only by a specific user. Modification, damage or copying of a memory device or a semiconductor memory chip can be prevented.

1 is a diagram illustrating a semiconductor memory chip according to an embodiment.
2 is a diagram illustrating a memory cell array constituting a plurality of cells for storing a plurality of information according to an embodiment.
3 is a diagram illustrating an address decoder according to an embodiment.
4 is a diagram illustrating a protection bus line of an address decoder according to another embodiment.
5 is a diagram illustrating an address decoder to which the protection bus line of FIG. 4 is applied.
6 is a diagram for explaining a memory cell array and configuring a plurality of cells including closed spare cells for storing a plurality of information according to an embodiment.
7 is a diagram illustrating an address decoder according to another embodiment.
8 is a diagram illustrating a protection bus line of an address decoder according to another embodiment.

Hereinafter, the present invention will be described in detail so that those skilled in the art can easily understand and reproduce it through preferred embodiments described with reference to the accompanying drawings. In the description of the present invention, when it is determined that detailed descriptions of related known functions or configurations may unnecessarily obscure the subject matter of embodiments of the present invention, detailed descriptions thereof will be omitted. Terms used throughout the specification of the present invention are terms defined in consideration of functions in the embodiments of the present invention, and can be sufficiently modified according to the intention or custom of a user or operator, so the definition of these terms is general It should be made on the basis of the contents.

Also, the above-described and additional aspects of the invention will be apparent through the embodiments described below. It is to be understood that the features of the selectively described aspects or the selectively described embodiments in this specification can be freely combined with each other, unless it is obvious that it is not technically contradictory to those skilled in the art, unless otherwise indicated in the drawings. I understand.

Therefore, the configuration shown in the embodiments and drawings described in this specification is only one of the most preferred embodiments of the present invention and does not represent all of the technical spirit of the present invention, and thus can replace them at the time of application. It should be understood that there may be equivalents and variations.

1 is a diagram illustrating a semiconductor memory chip according to an embodiment. As illustrated, the semiconductor memory chip 1000 may include a semiconductor memory device 100 and a memory controller 200.

The semiconductor memory device 100 may include a memory cell array 110 and an address decoder 120. The semiconductor memory device 100 may be a nonvolatile or volatile memory device. That is, the semiconductor memory device 100 includes DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory), LPDDR (Low Power Double Data Rate) SDRAM, GDDR (Graphics Double Data Rate) SDRAM, RDRAM (Rambus Dynamic Random Access Memory), and the like. It may be a dynamic random access memory (Dynamic Random Access Memory, DRAM). However, the embodiments of the present invention need not be limited thereto, and as an example, a semiconductor memory device includes flash memory, magnetic RAM (MRAM), ferroelectric RAM (FeRAM), phase change RAM (PRAM), and ReRAM ( Resistive RAM).

The semiconductor memory device 100 may be a chip in which a nonvolatile memory device and a volatile memory device are packaged together, such as an embedded multi-chip package (eMCP).

The semiconductor memory device 100 receives the CLK (Clock) signal or the CS (Chip Select) signal, and the CMD (Command) signal and the address (ADD) signal from the memory controller 200 and stores the stored data in the memory controller 200. And provide specific data. The semiconductor memory device 100 may transmit and receive data through the memory controller 200 through one or more channels. The operation of the memory controller 200 may be controlled through communication with a host. The host may be manipulated by a user. The memory controller 200 may access (access) the semiconductor memory device 100 at the request of the host.

2 is a diagram illustrating a memory cell array constituting a plurality of cells for storing a plurality of information according to an embodiment. As illustrated, the memory cell array 110 may be formed of a grouped structure in which 16 (4 X 4) cells are arrayed. The number of cells may be smaller or larger than 16. The unit cell may mean a block. As shown, a specific cell (block) of the cell array is designated as row addresses RA0B, RA0, RA1B, RA0B, RA1 and column addresses CA0B, CA0, CA1B, CA0B, CA1, and specific address signals are input and specified The cell can be accessed.

The memory cell array reads or writes only when a plurality of open cells that are allowed to read or write and a protection key signal are received. To form a closed cell that is allowed access. As illustrated, Cell 0 is a closed cell, and the remaining 16 cells including Cell 3 and Cell B may be Open cells. Closed cells may be arbitrarily designated and may be plural.

In the closed cell, product specification information of manufacturer name, production information, capacity, or speed information may be stored. Product specification information may include firmware. Firmware may be needed more for memory devices including solid state drives (SSDs), USB, and UFS.

3 is a diagram illustrating an address decoder according to an embodiment. As shown, the address decoder (120, Address decoder) is a plurality of logic gates (Logic gates, 122, connected to each of the plurality of cells, in order to selectively read a specific cell of the plurality of cells to read or write) 123) and an input bus 126 for providing a combined input to a plurality of logic gates. The input bus may be a circuit configured as a plurality of channels to function as an independent signal transmission path (Circuit).

The address decoder has a plurality of output channels (0 to F) and is controlled by a combination of input signals. Among them, a specific output may be enabled. Among the plurality of logic gates, only a logic gate connected to the closed cell may be further included, and a protection bus line 121 for transmitting a protection key signal to the closed cell may be further included. Therefore, in order for output channel 0 to be activated, the address decoder can be controlled by an additional signal. Accordingly, it is possible to prevent a general user, not a specific user, from accessing the memory cell area (eg, DRAM) without the protection key information and replacing the memory device. The general user may mean any user who does not receive protection key signal generation information directly from the semiconductor memory device manufacturer, and includes, but is not limited to, a semiconductor memory module manufacturer, a system manufacturer, and a system user. A specific user is a person who properly knows the protection key information, and may include a semiconductor memory device manufacturer and a person who has acquired from the semiconductor memory device manufacturer (eg, a memory controller manufacturer).

In the address decoder according to another embodiment, the logic gate may be a NAND gate and a NOT gate connected in series, and may also be configured as an AND gate (not shown). Preferably, it can be composed of a NAND gate and a NOT gate because the address decoder can be designed with a minimum number of transistors. NAND gate can be constructed using 4 transistors and NOT gate can be designed using 2 transistors. The method for constructing the logic gate may be various, so it is not limited thereto. A plurality of NAND gates or AND gates may be connected in parallel. It is obvious to a person having ordinary skill in the art that various logic gates can be designed using a transistor.

The overall operating principle of the semiconductor memory device 100 may be described as follows based on FIGS. 1 to 3. For example, when "Low" signals are input to RA0, RA1, CA0, CA1, and the protection bus line 121, all of RA0B, RA1B, CA0B, and CA1B become "High" and are among the output channels 0 to F of the address decoder. The output channel 0 becomes “High”, and the remaining output channels 1 to F are all “Low”, so that only the cell 0 (Block 0) is selected to access the information stored in the cell 0. Therefore, in order to access the information of cell 0, a protection key signal must be separately input through the protection bus line 121, and the protection key signal can be arbitrarily made by a semiconductor memory device manufacturer. Similarly, if you specify cell A as a closed cell, you can install a guard bus line so that the guard key signal becomes the input signal of the NAND gate of output A.

The access operation to a specific cell may be at least one of Read, Write, or Refresh.

When the protective bus line is removed by the semiconductor memory device manufacturer, Cell 0 is no longer a closed cell and can be an open cell.

4 is a diagram illustrating a protection bus line of an address decoder according to another embodiment. As illustrated, the protection bus line 121 of the address decoder 120 may include a logic gate in which the NAND gate 124 and the NOT gate 125 are connected in series. The reason is that the protection bus line of the address decoder can be designed with the minimum number of transistors. NAND gates and NOT gates can be designed using transistors.

In an address decoder according to another embodiment, the NAND gate of the protection bus line includes an input terminal for receiving a CLK (Clock) signal or a CS (Chip Select) signal, an input terminal for receiving a CMD (Command) signal, and an address (ADD) An input terminal for signal reception may be provided. The protection key signal may be generated by a combination of a CLK (Clock) signal or a CS (Chip Select) signal and a CMD (Command) signal, an address (ADD) signal, and a data input/output signal. Or it can be generated by combining some of the signals. The protection key signal may be a mode register set (MRS).

The command signal may be divided into a read command signal and a write command signal, and may further include various refresh command signals to perform various access operations. Therefore, a high signal may be generated by a combination of a CLK or CS and command signal, which is an input signal of a semiconductor memory chip, and a combination of an address pin.

5 is a diagram illustrating an address decoder 120 to which the protection bus line of FIG. 4 is applied in an address decoder according to an embodiment. As illustrated, a protection bus line 121 in which the NAND gate 124 and the NOT gate 125 are connected in series may be added as an input to the NAND gate of the output channel 0 to perform the above-mentioned function. When the protective bus line is removed by the semiconductor memory device manufacturer, Cell 0 is no longer a closed cell and can be an open cell. A switch (not shown) may be added to disable the function of the protection bus line. This allows Cell 0 to be easily switched between open and closed cells.

The NAND gate of the protection bus line may include an input terminal for receiving a CLK (Clock) signal or a CS (Chip Select) signal, an input terminal for receiving a CMD (Command) signal, and an input terminal for receiving an address (ADD) signal.

The command signal may be divided into a read command signal and a write command signal, and may further include various refresh command signals to perform various access operations.

FIG. 6 is a diagram for explaining a memory cell array and configuring a plurality of cells including closed spare cells for storing a plurality of pieces of information according to an embodiment. As shown, the memory cell array 110 is composed of a plurality of open cells that are allowed access to read or write, and additional cells that store product specification information including firmware. It is possible to configure a closed spare cell that is allowed access to read or write only when a protection key signal is received. As shown, 16 (4 X 4) cells (Cells) and a closed spare cell (113, Closed spare cell) may be formed as an array (Architecture) to form an array (Array). The number of total cells (Cells) may be less than 17 or more. The unit cell may mean a block. The closed spare cell may be a dummy area or may be spatially separated from the open cell.

As shown, a specific cell (block) of the cell array is designated as row addresses RA0B, RA0, RA1B, RA0B, RA1 and column addresses CA0B, CA0, CA1B, CA0B, CA1, and specific address signals are input and specified The cell can be accessed. The closed spare cell 113 can be accessed through inputs of CA0B, CA1B, RA0B, and RA1B, which are shared inputs, and an input (not shown) of a protection key signal.

The memory cell array is composed of a plurality of open cells (112) that are accessible to read or write, and additional cells that store product specification information including firmware, and protect key signals ( Protection key signal) constitutes a closed spare cell (113) that is allowed access to read or write only when receiving. In the closed spare cell 113, product specification information of a manufacturer name, production information, capacity, or speed information may be stored. Product specification information may include firmware. Firmware may be needed more for memory devices including solid state drives (SSDs), USB, and UFS. The closed spare cell 113 may be an exclusive cell that stores only product specification information including firmware.

7 is a diagram illustrating an address decoder according to another embodiment.

As shown, the address decoder (120, Address decoder) is a plurality of logic gates (Logic gates, 122, connected to each of the plurality of cells, in order to selectively read a specific cell of the plurality of cells to read or write) 123) and an input bus 126 for providing a combined input to a plurality of logic gates. The input bus may be a circuit configured as a plurality of channels to function as an independent signal transmission path (Circuit).

The address decoder has an output channel for accessing the closed spare cell 113 in addition to a plurality of output channels (0 to F), and is configured by a logic gate and controlled by a combination of input signals. A protection bus line (121) for transmitting a protection key signal to the closed spare cell is connected to only the logical gate 127 of the protection bus line connected to the closed spare cell among the plurality of logic gates. It may further include. Therefore, in order for output channel 0 to be activated, the address decoder can be controlled by an additional signal. Accordingly, it is possible to prevent a general user, not a specific user, from accessing the memory cell area (eg, DRAM) without the protection key information and replacing the memory device. The general user may mean any user who does not receive protection key signal generation information directly from the semiconductor memory device manufacturer, and includes, but is not limited to, a semiconductor memory module manufacturer, a system manufacturer, and a system user. A specific user is a person who properly knows the protection key information, and may include a semiconductor memory device manufacturer and a person who has acquired from the semiconductor memory device manufacturer (eg, a memory controller manufacturer).

In the address decoder according to another embodiment, the logic gate may be a NAND gate and a NOT gate connected in series, and may also be configured as an AND gate (not shown). Preferably, it can be composed of a NAND gate and a NOT gate because the address decoder can be designed with a minimum number of transistors. NAND gate can be constructed using 4 transistors and NOT gate can be designed using 2 transistors. The logic gate may be configured in various ways. A plurality of NAND gates or AND gates may be connected in parallel.

In the address decoder according to another embodiment, as shown, a protection key signal and an inversed signal may be additionally provided as inputs of each logic gate. The inversed signal may be commonly input to channels other than the channel of the closed spare cell.

The overall operation principle of the semiconductor memory device 100 based on FIGS. 1, 6, and 7 may be described as follows. For example, when "Low" signals are input to RA0, RA1, CA0, CA1, and the protection bus line 121, all of RA0B, RA1B, CA0B, and CA1B become "High" and are among the output channels 0 to F of the address decoder. The output channel 0 becomes “High”, and the remaining output channels 1 to F are all “Low”, so that only the cell 0 (Block 0) is selected to access the information stored in the cell 0. However, in order to access the closed spare cell 113, a protection key signal must be separately input through the protection bus line 121, and the protection key signal can be arbitrarily made by a semiconductor memory device manufacturer. Accordingly, when the protection key signal is additionally input, the closed spare cell 113 may be accessed, otherwise, the cell 0 may be accessed.

8 is a diagram illustrating a protection bus line of an address decoder according to another embodiment. As illustrated, the protection bus line 121 of the address decoder 120 may include a logic gate in which the NAND gate 124 and the NOT gate 125 are connected in series. The reason is that the protection bus line of the address decoder can be designed with the minimum number of transistors. NAND gates and NOT gates can be designed using transistors. It is apparent to those skilled in the art that various logic gates can be designed using transistors.

In an address decoder according to another embodiment, the NAND gate of the protection bus line includes an input terminal for receiving a CLK (Clock) signal or a CS (Chip Select) signal, an input terminal for receiving a CMD (Command) signal, and an address (ADD) An input terminal for signal reception may be provided.

The protection key signal may be generated by a combination of a CLK (Clock) signal or a CS (Chip Select) signal and a CMD (Command) signal, an address (ADD) signal, and a data input/output signal. Or it can be generated by combining some of the signals. The protection key signal may be a mode register set (MRS).

In an address decoder according to another embodiment, a logic circuit of an address decoder may be designed such that a protection key signal and an inversed signal are additionally provided as inputs of each logic gate, as illustrated. have. The inversed signal may be commonly input to channels other than the channel of the closed spare cell.

The command signal may be divided into a read command signal and a write command signal, and may further include various refresh command signals to perform various access operations. Accordingly, a high signal may be generated by a combination of a CLK or CS and command signal, which is an input signal of a semiconductor memory chip, a combination of an address pin, and data input/output.

1000: semiconductor memory chip
100: semiconductor memory device
110: memory cell array
200: memory controller
120: address decoder
122, 123: logic gate
121: protection bus line
124: NAND gate
125: NOT gate
126: input bus
127: logic gate of the protection bus line

Claims (5)

A memory cell array constituting a plurality of cells for storing a plurality of information;
In order to selectively access and read or write a specific cell among a plurality of cells, an input bus for providing a combined input to a plurality of logic gates and a plurality of logic gates connected to each of the plurality of cells ( An address decoder including an input bus; And
Memory cell array,
Multiple open cells that can be accessed to read or write, and allow access to read or write only when a protection key signal is received. Consisting of a closed cell (Closed cell),
The address decoder,
A semiconductor memory device further comprising a protection bus line connected to only a logic gate connected to a closed cell among the plurality of logic gates to transmit a protection key signal to the closed cell. A memory cell array constituting a plurality of cells for storing a plurality of information;
In order to selectively access and read or write a specific cell among a plurality of cells, an input bus for providing a combined input to a plurality of logic gates and a plurality of logic gates connected to each of the plurality of cells ( An address decoder including an input bus; And
Memory cell array,
It consists of a plurality of open cells that can be accessed to read or write, and additional cells that store product specification information, including firmware, to receive a protection key signal. Construct a closed spare cell that is allowed access only to read or write,
The address decoder,
A semiconductor memory device further comprising a protection bus line connected to only a logic gate connected to a closed spare cell among the plurality of logic gates to transmit a protection key signal to the closed spare cell. According to claim 1,
The closed cell is a semiconductor memory device in which product specification information including firmware is stored. The method according to claim 1 or 2,
The protection key signal is a semiconductor memory device generated by a combination of a CLK (Clock) signal or a CS (Chip Select) signal and a CMD (Command) signal, an address (ADD) signal, and a data input/output signal. A semiconductor memory chip packaged with a memory controller that provides a CLK (Clock) signal or a CS (Chip Select) signal and a CMD (Command) signal and an address (ADD) signal to the semiconductor memory device of claim 1 or 2.

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