JP2004032357A - Sampling rate converter and receiver equipped therewith - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a sampling rate converter for preventing the generation of phase turning over noises and further to provide a receiver equipped with the same. <P>SOLUTION: In a register 11, an input sampling period T1, an output sampling period T2, and a normalization reference time width ΔT/T1 in which a reference time width ΔT serving as a reference for determining a plurality of input samples used for obtaining one output sample data by an interpolating process is normalized by T1, are established. A timing operation section 16 carries out an operation of the sampling timing of the output sample with respect to each output sample based on the periods T1 and T2. Regarding each output sample, a data operation section 21 derives the output sample data by performing the interpolating process by using every input sample data belonging to the region within an interpolating scope period having the same time width as the reference time width ΔT centering on the sampling timing of the output sample. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a sample rate converter for converting an input sample sequence into an output sample sequence having a different sample period, and a receiver using the same.
[0002]
[Prior art]
In various applications dealing with digital signals, sample rate converters are used. For example, a sample rate converter is used in a digital receiver.
[0003]
In a digital receiver, generally, data obtained by A / D conversion of an analog IF (intermediate frequency) signal at a certain sampling period is subjected to down-frequency conversion to generate a discrete baseband signal, and further, the base data is generated. The sample interpolation process is performed using a sample rate converter in order to resynchronize with a rate of an integral multiple (usually an exponential multiple of 2) of one or more carrier frequencies arranged in the band.
[0004]
At this time, if the sample rates are expressed in a relatively prime relationship, the conventional technique mainly implements the rate conversion by using a signal processing method called a polynomial interpolation filter. This applies not only to digital receivers but also to sample rate converters used in other devices.
[0005]
Here, FIG. 4 shows a relationship between input samples and output samples by the polynomial interpolation filter. FIG. 5 shows an example of a polynomial interpolation filter when the interpolation order N is 2. In FIG. 4, a _n-2 , A _n-1 , A _n , A _{n + 1} Is the input sample, X _n-2 , X _n-1 , X _n , X _{n + 1} Is the input sample a _n-2 , A _n-1 , A _n , A _{n + 1} , B is the output sample, X is the sampling timing of the output sample b, T is the input sample period, and μ is the offset time of the sampling timing of the output sample b from the immediately preceding input sample. In FIG. 5, 1 to 3 are interpolation coefficients, 4 and 5 are adders, 6 and 7 are multipliers, and Δ is a value μ / T1 obtained by normalizing the offset time μ with the input sample period T1.
[0006]
In the polynomial interpolation filter, an intermediate amount on each interpolation point is linearly obtained from a certain arbitrary and fixed (always constant) number of input samples.
[0007]
FIG. 6 shows the sampling timing of input samples when the order N of the interpolation equation is 3 and the conversion rate of the sample rate (= input sample period / output sample period) is 5/6 for the polynomial interpolation filter; FIG. 6 is a diagram illustrating a relationship between sampling timing of output samples and an interpolation processing range period of each output sample. Here, the interpolation processing range period of a certain output sample indicates that the data of the output sample is obtained by performing the interpolation process using the data of the input sample belonging to the period.
[0008]
FIG. 7 shows the sampling timing of input samples when the order N of the interpolation equation is 2 and the conversion rate of the sample rate (= input sample period / output sample period) is 5/6, for the polynomial interpolation filter; FIG. 6 is a diagram illustrating a relationship between sampling timing of output samples and an interpolation processing range period of each output sample.
[0009]
[Problems to be solved by the invention]
However, in the polynomial interpolation filter, as shown in FIG. 6, if the order of the interpolation equation is odd, the number of input samples becomes redundant near the time position of the input sample and the output sample on the cycle of the least common multiple. And a bias appears in the time range of the input sample viewed from the output sample position. Conversely, if it is an even number, the interpolation sequence becomes symmetrical with respect to the half cycle as shown in FIG. Artificial distortion due to topological aliasing noise is synthesized.
[0010]
In addition to the polynomial interpolation filter, interpolation using a polyphase filter bank is well known, but these have fundamentally the same problem as the case of the polynomial interpolation filter.
[0011]
Also, in the digital receiver, the rate conversion ratio is adaptively corrected so as to successively correct the synchronization deviation due to the relative original oscillation error between the transmitter and the receiver (frequency error between the reference oscillator of the transmitter and the reference oscillator of the receiver). May be fine-tuned. In this case, depending on the correction timing as the amount of adjustment at each time, there may be a case where the aliasing noise is instantaneously increased.
[0012]
The present invention has been made in view of such circumstances, and an object of the present invention is to provide a sample rate converter capable of suppressing occurrence of phase-like aliasing noise, and a receiver using the same.
[0013]
[Means for Solving the Problems]
In order to solve the above-mentioned problem, a sample rate converter according to a first aspect of the present invention comprises a first set value corresponding to an input sample period, and a second set value corresponding to a sample rate conversion rate or an output sample period. Setting value storage means for storing a third set value corresponding to a reference time width serving as a reference for determining a plurality of input samples to be effectively used for obtaining data of one output sample by interpolation processing; A sampling timing calculating means for calculating a sampling timing of the output sample for each output sample based on the first set value and the second set value; and a sampling timing of the output sample for each output sample. All the inputs belonging to the interpolation processing range period having a time width substantially the same as the reference time width centered on the timing. Using data of the sample, performing interpolation processing to obtain data of the output sample; anddata calculation means for obtaining the data of the output sample, for each of the output samples, the data of the output sample obtained by the data calculation means. , And outputs the output sample obtained at the timing according to the sampling timing.
[0014]
In the first aspect, the interpolation processing is performed using data of all input samples belonging to an interpolation processing range period having a time width substantially equal to the reference time width centered on the sampling timing of the output sample. . Therefore, for any of the output samples, the bias in the time range of the input sample used for interpolation of the output sample as viewed from the output sample position is reduced. Therefore, according to the first aspect, it is possible to suppress occurrence of phase-wise aliasing noise.
[0015]
A sample rate converter according to a second aspect of the present invention is the sample rate converter according to the first aspect, wherein at least one of the first to third set values can be changed to a different value at any time.
[0016]
According to the second aspect, since at least one of the first to third setting values can be changed to a different value at any time, the versatility is improved by appropriately changing the setting value according to the purpose of use and the like. be able to.
[0017]
The sample rate converter according to a third aspect of the present invention, in the first or second aspect, is configured such that the second set value is set to a value according to an external command. The rate can be adjusted.
[0018]
According to the third aspect, since the conversion rate of the sample rate can be adjusted, for example, in the digital receiver, the digital receiver is adaptively adapted to sequentially correct the synchronization deviation due to the relative original error between the transmitter and the receiver. Fine adjustment of the rate conversion ratio can be performed, which is preferable.
[0019]
The sample rate converter according to a fourth aspect of the present invention is the sample rate converter according to any one of the first to third aspects, wherein the number of input samples belonging to the interpolation processing range period or the order of the interpolation processing determined according to the number of input samples or A value corresponding to any of these, a value obtained by normalizing the offset time from the input sample immediately before the sampling timing of the output sample by the input sample cycle or an approximate value thereof, or a value corresponding to any of these. , A look-up table storing means for storing a set of interpolation coefficients indicating the contents of the interpolation processing according to the index value determined by the above-described first to third settings for each of the output samples. Based on the value of the input sample belonging to the interpolation processing range period for the output sample. Or a means for obtaining, as a first value, an order of the interpolation processing determined in accordance with the order or a value corresponding to any of the orders. The sampling timing calculating means, for each of the output samples, Means for obtaining, as a second value, a value obtained by normalizing the offset time from the immediately preceding input sample of the sampling timing by the input sample period or an approximate value thereof, or a value corresponding to any of these values. The calculating means obtains a set of interpolation coefficients for each of the output samples by referring to the look-up table in accordance with an index value determined by the first and second values obtained according to the output samples. And the data of the input samples belonging to the interpolation process range period for the output sample. By performing the product-sum operation between the, and obtains data of the output sample.
[0020]
According to the fourth aspect, since the interpolation processing is performed using the look-up table, the cost of the apparatus can be reduced, and the processing load associated with the interpolation processing can be reduced.
[0021]
A sample rate converter according to a fifth aspect of the present invention is the sample rate converter according to any one of the first to fourth aspects, further comprising a memory that can simultaneously read and write, wherein the data of each input sample is synchronized with an input sample clock. And for each of the output samples, data of input samples belonging to the interpolation processing range period for the output samples is read from the memory in synchronization with an output sample clock, and the data operation unit Uses the data of the read input sample in the interpolation processing.
[0022]
According to the fifth aspect, since the memory that can be read and written at the same time is used, the configuration of the device is simplified.
[0023]
A receiver according to a sixth aspect of the present invention is a receiver for receiving a signal modulated by a predetermined modulation scheme as a received signal, wherein the discrete local oscillator for generating a complex local carrier signal is provided based on the received signal. A multiplier for synthesizing a baseband signal by multiplying the intermediate frequency signal obtained and A / D converted at an arbitrary sample rate by a complex local carrier signal generated by the discrete local oscillator; A sample rate converter for converting the baseband signal output in synchronization with the sample rate from the baseband signal and resynchronizing the baseband signal to a baseband signal processing rate; Demodulation means for demodulating the data, and a sample period error or a sample rate error of the receiving side with respect to the transmitting side. A detection unit for detecting, and a control unit, wherein the sample rate converter is the sample rate converter according to any one of the first to fifth aspects, and the control unit includes an error detected by the detection unit. , A value that reduces the error is instructed, and this value is stored in the set value storage means as the second set value of the sample rate converter.
[0024]
According to the sixth aspect, feedback control based on the sample period error or the sample rate error of the receiving side with respect to the transmitting side can be realized, the sample period error and the like can be suppressed, and the bit error rate can be reduced. it can. At this time, if a conventional sample rate converter is used as the sample rate converter of the receiver, the above-mentioned aliasing noise is instantaneously increased depending on the amount of adjustment of the conversion rate of the sample rate at each time, and the error rate becomes higher. There can be a lot of situations where things go wrong. On the other hand, in the sixth aspect, since the sample rate converter according to any one of the first to fifth aspects is used, generation of phase-like aliasing noise is always performed regardless of the amount of adjustment at each time. Thus, the bit error rate can be stably reduced.
[0025]
The use of the sample rate converter according to the first to fifth aspects is not limited to a receiver, and can be applied to various uses.
[0026]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, a sample rate converter according to the present invention and a receiver using the same will be described with reference to the drawings.
[0027]
[First Embodiment]
[0028]
FIG. 1 is a schematic block diagram showing a sample rate converter according to a first embodiment of the present invention. FIG. 2 is a diagram illustrating an example of a relationship between the sampling timing of an input sample, the sampling timing of an output sample, and an interpolation processing range period, which is realized by the sample rate converter illustrated in FIG.
[0029]
First, before describing the configuration of the sample rate converter according to the present embodiment, an example shown in FIG. 2 will be described.
[0030]
In the example shown in FIG. 2, the conversion rate of the sample rate (= input sample period T1 / output sample period T2) is 5/6. A reference time width ΔT, which is a reference for determining a plurality of input samples to be effectively used for obtaining data of one output sample by interpolation processing, is set to the length shown in FIG. The interpolation processing range period of each output sample has the same time width as the reference time width ΔT, and the sampling timing of the output sample is determined to be the center of the interpolation processing range period. For example, the interpolation processing range period of the output sample D has the same time width as the reference time width ΔT, and the sampling point of the output sample D is at the center of the interpolation processing range period of the output sample D. Actually, in the present embodiment, the time resolution (resolution) is determined by an output clock signal to be described later, so that the time width of the interpolation processing range period exactly matches the reference time width ΔT. I can not say.
[0031]
As described above, the interpolation processing range period of a certain output sample indicates that the data of the output sample is obtained using the data of the input sample belonging to the period. For example, in the example shown in FIG. 2, since four input samples a4, a5, a6, and a7 belong within the interpolation processing range period of the output sample D, the data of the output sample D is all input samples a4, a5. , A6, a7 by performing an interpolation process. Therefore, the degree N of interpolation (= the number of input samples -1) when obtaining the data of the output sample D is 3. On the other hand, since three input samples a7, a8, and a9 belong to the interpolation processing range period of the output sample A ', the data of the output sample D is interpolated using the data of all these input samples a7, a8, and a9. It is obtained by performing processing. Therefore, the degree N of interpolation (= the number of input samples -1) when obtaining the data of the output sample A 'is 2.
[0032]
Thus, in the present embodiment, the interpolation processing range period of each output sample has the same time width as the reference time width ΔT, and the sampling timing of the output sample is determined to be the center of the interpolation processing range period. Therefore, the order N when the output sample data is obtained by the interpolation processing is different between the output sample A ′ and the output sample D. In this respect, the order N of interpolation is completely different from the case of FIGS. 6 and 7 in which the order N is always the same for all output samples. In the example shown in FIG. 2, the conversion rate is 5/6, and the relationship of 4 × 4/5 + 3 × １ ／ = 3.8 holds, so that four inputs to four outputs by tertiary interpolation are performed. And an output by secondary interpolation from three inputs is executed once, and the normalized reference time width ΔT / T1 is 3.8.
[0033]
According to the present embodiment, the interpolation processing is performed using the data of all input samples belonging to the interpolation processing range period having the same time width as the reference time width ΔT centered on the sampling timing of the output sample. Therefore, for any of the output samples, the bias of the sampling position of the output sample with respect to the sampling timing of the input sample used for interpolation of the output sample in time is reduced, and the phase distortion is not concentrated. This is clear from the comparison between FIG. 2 and FIGS. 6 and 7. Therefore, according to the present embodiment, it is possible to suppress the occurrence of phase-wise aliasing noise.
[0034]
Next, the configuration of the sample rate converter according to the present embodiment will be described with reference to FIG.
[0035]
The sample rate converter according to the present embodiment has a dual-port RAM 11 as a simultaneously writable memory. The write control circuit 12 operating in synchronization with the input clock signal controls the writing of the RAM 11, so that the input sample data is temporarily and sequentially stored in the RAM 11 from the writing port of the RAM 11. The input sample data once stored in this manner is read out from the RAM 11 by the read control circuit 13 which operates in synchronization with the output clock signal independent of the input clock signal, and is synchronized with the output clock signal for each output sample. As many as necessary for each interpolation calculation are read out. The elements surrounded by the dotted line in FIG. 1 operate in synchronization with the output clock signal.
[0036]
The register 14 serving as a set value storage unit stores the input sample period T1, the output sample period T2, and the normalized reference time width ΔT / T1 obtained by normalizing the reference time width ΔT with the input sample period T1. Is stored as In the present embodiment, these set values T1, T2, ΔT / T1 are configured to be changed to different values at any time by a processor or the like (not shown) operated by a program, and the output sample period T2 is set to an external value. And the conversion rate T1 / T2 can be adjusted. Needless to say, for example, the conversion rate T1 / T2 may be stored in the register 14 instead of the output sample period T2.
[0037]
Based on the input sample period T1 and the output sample period T2, the normalized offset time calculation unit 14 calculates, for each output sample, an offset time μ from the immediately preceding input sample at the sampling timing of the output sample in the input sample period T1. A normalized value (normalized offset time) Δ = μ / T1 is calculated. In the example shown in FIG. 2, for example, the normalized offset time calculation unit 14 calculates Δ = μ _C / T1 is calculated. Since the offset time μ of each output sample is uniquely determined depending on the input / output sample periods T1 and T2, the normalized offset time Δ can be calculated for each output sample from the input sample period T1 and the output sample period T2. . It should be noted that the temporal position at which the sampling timing of the output sample can be taken is not a continuous position in a continuous manner but a discrete position determined by the resolution of the output clock signal. Therefore, the normalized offset time calculation unit 14 obtains, as the normalized offset time Δ, a value (ie, an approximate value) rounded to an integral multiple of the minimum unit (or an integral multiple thereof) determined by the resolution.
[0038]
The read timing determination unit 15 sequentially receives the normalized offset time Δ for each output sample from the normalized offset time calculation unit 14, further uses the input sample period T1, and counts the output clock signal to obtain each output sample. A read timing signal is given to the read control circuit 13 at a timing corresponding to the sampling timing. As will be understood from the following description, in the present embodiment, a point in time after a predetermined number of clocks from the point in time of the read timing signal is set as the actual sampling timing of the output clock. The read control signal 13 gives a signal synchronized with the read timing signal to the normalized offset time calculator 14. In response to this signal, the normalized offset time calculation unit 14 calculates a normalized offset time Δ for the next output sample.
[0039]
As can be understood from the above description, in the present embodiment, the normalized offset time calculator 14 and the read timing determiner 15 determine the sampling timing of each output sample by using the input sample period T1 and the output sample period. A sampling timing calculation unit 16 that performs calculation based on T2 is configured.
[0040]
The interpolation order calculation unit 17 sequentially receives the normalized offset time Δ for each output sample from the normalized offset time calculation unit 14 and based on the normalized offset time Δ and the normalized reference time width ΔT / T1, The number of input samples belonging to the interpolation processing range period having the same (actually approximate) time width as the reference time width ΔT centered on the sampling timing of the output sample is obtained, and 1 is subtracted from the input sample number. Thus, the order N of the interpolation processing is obtained.
[0041]
The index generation unit 18 generates an index (pointer) determined by the normalized offset time Δ sequentially received from the normalized offset time calculation unit 14 and the order N sequentially received from the interpolation order calculation unit 17.
[0042]
Look-up table 20 is stored in memory 19 in advance. In the look-up table 20, the interpolation processing for obtaining the data of the output sample corresponding to the normalized offset time Δ indicated by the index by the interpolation processing of the order N based on the data of the input sample corresponds to each index. A set of interpolation coefficients (h _Δ (0), h _Δ (1), ..., h _Δ (N)) is stored. That is, the look-up table 20 uses the normalized offset time Δ and the interpolation order N as parameters via the index as a set of interpolation coefficients (h _Δ (0), h _Δ (1), ..., h _Δ (N)) is stored. For example, in the example shown in FIG. 2, the interpolation order is one of the second order and the third order, and if the normalized offset time Δ can take 128 values from the point of the temporal resolution, 2 A set of × 128 interpolation coefficients (h _Δ (0), h _Δ (1), ..., h _Δ (N)) is stored in advance.
[0043]
Then, from the look-up table 20, a set of interpolation coefficients (h _Δ (0), h _Δ (1), ..., h _Δ (N)) is read out and supplied to the data operation unit 21. That is, a set (h) of interpolation coefficients corresponding to the normalized offset time Δ sequentially obtained from the normalized offset time calculator 14 and the order N sequentially obtained from the interpolation order calculator 17. _Δ (0), h _Δ (1), ..., h _Δ (N)) are sequentially supplied to the data operation unit 21. Here, the set of interpolation coefficients supplied from the lookup table 20 to the data operation unit 21 is represented by (C ₀ , C ₁ , ..., C _N ).
[0044]
On the other hand, the read control circuit 13 sequentially receives the normalized offset time Δ for each output sample from the normalized offset time calculation unit 14, and performs sampling of the output sample based on the normalized offset time Δ and the interpolation order N. The address in the RAM 11 of the data of a plurality of input samples belonging to the interpolation processing range period having the same (actually approximate) time width as the reference time width ΔT centered on the timing is obtained, and the read timing determination unit In response to the read timing signal from the address 15, the data of the plurality of input samples is read from the address. Now, the data of a plurality of input samples being read from the RAM 11 is (V ₀ , V ₁ , ..., V _N ). In the example shown in FIG. 2, for example, for the output sample D, the data of the input samples a4, a5, a6, and a7 is read from the RAM.
[0045]
The data operation unit 21 reads out (V ₀ , V ₁ , ..., V _N ) And a set of interpolation coefficients (C ₀ , C ₁ , ..., C _N ) To perform interpolation processing and output data of the output sample. That is, the data operation unit 21 uses, for each output sample, data of all input samples belonging to an interpolation processing range period having the same time width as the reference time width ΔT centered on the sampling timing of the output sample. By performing the interpolation processing, data of the output sample is obtained. In the present embodiment, the data calculation unit 21 realizes this interpolation processing by referring to the lookup table 20. For example, the data calculation unit 21 directly executes the calculation by the interpolation formula without using the lookup table 20. It is also possible.
[0046]
In the present embodiment, the time interval from when the read timing determining unit 15 generates the read timing signal to when the data of the corresponding output sample is output is substantially the same for all output samples. It is configured so that
[0047]
The normalized reference time width ΔT / T1 may be set to an appropriate value. For example, when a value similar to the example shown in FIG. 2 is derived, [ΔT / T1 = (A × low order Side input sample number + B × the number of higher-order side input samples) / input sample period T1]. However, in this equation, A + B = input sample period T1, and A and B are both positive integers.
[0048]
With the above-described configuration, according to the present embodiment, for example, the operation as shown in FIG. 2 is realized, and as described above, an advantage is obtained in that the generation of the phase aliasing noise can be suppressed.
[0049]
Further, according to the present embodiment, since the interpolation processing is performed using the look-up table 20, the cost of the apparatus can be reduced, and the processing load associated with the interpolation processing can be reduced.
[0050]
Furthermore, according to the present embodiment, since the RAM 11 that can be read and written at the same time is used, the configuration of the device is simplified.
[0051]
[Second embodiment]
[0052]
FIG. 3 is a schematic block diagram showing a receiver according to the second embodiment of the present invention. The receiver according to the present embodiment is configured as a receiver that receives a signal modulated by the OFDM method.
[0053]
As shown in FIG. 1, the receiver according to the present embodiment includes an antenna 31, an RF tuner unit 32 that converts a band of a signal received by the antenna 31 to obtain an analog intermediate frequency signal, and an RF tuner unit 32. A / D converter 33 for performing A / D conversion on the intermediate frequency signal at an arbitrary sample rate, a discrete local oscillator 34 for generating a complex local carrier signal, and A / D converted by the A / D converter 33 A multiplier 35 for synthesizing a baseband signal by multiplying the intermediate frequency signal by a complex local carrier signal generated by a discrete local oscillator 34; and a baseband output from the multiplier 35 in synchronization with the sample rate. A sample rate converter 36 that converts the signal to a sample rate and resynchronizes with the baseband signal processing rate; A symbol synchronization detecting unit 37 for detecting a start position of a symbol valid period, a demodulating unit 38 for performing demodulation processing on the baseband signal subjected to the sample rate conversion to demodulate data, a frequency offset detecting unit 39, An error detection unit 40 and a host processor 41 such as a microcomputer are provided.
[0054]
The discrete local oscillator 34 and the multiplier 35 constitute band conversion means for performing band conversion (down conversion) of a received signal from an intermediate frequency to a base band. In the present embodiment, the discrete local oscillator 34 is configured so that the oscillation frequency can be sequentially changed.
[0055]
The processing of the discrete local oscillator 34 and the multiplier 55 is performed in synchronization with the sample rate of the A / D converter 23. The sample rate converter 36 absorbs a relative difference between the sample rate of the A / D converter 33 and the baseband signal processing rate. In the present embodiment, the sample rate converter 36 shown in FIG. 1 according to the above-described first embodiment is used as the sample rate converter 36. In the present embodiment, the input sample period T1 and the normalized reference time width ΔT / T1 are set by the host processor 41 in a programmable manner. Further, based on the output sample period T2 error detected by the sample period error detection unit 40, the host processor 41 obtains a value of the output sample period T2 such that the error is small, and uses this value of the sample rate converter 36. It is set in the register 14 (see FIG. 1).
[0056]
The frequency offset detector 39 detects a frequency offset on the receiving side with respect to the transmitting side based on the baseband signal output from the sample rate converter 26. As the frequency offset detection unit 39, for example, the one disclosed in JP-A-2001-136143 can be used.
[0057]
The discrete local oscillator 34 receives the frequency offset detection signal from the frequency offset detector 39, and adjusts the oscillation frequency so that the frequency offset becomes smaller.
[0058]
The demodulation unit 38 uses the synchronization detection signal from the symbol synchronization detection unit 37 to perform a fast Fourier transform on the baseband signal to separate a plurality of carriers included in the baseband signal individually. And a decoding unit 43 for decoding each carrier signal and returning the data to data.
[0059]
The sample period error detection unit 40 detects a sample period error of the reception side with respect to the transmission side based on the carrier signal separated by the FFT unit 42.
[0060]
According to the present embodiment, feedback control based on the sample period error of the reception side with respect to the transmission side is realized, the sample period error can be suppressed, and the bit error rate can be reduced. At this time, if a conventional sample rate converter is used as the sample rate converter 36 of the receiver, the aforementioned aliasing noise is instantaneously increased depending on the amount of adjustment of the conversion rate of the sample rate at each time, and the error rate is rather increased. There can be enough scenes. On the other hand, in the present embodiment, since the sample rate converter shown in FIG. 1 is used as the sample rate converter 36, it is possible to always suppress the generation of the phase aliasing noise regardless of the amount of adjustment at each time. Thus, the bit error rate can be stably reduced.
[0061]
The embodiments of the present invention have been described above, but the present invention is not limited to these embodiments.
[0062]
For example, the sample rate converter according to the present invention can be used for various applications other than a receiver.
[0063]
【The invention's effect】
As described above, according to the present invention, it is possible to provide a sample rate converter capable of suppressing the occurrence of phase aliasing noise, and a receiver using the same.
[Brief description of the drawings]
FIG. 1 is a schematic block diagram showing a sample rate converter according to a first embodiment of the present invention.
FIG. 2 is a diagram illustrating an example of a relationship between a sampling timing of an input sample, a sampling timing of an output sample, and an interpolation processing range period, which is realized by the sample rate converter illustrated in FIG. 1;
FIG. 3 is a schematic block diagram illustrating a receiver according to a second embodiment of the present invention.
FIG. 4 is a diagram showing a relationship between input samples and output samples by a polynomial interpolation filter.
FIG. 5 is a diagram illustrating an example of a polynomial interpolation filter.
FIG. 6 shows a relationship between a sampling timing of an input sample, a sampling timing of an output sample, and an interpolation processing range period of each output sample when the order is 3 and the conversion rate is 5/6 for the polynomial interpolation filter. FIG.
FIG. 7 shows the relationship between the sampling timing of an input sample, the sampling timing of an output sample, and the interpolation processing range period of each output sample when the order is 2 and the conversion rate is 5/6 for the polynomial interpolation filter. FIG.
[Explanation of symbols]
11 Dual port RAM
12 Write control circuit
13 Read control circuit
14 Normalized offset time calculation unit
15 Read timing decision unit
16 Sampling timing calculator
17 Interpolation order calculator
18 Index generator
19 Memory
20 Look-up table
21 Data operation unit

Claims (6)

A first set value corresponding to the input sample period, a second set value corresponding to the conversion rate of the sample rate or the output sample period, and a plurality of values to be effectively used for obtaining data of one output sample by interpolation processing Set value storage means for storing a third set value corresponding to a reference time width serving as a reference for determining the input sample of
Sampling timing calculating means for calculating a sampling timing of each output sample based on the first set value and the second set value;
For each of the output samples, an interpolation process is performed using data of all input samples belonging to an interpolation processing range period having substantially the same time width as the reference time width centered on the sampling timing of the output sample. By doing so, a data operation means for obtaining data of the output sample,
With
For each of the output samples, outputting the data of the output sample obtained by the data operation means at a timing corresponding to the sampling timing of the output sample obtained by the sampling timing operation means. Sample rate converter. 2. The sample rate converter according to claim 1, wherein at least one of said first to third set values can be changed to a different value at any time. 3. The sample rate converter according to claim 1, wherein the second set value is set to a value according to an external command, and the conversion rate can be adjusted. The number of input samples belonging to the interpolation processing range period, the order of the interpolation processing determined accordingly, or a value corresponding to any of these, and the offset time of the sampling timing of the output sample from the immediately preceding input sample A lookup table storing a set of interpolation coefficients indicating the contents of the interpolation processing according to an index value determined by a value normalized by the input sample period or an approximate value thereof, or a value corresponding to any of these values. Lookup table storage means for storing,
For each of the output samples, based on the first to third setting values, the number of input samples belonging to the interpolation processing range period for the output sample or the order of the interpolation processing determined in accordance with the number, or any of these. Means for determining a value according to the first or second value as a first value;
With
The sampling timing calculating means, for each of the output samples, is based on a value obtained by normalizing the offset time from the immediately preceding input sample of the sampling timing of the output sample to the input sample period or an approximate value thereof, or any one of them. Means for determining the value obtained as the second value,
The data calculation means obtains a set of interpolation coefficients for each of the output samples by referring to the look-up table according to an index value determined by the first and second values obtained according to the output samples. 4. The data of the output sample is obtained by performing a product-sum operation between the set of interpolation coefficients and the data of the input sample belonging to the interpolation processing range period for the output sample. The sample rate converter according to any one of the above. With memory that can be read and written at the same time,
The data of each input sample is temporarily held in the memory in synchronization with an input sample clock,
For each output sample, data of an input sample belonging to the interpolation processing range period for the output sample is read from the memory in synchronization with an output sample clock;
The sample rate converter according to claim 1, wherein the data operation unit uses the data of the read input sample for the interpolation processing. In a receiver that receives a signal modulated by a predetermined modulation method as a reception signal,
A discrete local oscillator for generating a complex local carrier signal;
Multiplication for synthesizing a baseband signal by multiplying an intermediate frequency signal obtained based on the received signal and A / D converted at an arbitrary sample rate by a complex local carrier signal generated by the discrete local oscillator Vessels,
A sample rate converter that converts the baseband signal output in synchronization with the sample rate from the multiplier and resynchronizes with the baseband signal processing rate;
Demodulation means for performing demodulation processing on the resynchronized baseband signal to demodulate data,
Detecting means for detecting a sample period error or a sample rate error of the receiving side with respect to the transmitting side,
A control unit;
With
The sample rate converter is a sample rate converter according to any one of claims 1 to 5,
The control unit instructs a value such that the error is reduced based on the error detected by the detection unit, and uses the value as the second set value of the sample rate converter. A receiver.

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