WO2004010624A1

WO2004010624A1 - Ofdm receiver

Info

Publication number: WO2004010624A1
Application number: PCT/KR2003/001430
Authority: WO
Inventors: Min-Soo Jung
Original assignee: Open Solution Co., Ltd.
Priority date: 2002-07-19
Filing date: 2003-07-18
Publication date: 2004-01-29
Also published as: AU2003281660A1; KR20040008872A

Abstract

A receiver for receiving modulated signals based on OFDM (Orthogonal Frequency Division Multiplexing) from a transmitter. The receiver for recovering the OFDM signals directly converts an intermediate band signal into a digital signal, and converts the digital signal into baseband signals after correcting a frequency error by means of a NCO (Numerically Controlled Oscillator) and a multiplier. The receiver corrects a clock error through Farrow filters after canceling out high frequency components by means of LPFs (Low Pass Filters). As a correlation between a timing recovery circuit and a frequency recovery circuit can be significantly reduced, an operation of the receiver can be stabilized.

Description

OFDM RECEIVER

Technical Field

The present invention relates to a European digital

TV transmission system, and more particularly to a receiver for receiving modulated signals based on OFDM (Orthogonal Frequency Division Multiplexing) from a transmitter.

Background Art

An OFDM (Orthogonal Frequency Division Multiplexing) scheme is a type of digital modulation scheme based on multiple carriers for use in digital audio broadcasting for mobile stations or terrestrial digital TV broadcasting that is widely used in Europe.

Many research workers conduct research on symbol timing and carrier frequency synchronization for an OFDM receiver. In order for the OFDM receiver to appropriately recover received data, the OFDM receiver must correctly search for an FFT (Fast Fourier Transform) window field and a sampling phase for A/D (Analog/Digital) conversion. In order for the OFDM receiver to correctly search for the FFT window field and the sampling phase for the A/D conversion, timing recovery and carrier frequency offset correction operations must first be carried out. A configuration necessary for carrying out the timing recovery and carrier frequency offset correction operations is shown in FIG. 1.

FIG. 1 is a block diagram illustrating a tuner and upstream digital circuits in accordance with a conventional

DVB-T (Digital Video Broadcasting-Terrestrial) OFDM receiver; and FIG. 2 is a view illustrating the detailed configuration of a polyphase filter shown in FIG. 1.

Referring to FIG. 1, the OFDM receiver includes three polyphase filters 102, 108 and 110, and has a structure in which a carrier frequency recovery loop is contained within a timing recovery loop.

In FIG. 1, an ADC (Analog-to-Digital Converter) 100 converts an analog IF (Intermediate Frequency) input signal outputted through a tuner and an IF processor into a digital signal .

In response to a ROM (Read Only Memory) address value addr 1 outputted from the first timing NCO (Numerically

Controlled Oscillator) 104, the first polyphase filter 102 converts the frequency of a sampled signal based on a sampling frequency f_s of the ADC 100 into a signal fτ_F operable in a clock frequency corresponding to twice a baseband sample rate, and performs a function of correcting a timing error. As shown in FIG. 2, the first polyphase filter 102 includes 31 delay devices (D) 101, 32 multipliers 103, look-up tables 105 for selecting filter tap coefficients and an adder 107. The polyphase filter acts as an interpolator.

The first timing NCO 104 generates the ROM address value addr 1 for selecting a look-up table of the first polyphase filter 102, and the ROM address value addr 1 is generated according to an error estimation value of a clock between a transmitter and a receiver that is outputted from a symbol timing recovery circuit 122.

The signal f_IF operable in a clock frequency corresponding to twice a baseband sample rate is down- converted into a real component signal I and an imaginary component signal Q based on a baseband by a down converter 106, and the down-converted signals are inputted into the second and third polyphase filters 108 and 110. In response to a ROM address value addr 2 outputted from the second timing NCO 112, the second and third polyphase filters 108 and 110 convert a real component f_IF signal and an imaginary component f_ΪF signal into f_Bβ signals based on a baseband sample rate, respectively, and then outputs the f_BB signals, respectively.

For reference, the reason why the OFDM receiver needs the three polyphase filters is because the DVB-T system uses three bandwidths of β, 7 and 8 MHz, and because the baseband sample rate is different according to bands. Thus, where the same sampling frequency for the ADC 100 is used irrespective of a bandwidth, signals FI with the same IF can be produced. If each signal FI endures operations of the first polyphase filter 102 and the down converter 106, the signal FI is converted into fτ_F signals F3 operable in a clock frequency corresponding to twice a baseband sample rate, and the f_IF signals F3 are inputted into the second and third polyphase filters 108 and 110. The second and third polyphase filters 108 and 110 convert the f_τF signals F3 operable in the clock frequency corresponding to twice the baseband sample rate into signals F4 operable in a baseband sample frequency f_BB, respectively. The baseband sample frequency f_BB = 48/7 MHz where a bandwidth is 6 MHz, the baseband sample frequency f_BB = 8.0 MHz where a bandwidth is 7 MHz, and the baseband sample frequency f_BB = 64/7 MHz where a bandwidth is 8 MHz. Look-up tables provided in the polyphase filters 2 and 3 contain information associated with baseband LPFs (Low Pass Filters) corresponding to three types of bands.

The second timing NCO 112 generates the address value addr 2 necessary for selecting look-up tables for the second and third polyphase filters 108 and 110, and can convert a signal operable in a sample rate of 18.28 MHz into a signal operable in a baseband sample rate of 48/7 MHz, 8.0 MHz or 64/7 MHz according to bands.

A complex multiplier 114 carries out a complex multiplication operation for sinusoidal wave signals SINE and COSINE outputted from an NCO 118 and the signals F4 outputted from the second and third polyphase filters 108 and 110, such that an offset cancellation operation for input signals is carried out. The complex multiplier 114 typically includes four multipliers, one adder and one subtracter.

The NCO 118 receives a value of the residual frequency offset estimated by a carrier frequency recovery circuit 120 to correct the frequency offset and then generates the sinusoidal wave signals SINE and COSINE with a center frequency of 0.0 Hz to output the generated sinusoidal wave signals SINE and COSINE.

Furthermore, an FFT (Fast Fourier Transform) processor 116 carries out an FFT operation for useful data duration of input signals, converts time domain signals into frequency domain signals, and outputs the frequency domain signals. An equalizer 124 compensates for signal distortion caused by a transmission channel.

Finally, the carrier frequency recovery circuit 120 estimates the residual frequency offset from outputs of the FFT processor 116, and outputs a value of the estimated residual frequency offset to the NCO 118. The NCO 118 converts the estimated residual frequency offset value into the sinusoidal wave signals SINE and COSINE. The sinusoidal wave signals SINE and COSINE are inputted into the complex multiplier 114. Since the carrier frequency recovery loop is contained within a timing recovery loop in the OFDM receiver, an operation of the timing recovery loop depends upon an operation of the carrier frequency recovery loop. In other words, the timing recovery loop is relatively longer than the carrier frequency recovery loop. When a sampling frequency error varies abruptly in this system, there is a problem in that a convergence rate may be slow since the carrier frequency recovery loop recovers the sampling frequency error using a carrier frequency error.

Furthermore, each polyphase filter shown in FIG. 1 must include a large number of multipliers and a large number of look-up tables for storing filter coefficient values as shown in FIG. 2. Since ROMs are needed to construct the look-up tables, there is another problem in that a large number of memories are unnecessarily needed.

Disclosure of the Invention

Therefore, the present invention has been made in view of the above problem, and it is one object of the present invention to provide an OFDM (Orthogonal Frequency Division Multiplexing) receiver, which can accelerate a convergence rate of a timing recovery loop, minimize a correlation between the timing recovery loop and a carrier frequency recovery loop, such that the OFDM receiver can stably operate.

It is another object of the present invention to provide an OFDM (Orthogonal Frequency Division Multiplexing) receiver, which can replace polyphase filters with simple structure-based interpolators, thereby simplifying the configuration of hardware.

It is yet another object of the present invention to provide an OFDM (Orthogonal Frequency Division Multiplexing) receiver including Farrow filters capable of improving a computation rate and reducing the complexity of hardware .

Brief Description of the Drawings

The above and other objects, features and other advantages of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which: FIG. 1 is a block diagram illustrating a conventional

DVB-T (Digital Video Broadcasting-Terrestrial) OFDM (Orthogonal Frequency Division Multiplexing) receiver;

FIG. 2 is a view illustrating the detailed configuration of a polyphase filter 102 shown in FIG. 1; FIG. 3 is a block diagram illustrating an OFDM receiver in accordance with the first embodiment of the present invention;

FIG. 4 is a view illustrating a signal spectrum outputted from an ADC (Analog-to-Digital Converter) 200 shown in FIG. 3;

FIG. 5 is a view illustrating a signal spectrum in accordance with the present invention;

FIG. 6 is a view illustrating the configuration of a Farrow filter provided in the OFDM receiver in accordance with the present invention;

FIG. 7 is a graph illustrating operation characteristics of the Farrow filter;

FIG. 8 is a block diagram illustrating an OFDM receiver in accordance with the second embodiment of the present invention;

FIG. 9 is a block diagram illustrating an OFDM receiver in accordance with the third embodiment of the present invention;

FIG. 10 is a block diagram illustrating an OFDM receiver in accordance with the fourth embodiment of the present invention; and

FIG. 11 is a view illustrating a Farrow filter usable in the embodiments of the present invention.

Best Mode for Carrying Out the Invention In accordance with an aspect of the present invention, the above and other objects can be accomplished by the provision of an OFDM (Orthogonal Frequency Division Multiplexing) receiver including a carrier frequency recovery circuit for estimating a residual frequency offset from outputs of an FFT (Fast Fourier Transform) processor and outputting a value of the estimated residual frequency offset, an NCO (Numerically Controlled Oscillator) for generating sinusoidal wave signals in response to the estimated residual frequency offset value outputted from the carrier frequency recovery circuit, and a symbol timing recovery circuit for estimating an error of a clock between a transmitter and a receiver from the outputs of the FFT processor and outputting a value of the estimated clock error, comprising: an ADC (Analog-to-Digital Converter) for converting an input OFDM IF (Intermediate Frequency) signal into a digital IF signal; an I/Q separator for multiplying the digital IF signal by the sinusoidal wave signals outputted from the NCO and outputting baseband complex digital sample signals in which a frequency offset is corrected;

LPFs (Low Pass Filters) for removing high frequency components from the baseband complex digital sample signals ( I and Q ) ; a timing NCO for outputting a timing adjustment signal value ( μ ) in response to the estimated clock error value; and Farrow filters for correcting timing errors of the baseband complex digital sample signals (I and Q) from which the high frequency components are removed in response to the timing adjustment signal value ( μ ) and carrying out an output operation. Now, preferred embodiments of the present invention will be described in detail with reference to the annexed drawings so that those skilled in the art can easily understand the present invention.

FIG. 3 is a block diagram illustrating an OFDM (Orthogonal Frequency Division Multiplexing) receiver in accordance with the first embodiment of the present invention; FIG. 4 is a view illustrating a signal spectrum outputted from an ADC (Analog-to-Digital Converter) 200 shown in FIG. 3; and FIG. 5 is a view illustrating a spectrum of a baseband signal outputted from an I/Q separator 202 and a spectrum of a signal with a center frequency 0 Hz remaining through LPFs (Low Pass Filters) 204 and 206 in accordance with the present invention.

Referring to FIG. 3, an OFDM IF (Intermediate Frequency) signal outputted through a tuner and an IF processor is sampled with a sampling frequency f_s by the ADC 200, such that the IF signal is converted into a digital signal. The digital signal is inputted into the I/Q separator 202. The sampling frequency is set to a predetermined value so that aliasing cannot be generated.

For reference, the DVB-T system uses two IF signals. The two IF signals include a primary IF signal of 36.125 MHz, 36.167 MHz or 36.15 MHz equal to a PAL signal, and a secondary IF signal of 4.57 MHz. In accordance with the embodiment of the present invention, the primary IF signal and the secondary IF signal (4.57 MHz) are sampled with the same sampling frequency. The input IF signal is sampled with a sampling frequency between 20.3475 MHz and 20.3685 MHz. Of course, a value of the sampling frequency can vary with systems .

Where the input IF signal is sampled with a sampling frequency between 20.3475 MHz and 20.3685 MHz in accordance with the present invention, a signal spectrum is shown in FIG. 4. Referring to FIG. 4, a digital signal located at the secondary IF signal being the center frequency is repeatedly generated every f_s.

The I/Q separator 202 multiplies the IF signal converted into the digital signal by sinusoidal wave signals SINE and COSINE outputted from an NCO 222, thereby outputting baseband complex digital sample signals I and Q containing high frequency components in which a carrier frequency offset is corrected. The I/Q separator 202 includes two multipliers.

For example, where an input signal of each multiplier is a(t) *cos (Wi*t) and output signals of the NCO 222 are cos (Wo*t) and sin(Wo*t), a real component corresponds to a(t)*cos(Wi*t)*cos(Wo*t) = a (t) /2*{cos ( (Wi - Wo)*t) + cos ( (Wi + Wo)t)} and an imaginary component corresponds to a(t)*cos(Wi*t)*sin(Wo*t) = a (t) /2*{-sin ( (Wi - Wo) *t) + sin((Wi + Wo)t)}. Here, Wi denotes an input frequency and Wo denotes an output frequency of the NCO 222. If a carrier frequency recovery circuit 220 carries out an estimation operation so that Wo = Wi, output signals of the two multipliers are described as in the following. Real component: cos (Wi*t) *cos (Wo*t) = a(t)/2*{l + cos(2Wit) }

Imaginary component: cos (Wi*t) *sin (Wo*t) = a(t) /2*sin(2Wit)

Thus, if the following LPFs cancel out high frequency components corresponding to 2Wi, baseband values can be produced.

On the other hand, the complex digital sample signals I and Q containing high frequency components outputted from the I/Q separator 202 are filtered by the LPFs 204 and 206, respectively. Thus, only baseband signals from which the high frequency components are removed are outputted.

Filter tap coefficients and the number of taps can be changed according to a bandwidth of 6, 7 or 8 MHz to be processed by the LPF. The LPF can be designed so that only the widest bandwidth of 8 MHz can be used. Where the signals from the I/Q separator 202 are outputted to the LPFs 204 and 206, a signal spectrum in the case where only baseband signals with a center frequency of 0 Hz are residual is shown in FIG. 5. For reference, the NCO 222 has the secondary IF as the center frequency, and generates sinusoidal wave signals corresponding to a value of the frequency offset outputted from the carrier frequency recovery circuit 220. The sinusoidal wave signals are used for generating the baseband complex digital sample signals I and Q that contain high frequency components as described above .

The baseband complex digital sample signals I and Q with the center frequency of 0 Hz are. inputted into the following first and second Farrow filters 208 and 210, respectively. The first and second Farrow filters 208 and 210 perform a function of correcting a timing error due to sample rate conversion in response to a value μ from the timing NCO 218. Each of the Farrow filters is configured by only three multipliers as shown in FIG. 6. Thus, the configuration of the Farrow filter is simpler than that of the conventional polyphase filter, and hence the configuration of the interpolator for correcting a timing error in the OFDM receiver can be simplified.

For reference, the Farrow filter will now be described in detail. Assuming that T_s and Ti denote an input signal interval and an output signal interval associated with the Farrow filter, respectively, (m-3)T_s, (m-2)T_s, ... , mT_s, ... , (m+2)T_s, (m+3)T_s denote input signals of the Farrow filter and (k-l)Ti, kTi, (k+l)Ti denote output signals of the Farrow filter as shown in FIG. 7. Thus, it can be seen that sampling rates for the input and output signals are different since values of T_s and Ti are different. In other words, if the timing NCO 218 outputs the value μ necessary for adjusting the value μ T_s being a difference between mT_s and kTi in response to an error estimation value of a clock between the transmitter and the receiver outputted from the symbol timing recovery circuit 216, a timing error due to the sample rate conversion can be corrected. The value μ necessary for correcting the timing error is 0 < μ < \ . The FFT processor 212 carries out an FFT operation for useful data duration of the input signal, converts a time domain signal into a frequency domain signal, and outputs the frequency domain signal. An equalizer 124 compensates for signal distortion caused by a transmission channel. The symbol timing recovery circuit 216 receives output signals of the FFT processor 212, estimates an error of a clock between the transmitter and the receiver, and outputs a value of the estimated clock error to the timing NCO 218 so that a symbol timing correction operation can be appropriately carried out.

Finally, the carrier frequency recovery circuit 220 estimates the residual frequency offset from an output of the FFT processor 212, and outputs a value of the estimated residual frequency offset to the NCO 222. Then, the I/Q separator 202 and the LPFs 204 and 206 carry out the frequency-offset correction operation.

In the OFDM receiver as described above, the ADC 200 converts an IF signal received and processed by an antenna and a tuner into a digital signal. The IF signal converted into the digital signal is multiplied with sinusoidal wave signals SINE and COSINE outputted from the NCO 222 by the I/Q separator 202, such that baseband complex digital sample signals I and Q in which the frequency offset is corrected are outputted. Since these complex digital sample signals I and Q contain high frequency components, the high frequency components of the complex digital sample signals I and Q are cancelled out by the LPFs 204 and 206, and only baseband signals are inputted into the first and second Farrow filters 208 and 210. The baseband signals without the high frequency components allow the symbol timing error due to sampling rate conversion to be corrected according to the value μ outputted from the timing NCO 218.

Thus, the OFDM receiver in accordance with the first embodiment of the present invention can accelerate the convergence rate of a symbol timing recovery loop and improve convergence characteristics of a carrier frequency recover loop, thereby stabilizing a system. Furthermore, as Farrow filters are adopted in place of polyphase filters, hardware complexity of the overall receiver can be simplified.

FIG. 8 is a block diagram illustrating an OFDM receiver in accordance with the second embodiment of the present invention. The OFDM receiver shown in FIG. 8 is the same as the configuration in which the LPFs 204 and 206 are removed from the OFDM receiver shown in FIG. 3. The reason why the OFDM receiver can appropriately correct carrier frequency and symbol timing offsets associated with received OFDM signals without the LPFs 204 and 206 shown in FIG. 3 is because the OFDM receiver shown in FIG. 8 can use the characteristics of Farrow filters 304 and 306.

A Farrow filter is primarily based on a SYNC function in a time domain, and is a rectangular-type filter in a frequency domain. Thus, if a tap coefficient for the Farrow filter is adjusted so that the Farrow filter can appropriately operate according to bandwidths, a symbol timing error correction operation can remove high frequency components from baseband complex digital sample signals I and Q.

FIG. 9 is a block diagram illustrating an OFDM (Orthogonal Frequency Division Multiplexing) receiver in accordance with the third embodiment of the present invention. The OFDM receiver shown in FIG. 9 further includes a coarse STR (Symbol Timing Recovery) circuit 320 as compared with the OFDM receiver shown in FIG. 3. The OFDM receiver shown in FIG. 9 produces a carrier frequency error value for the carrier recovery operation using complex digital sample data produced before the operation of an FFT (Fast Fourier Transform) processor 212 as well as output data of the FFT processor 212. Where the produced carrier frequency error value is used, the OFDM receiver has an appropriate structure designed so that a convergence rate can be enhanced.

In other words, the OFDM receiver shown in FIG. 9 has a structure capable of producing the value of a carrier frequency offset using data before the FFT operation and data after the FFT operation and correcting the carrier frequency error. The OFDM receiver can be designed so that the OFDM receiver estimates and compensates for a carrier offset using signals before the FFT operation at an initial system operation time, and the carrier frequency error can be compensated using signals corresponding to a result of the FFT operation after the system operation is stabilized. A carrier recovery algorithm based on the above-described structure is well known to those skilled in the art. The carrier recovery algorithm is classified into coarse carrier offset compensation and fine carrier offset compensation. In a comprehensive meaning, the coarse carrier offset compensation and fine carrier offset compensation are referred to as "carrier frequency recovery algorithms".

An operation of the coarse STR circuit 320 shown in FIG. 9 will now be briefly described. The coarse STR circuit 320 receives outputs of the Farrow filters 208 and 210 in which a timing error is corrected, makes a correlation between a guard interval and useful data duration, detects a frequency offset from maximum symbol accumulation values of real and imaginary components, and outputs a value of the detected frequency offset to a carrier frequency recovery circuit 220. A carrier frequency offset correction operation can thus be carried out at a rapid convergence rate.

FIG. 10 is a block diagram illustrating an OFDM (Orthogonal Frequency Division Multiplexing) receiver in accordance with the fourth embodiment of the present invention. The OFDM receiver shown in FIG. 10 further includes a coarse STR (Symbol Timing Recovery) circuit 320 as compared with the OFDM receiver shown in FIG. 8.

The OFDM receiver shown in FIG. 10 includes the coarse STR circuit 320 for rapidly correcting a carrier frequency error as in the OFDM receiver shown in FIG. 9. Furthermore, the OFDM receiver shown in FIG. 10 includes Farrow filters 304 and 306 without LPFs (Low Pass Filters) as in FIG. 8. If the Farrow filters 304 and 306 in accordance with the fourth embodiment of the present invention adjust tap coefficients thereof so that the Farrow filters can appropriately operate according to bandwidths as the LPFs, a symbol timing error compensation operation can remove high frequency components from baseband complex digital sample signals I and Q.

The coarse STR circuit 320 receives outputs of the Farrow filters 208 and 210 in which a timing error is corrected, makes a correlation between a guard interval and useful data duration, detects a frequency offset from maximum symbol accumulation values of real and imaginary components, and outputs a value of the detected frequency offset to a carrier frequency recovery circuit 220. A carrier frequency offset correction operation can thus be carried out at a rapid convergence rate.

FIG. 11 is a view illustrating a configuration of the above-described Farrow filter 304 capable of being used in the embodiments of the present invention. Since a conventional Farrow filter has four taps having tap coefficients of irrational numbers 1/3 and 1/6, there is a drawback in that hardware configuration for an irrational number computation operation is complex. For this reason, a new Farrow filter is designed in accordance with the present invention so that the tap coefficients of the Farrow filter can be simplified and at least one common computation operation can be shared. The configuration of the new Farrow filter is shown in FIG. 11. Where x(n) is an input of the Farrow filter, an output y(n) is given by the following Equation 1.

Equation 1 y(n) = B₃ (n)μ³ + B₂ (ή)μ² + B (n)μ + B₀ (n)

In the above Equation 1, B_n (n = 0, 1, 2, 3) is produced by the following Equation 2.

Equation 2

1 1 1 1 B₃ (ή) =—x(ή) x(n-1) +— x(n -2) — x(n-3)

B₂ (ή) = —x(n-1) - x(n-2) + —x(n -3)

J5_j (ή) =— x(n) + x(n -1) — x(n -2) — x(n -3) 6 2 6

B_Q (ή) = x(n - 2)

As apparent from B_n (n = 0, 1, 2, 3) produced by the above

Equation 2, there are four taps with tap coefficients of an irrational number 1/6. In this case, as a bit resolution associated with the irrational number 1/6 increases, a bit resolution associated with a multiplier increases.

To overcome this drawback, the present invention modifies the output y(n) as in the following Equation 3 so that a 1/6 computation operation can be performed once. Consequently, an overall operation of the new Farrow filter can be equally implemented as in the conventional Farrow filter.

Equation 3

y(ή) = 6[B₃(n)μ³ + B₂(n)μ² + B_λ(n)μ + B₀(n)]^ o

Where B_n is changed in the above Equation 3, the following Equation 4 is produced.

Equation 4

B₃ (ή) = 6B₃ (ή) = x(ή) - 3x(n -1) + 3x(n - 2) - x(n - 3)

= x(ή) —x_l + x₂ — x(n - 3) B₂ (n) = 6B₂ (ή) = 3x(n - 1) - 6x(n - 2) + 3x(n - 3) = x_λ -

+ x₃ B_λ (ή) = 6B (ή) = - x(ή) + 6x(n - 1) - 3x(n - 2) - x(n — 3)

= - x(ή) + 2x - x₂ + x(n - 3) B₀ (n) = 6B₀ (ή) = 6x(n — 2) = x₂

Furthermore, x , x₂ , x₃ and x₂ shown in the above Equation 4 are produced by the following Equation 5. Equation 5 C_j = 3x(n -V) x₂ = 3x(n - 2) x₃ = 3x(n —3) x₂ = Zx₂

Thus, B_n can be changed to simple tap coefficients as in the above Equation 4, part of a common computation operation can be shared as in x_x , x₂ , x₃ and x₂ , and computation operations associated with parts multiplied by 3 can be simplified since the parts multiplied by 3 can be made in the form of "(1 + 2 ) " as in x_λ , x₂ and x₃ .

The Farrow filter shown in FIG. 11 in accordance with the embodiment of the present invention can use common computation operations, set tap coefficients to "1" and "2", and carry out a 1/6 computation operation only one time, such that the computation operation can be carried out at a high rate and hardware complexity can be reduced.

Industrial Applicability

As apparent from the above description, the present invention can minimize a correlation between a timing recovery loop and a carrier frequency recovery loop while accelerating the convergence rate of a timing recovery loop, thereby improving the stability of a system.

Further, the present invention can simplify the configuration of hardware by replacing polyphase filters used as interpolators for correcting a timing error with simple structure-based Farrow filters, and is applicable to a receiver of a system adopting an OFDM (Orthogonal Frequency Division Multiplexing) method similar to a DVB-T (Digital Video Broadcasting-Terrestrial) system such as an ADSL (Asymmetric Digital Subscriber Line) , WLAN (Wireless Local Area Network) , etc.

Furthermore, the present invention can provide Farrow filters capable of using common computation operations, setting tap coefficients to "1" and "2", and carrying out a 1/6 computation operation only one time, such that an operation rate can be rapid and hardware complexity can be reduced. Although the preferred embodiments of the present invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope of the invention. Accordingly, the present invention is not limited to the above-described embodiments, but the present invention is defined by the claims which follow, along with their full scope of equivalents.

Claims

Claims :

1. An OFDM (Orthogonal Frequency Division

Multiplexing) receiver including a carrier frequency recovery circuit for estimating a residual frequency offset from outputs of an FFT (Fast Fourier Transform) processor and outputting a value of the estimated residual frequency offset, an NCO (Numerically Controlled Oscillator) for generating sinusoidal wave signals in response to the estimated residual frequency offset value outputted from the carrier frequency recovery circuit, and a symbol timing recovery circuit for estimating an error of a clock between a transmitter and a receiver from the outputs of the FFT processor and outputting a value of the estimated clock error, comprising: an ADC (Analog-to-Digital Converter) for converting an input OFDM IF (Intermediate Frequency) signal into a digital IF signal; an I/Q separator for multiplying the digital IF signal by the sinusoidal wave signals outputted from the NCO and outputting baseband complex digital sample signals in which a frequency offset is corrected;

LPFs (Low Pass Filters) for removing high frequency components from the baseband complex digital sample signals (I and Q) ; a timing NCO for outputting a timing adjustment signal value ( μ ) in response to the estimated clock error value; and

Farrow filters for correcting timing errors of the baseband complex digital sample signals (I and Q) from which the high frequency components are removed in response to the timing adjustment signal value ( μ ) and carrying out an output operation.

2. The OFDM receiver as set forth in claim 1, wherein the ADC uses a sampling frequency between 20.3475 MHz and 20.3685 MHz, and wherein the LPFs sets tap coefficients and the number of taps according to bandwidths of input OFDM signals .

3. The OFDM receiver as set forth in claim 1, further comprising: a coarse symbol timing recovery circuit for receiving outputs of the Farrow filters in which the timing errors are corrected, making a correlation between a guard interval and useful data duration, detecting a frequency offset from maximum symbol accumulation values of real and imaginary components, and outputting a value of the detected frequency offset to the carrier frequency recovery circuit.

4. The OFDM receiver as set forth in claim 1 or 3, wherein the Farrow filters are designed so that an output y(n) is produced by an equation when an input is x(n), the equation being:

y(ή) = 6[B₃(ή)μ³ + B₂(n)μ² + B_x(ή)μ + B₀(n)]- ,

6

wherein

B₃ (ή) = 6 B₃ (ή) = x(ή) - 3x(n — 1) + 3x(n - 2) - x(n -3) - x(ή) - x_λ + x₂ — x(n - 3), B₂(ή) = 6B₂( ) = 3x(n-V) - 6x(n-2) + 3x(n -3) = x_l - x₂ + x₃, .δ_j (n) = 6 B_x (ή) = - x(ή) + 6x(n — 1) - 3x(n - 2) - x(n - 3) = - x(ή) + 2x_λ — x₂ + x(n - 3) and B₀ ( ) = 6B₀ ( ) = 6x(n -2) = x₂, and wherein _j = 3x(n — 1), x₂ - 3x(n - 2), x₃ = 3x(n - 3) and x₂ = 2x₂.

5. An OFDM (Orthogonal Frequency Division Multiplexing) receiver including a carrier frequency recovery circuit for estimating a residual frequency offset from outputs of an FFT (Fast Fourier Transform) processor and outputting a value of the estimated residual frequency offset, an NCO (Numerically Controlled Oscillator) for generating sinusoidal wave signals in response to the estimated residual frequency offset value outputted from the carrier frequency recovery circuit, and a symbol timing recovery circuit for estimating an error of a clock between a transmitter and a receiver from the outputs of the FFT processor and outputting a value of the estimated clock error, comprising: an ADC (Analog-to-Digital Converter) for converting an input OFDM IF (Intermediate Frequency) signal into a digital IF signal; an I/Q separator for multiplying the digital IF signal by the sinusoidal wave signals outputted from the NCO and outputting baseband complex digital sample signals (I and Q) in which a frequency offset is corrected; a timing NCO for outputting a timing adjustment signal value ( μ ) in response to the estimated clock error value; and

6. The OFDM receiver as set forth in claim 5, further comprising: a coarse symbol timing recovery circuit for receiving outputs of the Farrow filters in which the timing errors are corrected, making a correlation between a guard interval and useful data duration, detecting a frequency offset from maximum symbol accumulation values of real and imaginary components, and outputting a value of the detected frequency offset to the carrier frequency recovery circuit .

7. The OFDM receiver as set forth in claim 5 or 6, wherein the Farrow filters are designed so that an output y(n) is produced by an equation when an input is x(n), the equation being:

y(ή) = 6[B₃(n)μ³ + B₂(n)μ² + B_λ(n)μ + ,

wherein

B₃ (ή) = 6B₃ (ή) = x(ή) - 3x(n - 1) + 3x(n - 2) - x(n — 3) = x(ή) - x + x₂ - x(n - 3), B₂(ή) = 6B₂(ή) = 3x(n-\) - 6x(n-2) + 3x(n-3) - x_λ - x₂ + x₃, B (n) = 6B_X (ή) = - x(ri) + 6x(n - 1) - 3x(n - 2) - x(n - 3) = - x(ή) + 2x - x₂ + x(n - 3) and B₀ (ή) = 6B₀ (ή) = 6x(n — 2) = x₂, and wherein x_x = 3x(n - 1), x₂ = 3x(n - 2), x₃ = 3x(n - 3) and x = 2x₂.