JP2004031996A - Wiring board and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a wiring board which improves a connecting accuracy of an electronic part by substantially equalizing diameters of top faces of flattened solder bumps irrespective of the presence or absence of a solid layer, and to provide a method for manufacturing the same. <P>SOLUTION: The method for manufacturing the board 1 comprises a solder paste printing step of coating a plurality of pads 22 opened on a main surface 2 side with solder pastes, a reflowing step of forming a substantially semispherical solder bump by melting the coated solder paste, and a flattening step of forming the flattened solder bump 25 by pressing a top of the substantially semispherical solder bump by a flat pressing surface. In the solder paste printing step, the first pad 22B is coated with a smaller amount of the solder paste than a second pad 22C according to whether the pad 22 is the first pad 22B formed with the solid layer 21 on a region to which oneself is projected to a rear surface side via one or a plurality of resin insulating layers or not, or whether the pad 22 is the second pad 22C in which the solid layer 21 does not exist on a region in which oneself is projected on the rear surface side or not. <P>COPYRIGHT: (C)2004,JPO

Description

{Circle over (1)} The present invention relates to a wiring board having flattened solder bumps in which the top surfaces of the solder bumps protruding toward the main surface are flattened, and a method of manufacturing the same.

Conventionally, as an example of a wiring substrate having a resin insulating layer and a conductor layer of a predetermined pattern formed thereon, a substrate 101 shown in FIG. This substrate 101 includes a core substrate (resin insulating layer) 103 at the center thereof. One or a plurality of resin insulating layers 105 are laminated on both surfaces of the core substrate 103, and a solder resist layer (resin insulating layer) 107 is laminated on the outside thereof to form a main surface.

A plurality of substantially cylindrical through-hole conductors 111 penetrating the core substrate 103 are formed at predetermined positions, and the inside of the core substrate 103 is filled with a resin filling material 112. In the resin insulating layer 105, a plurality of via through holes 113 penetrating therethrough are formed at predetermined positions, and a via conductor 115 is formed in each via through hole 113. In the solder resist layer 107, a plurality of pad openings 117 that penetrate the solder resist layer 107 and expose the pads 116 on the bottom surface are formed at predetermined positions. Further, a first conductor layer 118 having a predetermined pattern such as a wiring or a pad is formed between the core substrate 103 and the resin insulation layer 105, and a through-hole conductor 111 of the core substrate 103 and a via conductor 115 of the resin insulation layer 105 are formed. Is connected to Further, a second conductor layer 119 having a predetermined pattern such as a wiring and a pad is formed between the resin insulating layer 105 and the solder resist layer 107, and is connected to the via conductor 115. When a plurality of resin insulation layers 105 are stacked, a conductor layer is also formed between the plurality of resin insulation layers 105.

(4) On the pads 116 formed on the solder resist layer 107 of the substrate 101, bumps raised by solder, gold, or the like are formed as terminals for electrical connection. Further, in order to ensure connection with electronic components (for example, IC chips, chip capacitors, chip resistors, etc.) mounted on the substrate 101, the top surfaces of the respective bumps are flattened by flat pressing surfaces, and Solder bumps 120 are formed.

However, in such a substrate 101, a resin having a substantially uniform thickness is used as the resin insulating layer 105. Therefore, the portion of the resin insulating layer 105 where the wiring and the pattern are formed in the first conductive layer 118 and the second conductive layer 119 between the layers is in a slightly raised state. When the resin insulating layer 105 is formed, the surface is smoothed to some extent because pressing is performed while heating. However, for example, as shown in FIG. 6, the resin insulating layer 105 formed on the portion where the solid layer 121 which spreads with a certain area as a part of the first conductor layer 118 is formed It is inevitable that the state will be slightly raised compared to other parts. Therefore, the first pad 116B provided in the area where the solid layer 121 is projected on the main surface side is formed at a relatively raised position as compared with the second pad 116C in the other area. .

Therefore, even if the solder bumps 122B formed on the first pad 116B and the solder bumps 122C formed on the second pad 116C have the same size as shown by the dotted line in FIG. Somewhat different. By pressing these solder bumps 122B and 122C with the same flat pressing surface 123 and flattening, the respective top surfaces are pressed to the pressing surface 123, and the first flattening solder bump 120B and the second flattening solder bump 120C are formed. Is formed. That is, the amount of the solder crushed for flattening differs by the difference in the position of the top surface, and the diameter M1 of the top surface of the flattened solder bump 120B is compared with the diameter M2 of the top surface of the flattened solder bump 120C. Then it gets bigger. As a result of the measurement, it was found that the difference in the diameter of the top surface of the flattened solder bump 120 was about 10 μm even when the difference in height between the pad positions was 2 to 3 μm.

The connection terminals of the electronic components mounted on the substrate 101 are formed very uniformly, whereas the diameter of the top surface of the flattening solder bump 120 of the substrate 101 is different, so that the When mounting components or the like, the connection accuracy sometimes varies.

The present invention has been made in view of such a situation, and a wiring board having improved connection accuracy with an electronic component by making the diameter of the top surface of a flattening solder bump substantially equal regardless of the presence or absence of a solid layer. And a method for producing the same.

The solution is a method of manufacturing a wiring board having a plurality of flattened solder bumps having a main surface and a back surface, protruding toward the main surface, and each having a top surface flattened. A solder paste printing step of applying a solder paste to each of the plurality of pads, wherein the plurality of pads are formed with a solid layer via one or a plurality of resin insulating layers in a region where the plurality of pads are projected on the back surface side. A first pad, and a second pad having no solid layer in a region where the self-projection is projected on the back surface side. The first pad is coated with a smaller amount of the solder paste than the second pad. A solder paste printing step of applying, a reflow step of dissolving the applied solder paste to form a substantially hemispherical solder bump, and pressing a top of the substantially hemispherical solder bump with a flat pressing surface. A method of manufacturing a wiring board and a planarization step of forming the flattening solder bumps with.

According to the present invention, a solder paste is applied to a plurality of pads opened on the main surface side. Next, the applied solder paste is dissolved to form a substantially hemispherical solder bump. Thereafter, the top of the solder bump is pressed with a flat pressing surface to form a flattened solder bump. Among these, in the solder paste printing step of applying a solder paste, the pad to be applied is divided according to whether or not a solid layer is formed in a region where the self is projected on the back surface side, and a solid layer is formed. A smaller amount of solder paste is applied to the first pad than to the second pad on which no solid layer is formed.

Generally, the thickness of the entire wiring board is relatively thick in a portion where a solid layer is formed between layers as compared with a portion where a solid layer is not formed. Therefore, when flattening is performed on the flat pressing surface, the distance between the first pad and the pressing surface is smaller than the distance between the second pad and the pressing surface. That is, the height of the solder bump from the pad after the planarization process is lower in the first pad than in the second pad. Therefore, when the same amount of solder paste is applied to the first pad and the second pad, the flattened solder bump formed on the first pad is pressed lower than in the case of the second pad. The diameter of the surface is larger than the diameter of the top surface of the flattened solder bump formed on the second pad.

On the other hand, in the present invention, the amount of the solder paste applied to the first pad is smaller than that of the solder paste applied to the second pad. Therefore, the size of the solder paste formed on the second pad is smaller than that of the solder bump formed on the second pad. The size of the solder bump is smaller. Accordingly, the difference between the diameter of the top surface of the second flattened solder bump and the diameter of the top surface of the first flattened solder bump can be reduced. Therefore, when the electronic component is mounted on the wiring board later, the difference between the first pad and the second pad due to the presence or absence of the solid layer can be reduced with respect to the connection state between the electronic component and the connection terminal.

The material of the resin insulating layer may be any resin having an insulating property, such as an epoxy resin or a BT resin. Further, a composite material of a resin such as a glass fiber or a ceramic powder and a resin such as a glass-epoxy composite material is also included. The solid layer is a conductor layer provided between layers of the resin insulating layer, and is a portion having a certain area and extending between the layers. The metal forming the solder bumps may be appropriately selected according to the material of the connection terminals and the like of the electronic component to be mounted. Pb-Sn based solders such as 90Pb-10Sn, 95Pb-5Sn, and 40Pb-60Sn may be used. Examples of the solder include Sn-Sb solder, Sn-Ag solder, Sn-Ag-Cu solder, Au-Ge solder, and Au-Sn solder. The pressing surface is formed as a flat surface by a metal material such as a steel material or a ceramic material.

Furthermore, there are various types of pads. For example, there are a pad-on via in which a pad is provided directly above a via, and a pad-off via in which a pad is not located directly above a via. These may be mixed in the same wiring board. Examples of the form of the via include a filled via in which the inside of the via is filled with plating and the upper surface is flat, and an unfilled via which is not completely filled and has a dent at the center.

形態 These forms must be considered when determining the amount of solder paste to be applied to the pad. For example, there is a difference between a pad-on via and a pad-off via in an unfilled via. Further, depending on the wiring board, the area (opening size) of the pad may be different. Therefore, in the present invention, when one wiring board has pads of different forms and dimensions, it is necessary to compare the first and second pads of the same form and dimensions. In other words, it is necessary to have the first pad and the second pad having the same form and size as the first pad without a solid layer in the region where the self is projected on the back surface side.

Further, in the above-described method for manufacturing a wiring board, the flattening step may include a step of: determining a diameter of a top surface of a first flattening solder bump formed on the first pad, and a second flattening shape formed on the second pad. It is preferable to provide a method of manufacturing a wiring board including a flattening step of forming a flattened solder bump having substantially the same diameter as the top surface of the solder bump.

According to the present invention, in the flattening step, the diameter of the top surface of the first flattening solder bump formed on the first pad and the diameter of the top surface of the second flattening solder bump formed on the second pad are: Almost equal. Therefore, when the electronic component is mounted on the wiring board later, the connection state between the electronic component and the connection terminal can be made substantially uniform between the first pad and the second pad.

Further, in the above-described method for manufacturing a wiring board, the print mask used in the solder paste printing step may be such that the diameter of the first through hole corresponding to the first pad is equal to the second transparent hole corresponding to the second pad. It is preferable to use a method for manufacturing a wiring board smaller than the diameter of the hole.

According to the present invention, in the solder paste printing step, the diameter of the through-hole provided in the print mask is formed smaller for the first pad than for the second pad. Therefore, even if the solder paste is applied in the same manner, the amount of the solder paste transmitted through the pad is smaller in the first pad than in the second pad. Therefore, the difference in the diameter of the top surface of the flattened solder bump due to the presence or absence of the solid layer can be reduced, so that the difference in the connectivity between the first pad and the second pad can be reduced.

Furthermore, if the diameter of the top surface of the flattened solder bumps can be made substantially equal regardless of the presence or absence of the solid layer, when mounting the electronic component on this wiring board later, regarding the connection state with the connection terminal of the electronic component, It is more convenient because the first pad and the second pad can be made substantially uniform.

Note that the print mask only needs to be provided with a through-hole for transmitting the solder paste, and for example, a metal mask having a hole in a metal plate such as a stainless steel plate or a screen mask is used.

Still another solution is a wiring board having a plurality of flattened solder bumps having a main surface and a back surface, protruding toward the main surface, and each having a top surface flattened, and having an opening on the main surface. A first pad in which a solid layer is formed via one or more resin insulating layers in a region where the self is projected on the back surface side, and a solid pad is formed in a region where the self is projected on the back surface side; A second pad having no layer, a diameter of a top surface of the first flattening solder bump formed on the first pad, and a diameter of a top surface of the second flattening solder bump formed on the second pad. The wiring board has a diameter substantially equal to that of the wiring board.

In the wiring board of the present invention, the diameter of the top surface of the solder bump formed on the plurality of pads opened on the main surface side is independent of whether or not a solid layer is formed in a region where the pad is projected on the back surface side. , Almost equal. Therefore, when the electronic component is mounted on the wiring board later, the connection state between the electronic component and the connection terminal can be made substantially uniform between the first pad and the second pad.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. First, an outline of the wiring board according to the present embodiment will be described.
FIG. 1 shows a partially enlarged cross-sectional view of the main surface 2 side of the substrate 1 of the present embodiment. The substrate 1 has a substantially rectangular substantially plate shape having a main surface 2 and a back surface (not shown), and has a central portion formed of a composite material obtained by impregnating glass fiber cloth with an epoxy resin and having a thickness of about 600 μm. A plate-shaped core substrate (resin insulating layer) 3 is provided. A resin insulation layer 5 of about 30 μm in thickness made of epoxy resin or the like is laminated on both surfaces. On the resin insulating layer 5, a solder resist layer (resin insulating layer) 7 made of epoxy resin or the like and having a thickness of about 25 μm is laminated.

Of these, a plurality of through-hole conductor through holes 10 having a diameter of about 250 μm are formed at predetermined positions in the core substrate 3, and a substantially cylindrical through-hole conductor 11 is formed on the inner peripheral surface thereof. Each is formed. Each through-hole conductor 11 is filled with a substantially cylindrical resin filling material 12 made of epoxy resin or the like. A plurality of via through holes 13 penetrating the resin insulating layer 5 are formed at predetermined positions, and a substantially cylindrical via conductor 15 is formed in each of the via through holes 13. The solder resist layer 7 has a plurality of pad openings 17 having a diameter of about 120 μm penetrating the solder resist layer 7 at predetermined positions.

Further, a first conductor layer 18 including a solid layer 21 extending between the core substrate 3 and the resin insulation layer 5 with a certain area is formed between the core substrate 3 and the resin insulation layer 5. It is connected to the via conductor 15 of the insulating layer 5. A second conductor layer 19 having a predetermined pattern such as a wiring or a pad is formed between the resin insulating layer 5 and the solder resist layer 7, and is connected to the via conductor 15 of the resin insulating layer 5. As shown in FIG. 1, the thickness of the resin insulating layer 5 formed on the solid layer 21 is substantially the same as that of the resin insulating layer 5 directly in contact with the core substrate 3. The height up to the upper surface is higher in a region where the solid layer 21 is projected on the main surface side than in other regions.

Some pads 22 formed between the resin insulating layer 5 and the solder resist layer 7 are exposed in the pad openings 17 of the solder resist layer 7 in order to mount electronic components such as IC chips on the substrate 1. are doing. A Ni plating layer is formed on the surface of the pad 22 to prevent oxidation, and an Au plating layer is formed on the surface (not shown). Here, since the upper surface of the resin insulating layer 5 is higher in a region where the solid layer 21 is projected on the main surface side, the first pads 22B formed in that region are formed in other regions. It is located higher than the core substrate 3 as compared with the second pad 22C.

{Circle around (2)} The plurality of pads 22 are formed with first planarized solder bumps 25B on the first pads 22B and second planarized solder bumps 25C on the second pads 22C, respectively, protruding from the main surface 2 of the substrate 1. Each of the flattening solder bumps 25B and 25C is made of 40Pb-60Sn solder, and the bottom surface covers each of the pads 22B and 22C. The first flattened solder bump 25B is smaller in height and volume than the second flattened solder bump 25C, and the height of the first flattened solder bump 25B from the main surface 2 is smaller than that of the second flattened solder bump 25B. It is lower than the solder bump 25C. However, since the first pad 22B and the second pad 22C have different heights from the core substrate 3, the top surface 26B of the first flattening solder bump 25B and the top surface 26C of the second flattening solder bump 25C are almost the same. Included in the plane. Further, the top surfaces 26B and 26C are formed into a flat surface, and the diameter thereof is about 105 μm.

This substrate 1 is manufactured as follows.
First, a description will be given with reference to FIG. The through-hole conductor 11 is formed on the core substrate 3 by a known method, and the first conductor layer 18 having a predetermined pattern including the solid layer 21 is formed on the core substrate 3. The filling material 12 is filled. Next, the resin insulating layer 5 and a Cu foil having a thickness of about 5 μm are laminated on the core substrate 3 and the first conductor layer 18 and pressed while being heated. The layer 5 is formed. Further, a predetermined position is pierced with a laser or the like, and a plurality of via through holes 13 penetrating the Cu foil and the resin insulating layer 5 are formed.

(4) Next, a substantially cylindrical via conductor 15 is formed in the via hole 13 and a second conductor layer 19 having a predetermined pattern is formed on the resin insulating layer 5 by a known method. Next, a solder resist layer 7 having a pad opening 17 is formed on the resin insulating layer 5 and the second conductor layer 19. Thereafter, a Ni plating layer is formed on the pad 22 exposed from the solder resist layer 7 to prevent oxidation, and an Au plating layer is further formed thereon (not shown).

Next, in a solder paste printing step, a solder paste 31 made of 40Pb-60Sn solder is applied to each pad 22 (see FIG. 2). Specifically, a print mask 32 is arranged on the substrate 1 and the solder paste 31 is applied from above the print mask 32 with a squeegee (not shown). As a result, the solder paste 31 that has passed through the through holes 33 provided in the print mask 32 adheres to the pads 22. The print mask 32 is formed in a substantially rectangular shape similar to the substrate 1 using a stainless steel plate, and through holes 33 are formed at positions corresponding to the respective pads 22.

Here, the diameter D1 of the first through hole 33B corresponding to the first pad 22B formed in the area where the solid layer 21 is projected on the main surface side corresponds to the second pad 22C formed in the other area. The diameter is smaller than the diameter D2 of the second through hole 33C. Here, the diameter D1 of the first through-hole 33B was about 130 μm, and the diameter D2 of the second through-hole 33C was about 150 μm. Therefore, the amount of the solder paste 31 applied to the first pad 22B is smaller than the amount of the solder paste 31 applied to the second pad 22C.

Next, in a reflow process, the solder paste 31 is dissolved to form a substantially hemispherical solder bump 35 (see FIG. 3). When the solder paste 31 is dissolved, the solder paste 31 becomes a substantially hemispherical solder bump 35 due to its surface tension. Here, since the amount of the solder paste 31 applied to the first pad 22B is smaller than that of the second pad 22C, as shown in FIG. 3, the volume of the first solder bump 35B formed on the first pad 22B and the amount of the first solder bump 35B are reduced. The height from the pad 22B is smaller than the volume of the second solder bump 35C formed on the second pad 22C and the height from the second pad 22C.

Next, in the flattening step, the top of the solder bump 35 is pressed by a pressing tool 39 having a flat pressing surface 37 to form the flattened solder bump 25 (see FIG. 4). For example, the solder bump 35 is crushed by a flattening device (not shown) that presses the flat pressing surface 37 against the substrate 1 using an air press with a pressing pressure of about 75 to 100 kg. At this time, the solder bump 35 may be heated by using the heated pressing surface 37 simultaneously with the pressing to make the solder bump 35 easily deformable.

As shown in FIG. 4, since the solid layer 21 is formed below, the distance T1 between the pressing surface 37 and the first pad 22B in the pressed state is the distance between the pressing surface 37 and the second pad 22C. It is smaller than T2. However, the first solder bump 35B formed on the first pad 22B has a smaller volume than the second solder bump 35C formed on the second pad 22C, and the height of the first solder bump 35B from the first pad 22B is equal to the second solder bump 35B. The height is lower than the height of the solder bump 35C from the second pad 22C. Therefore, the difference in the amount of solder crushed by the pressing surface 37 between the first solder bump 35B and the second solder bump 35C becomes smaller. Therefore, the difference between the diameter L1 of the top surface 26B of the first flattening solder bump 25B formed from the first solder bump 35B and the diameter L2 of the top surface 26C of the second flattening solder bump 25C formed from the second solder bump 35C is , Become smaller.

By appropriately adjusting the diameter of the first through hole 33B and the second through hole 33C formed in the print mask 32, the diameter L1 of the top surface 26B of the first flattening solder bump 25B and the second flattening solder bump 25B can be adjusted. The diameter L2 of the top surface 26C of the solder bump 25C may be substantially the same.
Thus, the substrate 1 is completed.

径 The diameter of the top surface 26 of the flattened solder bump 25 formed on the substrate 1 was 105.4 μm on average, 133.9 μm at maximum, 74.4 μm at minimum, 59.5 μm in range, and standard deviation 8.1. In the conventional substrate 101, the average was 118.9 μm, the maximum was 182.9 μm, the minimum was 62.9 μm, the range was 120.0 μm, and the standard deviation was 10.4. Therefore, it can be seen that both the range and the standard deviation were greatly improved.

In the above, the present invention has been described in accordance with the embodiments. However, it is needless to say that the present invention is not limited to the above embodiments, and can be appropriately modified and applied without departing from the gist thereof.
For example, in the above-described embodiment, the via conductor 15 in the form of a filled via is formed in the via-hole 13 for via, but a via conductor in a substantially bowl shape (unfilled via form) having a dent at the center may be formed. However, in this case, the comparison between the first pad 22B and the second pad 22C can be applied to pads having the same condition (difference in pad-on via or pad-off via) other than the solid layer.

In addition, in the above embodiment, when the first pad 22B and the second pad 22C are divided, attention is paid only to whether or not the solid layer 21 is provided in a region where the pad 22 is projected on the back surface side. However, besides this, for example, a pad 22 or the like in which an end of the solid layer 21 or a wiring other than the solid layer 21 is formed in a region where the pad 22 is projected on the back surface side can be considered. In this case, the diameter of the through hole 33 of the print mask 32 may be changed depending on the condition of each pad 22. By doing so, the diameter of the top surface 26 of each flattened solder bump 25 can be made more uniform.

In the above embodiment, one layer of the resin insulating layer 5 is formed on the substrate 1. However, a plurality of resin insulating layers 5 are stacked between the core substrate 3 and the solder resist layer 7. You may. In this case, the present invention can be applied to a case where the solid layer 21 is formed not between the core substrate 3 and the resin insulating layer 5 but between a plurality of resin insulating layers 5.

FIG. 3 is a partial enlarged cross-sectional view of the substrate according to the embodiment. FIG. 4 is an explanatory view showing a state where a solder paste is applied to a pad. FIG. 3 is an explanatory view showing a state in which solder bumps are formed on pads. It is explanatory drawing which shows a mode that the solder bump was pressed and the flattened solder bump was formed. It is a partial expanded sectional view of the conventional substrate. It is a partial expanded sectional view of the conventional substrate.

Explanation of reference numerals

1 substrate 2 main surface 3 core substrate (resin insulation layer)
5 Resin insulation layer 7 Solder resist layer (resin insulation layer)
21 solid layer 22 pad 22B first pad 22C second pad 25 flattened solder bump 25B first flattened solder bump 25C second flattened solder bump 26 top surface 31 solder paste 32 print mask 33B first through hole 33C second through hole 35 solder bump 37 pressing surface

Claims (4)

A method of manufacturing a wiring board comprising a plurality of flattened solder bumps having a main surface and a back surface, protruding toward the main surface, and having a top surface each flattened,
A solder paste printing step of applying a solder paste to each of the plurality of pads opened on the main surface side,
The plurality of pads include a first pad in which a solid layer is formed via one or more resin insulating layers in a region where the self is projected on the back surface side, and a solid layer in a region where the self is projected on the back surface side. Has no second pad, and
A solder paste printing step of applying a smaller amount of the solder paste than the second pad to the first pad;
A reflow step of dissolving the applied solder paste to form a substantially hemispherical solder bump,
A flattening step of pressing the top of the substantially hemispherical solder bump with a flat pressing surface to form the flattened solder bump;
The manufacturing method of the wiring board provided with. It is a manufacturing method of the wiring board of Claim 1, Comprising:
In the flattening step, the diameter of the top surface of the first flattened solder bump formed on the first pad is substantially equal to the diameter of the top surface of the second flattened solder bump formed on the second pad. A method of manufacturing a wiring board, comprising: a flattening step of forming solder bumps. A method of manufacturing a wiring board according to claim 1 or 2,
The print mask used in the solder paste printing step,
A method of manufacturing a wiring board, wherein a diameter of a first through hole corresponding to the first pad is smaller than a diameter of a second through hole corresponding to the second pad. A wiring substrate having a main surface and a back surface, protruding toward the main surface, and including a plurality of flattened solder bumps each having a flattened top surface,
A first pad having a plurality of pads opened on the main surface side, wherein a first pad having a solid layer formed thereon via one or a plurality of resin insulating layers in a region where the self is projected on the back surface side; A second pad having no solid layer in the area projected to the side,
A wiring board wherein the diameter of the top surface of the first flattening solder bump formed on the first pad is substantially equal to the diameter of the top surface of the second flattening solder bump formed on the second pad.

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