JP3966786B2 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

Info

Publication number
JP3966786B2
JP3966786B2 JP2002237127A JP2002237127A JP3966786B2 JP 3966786 B2 JP3966786 B2 JP 3966786B2 JP 2002237127 A JP2002237127 A JP 2002237127A JP 2002237127 A JP2002237127 A JP 2002237127A JP 3966786 B2 JP3966786 B2 JP 3966786B2
Authority
JP
Japan
Prior art keywords
semiconductor device
manufacturing
forming
bump
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2002237127A
Other languages
Japanese (ja)
Other versions
JP2003174060A (en
Inventor
浩之 平井
義孝 福岡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Dai Nippon Printing Co Ltd
Original Assignee
Dai Nippon Printing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Dai Nippon Printing Co Ltd filed Critical Dai Nippon Printing Co Ltd
Priority to JP2002237127A priority Critical patent/JP3966786B2/en
Publication of JP2003174060A publication Critical patent/JP2003174060A/en
Application granted granted Critical
Publication of JP3966786B2 publication Critical patent/JP3966786B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body

Description

【０００１】
【発明の属する技術分野】
本発明は半導体装置とその製造方法に係り、更に詳細には、半導体素子内蔵型の半導体装置とその製造方法に関する。
【０００２】
【従来の技術】
従来より、絶縁性基板上に配線パターンを形成し、この配線パターン上に半導体素子を実装する方式の半導体装置２００が知られている。図１３は、代表的な半導体装置の製造工程を示した図である。図１３（ａ）に示したように、この半導体装置２００では、絶縁性基板１０１のアルミ電極パッド１０２，１０２，…の上に金ワイヤをキャピラリ１０４用いて金ボールバンプ１０３，１０３，…を一つずつ形成する。次にプリント配線基板１１０の所定位置に異方性導電フィルム１０５を貼り付け、プリント配線基板１１０上面に形成した導体パッド１１１，１１１，…と金ボールバンプ１０３，１０３，…とを位置合わせし、半導体素子１００を加圧、加熱する。ことにより金ボールバンプ１０３，１０３，…と導体パッド１１１，１１１，…とを異方性導電フィルム１０５中に含まれる導電性粒子１０６を介して電気的接続を形成する。半導体素子１００とプリント配線基板１１０とを機械的に接続し、半導体装置２００を製造している。
【０００３】
しかし上記のような金ボールボンディング法による製造方法では、半導体素子１００の複数個のアルミ電極パッド１０２，１０２，…に対して一つずつ金ボールバンプ１０３，１０３，…を形成するため、手間がかかり過ぎて生産性が悪いという問題がある。この電極パッド１０２，１０２，…の個数は増加傾向にあり、半導体素子１００が大型化し、電極パッド１０２の個数が増えれば増えるほどバンプ形成の所要時間が必然的に長くなり、工数の増大と生産速度が低下するという問題を含んでいる。
【０００４】
また、上記のような金ボールバンプ法では、半導体素子１００の実装時に金ボールバンプ１０３と半導体素子１００のアルミ電極パッド間で金属拡散する温度まで圧力を加えて加熱（約３００℃以上）しなければならず、この加熱により半導体素子１００が劣化する可能性が増大するという半導体装置の信頼性の問題がある。
【０００５】
更に金ボールバンプ法では高価な金ワイヤを必須とするため、半導体装置の材料コストが上昇し、ひいては半導体装置の製造コストが増大するという問題がある。
【０００６】
【発明が解決しようとする課題】
上記したように、従来の方法では、製造時の工数が増大したり、半導体装置の品質や信頼性が低下したり、製造コストが増大するという問題があった。
【０００７】
本発明は、上記従来の問題を解消するためになされた発明である。すなわち、本発明は、製造時の工数が少なくて済み、半導体装置の品質や信頼性を高い水準に維持することができ、製造コストを安価に抑えることができる半導体装置及びその製造方法を提供することを目的とする。
【０００８】
【課題を解決するための手段】
上記目的を達成するために、本発明の半導体装置の製造方法で製造される半導体装置は、絶縁性基板と、前記絶縁性基板上に配設された配線パターンと、前記配線パターン上の所定位置に配設された半導体素子と、前記半導体素子の電極板と前記配線パターンとの間に介挿され、前記電極板と前記配線パターンとを電気的に接続する略円錐形の導体バンプと、前記半導体素子と前記絶縁性基板との間を封止する封止材料層と、を具備することを特徴とする。
【０００９】
上記半導体装置において、前記導体バンプの例として、底面半径２５〜４０μｍ、高さ１０〜４０μｍ、及び、アスペクト比１：５〜１：２を有するものを挙げることができる。
【００１０】
上記半導体装置において、前記導体バンプの例として、バンプ表面を被覆するバリアメタル層と、前記バリアメタル層表面を被覆する溶接性金属層とを有するものを挙げることができる。
【００１１】
上記半導体装置において、前記封止材料層の例として、異方導電性組成物からなるものを挙げることができる。
【００１２】
また、本発明の半導体装置の製造方法は、複数の半導体素子の実装された半導体装置の製造方法であって、第１の面と第２の面を有する絶縁性基板の第１の面に、実装される複数の半導体素子の各電極と対応する位置に電極パッドを有する配線パターンが形成され、第２の面には複数の電極板が形成され、前記配線パターンと前記各電極板が前記絶縁性基板を貫通する層間接続導体により接続された配線基板を形成する工程と、前記配線基板の第１の面の前記配線パターンの電極パッド上に一括して導体バンプを形成する工程と、前記配線基板の第１の面の前記導体バンプの形成された電極パッド上に異方導電性組成物を塗布する工程と、前記配線基板の第１の面の電極パッドと実装すべき半導体素子の電極とを位置合わせする工程と、位置合わせの行われた前記半導体素子と前記配線基板とを加熱下に加圧して前記導体バンプと前記電極とを接合する工程と、前記配線基板の第２の面に形成した複数の電極板上に他の配線基板に接続するための外部接続端子を設ける工程とを具備することを特徴とする。
【００１３】
上記半導体装置の製造方法において、前記導体バンプを形成する工程の例として、孔を備えた型板の上から導電ペーストをすりこみ、しかる後に前記型板を剥がすことにより導電ペーストバンプを形成する方法を挙げることができる。
【００１４】
上記半導体装置の製造方法において、前記導体バンプを形成する工程の例として、前記配線パターン形成面上にバンプ形成用の孔を備えたマスキングを形成し、前記マスキングの孔内に金属を析出することによりメッキバンプを形成する方法を挙げることができる。
【００１５】
上記半導体装置の製造方法において、前記導体バンプを形成する工程の例として、金属板上のバンプ頭部相当位置にマスキングを形成し、前記マスキングの上からエッチング液を供給することによりエッチングバンプを形成する方法を挙げることができる。
【００１６】
上記半導体装置の製造方法において、前記バンプ形成後、前記バンプ表面にバリアメタル層を形成する工程と、前記バリアメタル層表面に溶接金属層を形成する工程を更に具備していても良い。
【００１７】
本発明では、半導体素子をプリント配線基板上に実装するのに、上記のような導体バンプを用いているので、製造工数を減少させ、半導体装置の品質や信頼性を高水準に維持でき、しかも製造コストを安価に抑えることのできる半導体装置及びその製造方法を提供することができる。
【００１８】
【発明の実施の形態】
（第１の実施の形態）
以下、本発明の第１の実施の形態に係る半導体装置の製造について説明する。図１及び図２は、本実施形態に係る半導体装置の製造方法のフローチャートであり、図３、図４及び図５は、製造途中の本実施形態に係る半導体装置の断面図である。
【００１９】
本実施形態に係る半導体装置を製造するには、まず絶縁基板の両面に配線パターンを形成した、いわゆる２層板を用意する。この２層板の製造方法のフローチャートを示したのが図１であり、製造途中の２層板の断面図を示したのが図３である。この２層板を製造するには、最初に図３（ａ）に示したように銅箔などの導体板１０を用意する。この導体板１０の上に印刷技法を用いて導体バンプ２０，２０…を形成する。
【００２０】
この導体バンプ２０，２０，…の形成方法としては、例えば、バンプ形成部分に孔を設けたマスキングを施す。（ステップ１）次いでこの孔内に導電性ペースト、例えば銀粉や銅粉などの金属微粒子をエポキシ樹脂のような液状樹脂中に分散させたペースト状組成物を充填する。（ステップ２）しかる後、マスキング上面からスキージ（ステップ３）し、前記マスキングを剥離する（ステップ４）。このようにして、図３（ｂ）に示したような、略円錐形の導体バンプ２０，２０，…を形成した後、この導体バンプ２０，２０，…を乾燥させ、硬化する（ステップ５）。
【００２１】
次に、図３（ｃ）に示したように、導体バンプ２０，２０，…の上にプリプレグ（絶縁基板前駆体）３０、すなわちガラス繊維マットのような補強材料中にエポキシ樹脂などの絶縁性樹脂を含浸させたものを重ねる。更にこのプリプレグ３０の上にもう１枚の銅箔などの導体板４０を重ね合わせ（ステップ６）、この状態でヒートプレス、すなわち加熱下で加圧する（ステップ７）。
【００２２】
このヒートプレスすることにより導体バンプ２０，２０，…は、プリプレグ３０を貫通して導体板１０と導体板４０との間が電気的に接続される。それと同時にプリプレグ３０が硬化して、図３（ｄ）に示したような、２層型プリント配線基板５０が得られる。この２層型配線基板５０表面の導体板１０，４０に例えばエッチング処理等によるパターニング（ステップ８）を施すことにより配線パターン１１，４１が形成された２層板５１が形成される。
【００２３】
次いで、２層板５１上の配線パターン４１のうち、図３（ｆ）に示すように、半導体素子の電極に対応する位置に形成した電極パッド４１ｂ，４１ｂ，…上に実装バンプとして、銀ペーストバンプのような実装バンプ６０，６０，…を形成する。この実装バンプ６０，６０，…の形成方法は上記導体バンプ２０，２０，…の形成方法と実質的に同じである。
【００２４】
すなわち、バンプ形成部分に孔を設けたマスキングを施し（ステップ１ａ）、この孔内に導電性ペースト、例えば銀粉や銅粉などの金属微粒子をエポキシ樹脂のような液状樹脂中に分散させたペースト状組成物を充填し（ステップ２ａ）、マスキング上面からスキージ（ステップ３ａ）し、前記マスキングを剥離する（ステップ４ａ）ことからなる方法である。
【００２５】
但し、ここで形成する銀ペーストバンプ６０，６０，…の大きさは、高さが１０〜４０μｍ、底面半径が２５〜４０μｍである。これは半導体素子７０ａ〜７０ｃの大きさに対応させるためである。実装バンプ６０，６０，…の大きさの更に好ましい範囲は、高さが１５〜２５μｍ、底面半径が３０〜３５μｍである。
【００２６】
次にマスキング剥離後、実装バンプ６０，６０，…を硬化させ（ステップ５ａ）、然る後に、例えば電解メッキや無電解メッキなどのＮｉメッキ処理を施すことにより、実装バンプ６０，６０，…、その底部の電極パッド４１ｂ表面に、図４（ｈ）に示したような、バリアメタル層としてのＮｉ層６１を形成する（ステップ６ａ）。次いでＮｉ層６１の上からＡｕメッキ処理（ステップ７ａ）を施すことによりＡｕ層６２を形成する。こうして図４（ｈ）に示したようなバンプ付基板５２が得られる。
【００２７】
次に、こうして得られたバンプ付基板５２の実装バンプ６０，６０，…形成面上に、図４（ｉ）に示したように、ＡＣＦ（異方性導電接着剤層）６３ａ〜６３ｃを形成し、電極パッド４１ｂ，４１ｂ，…に対して電極板７１ａ，７１ａ，…、７１ｂ，７１ｂ，…、７１ｃ，７１ｃ，…がそれぞれ対向するように半導体素子７０ａ〜７０ｃを位置合わせする（ステップ８ａ）。
【００２８】
次いで、この状態で半導体素子７０ａ〜７０ｃとバンプ付基板５２とを押圧すると、図５（ｊ）に示したように、実装バンプ６０，６０，…がＡＣＦ（異方性導電接着剤層）６３ａ〜６３ｃをそれぞれ貫通し、電極板７１ａ，７１ａ，…、７１ｂ，７１ｂ，…、７１ｃ，７１ｃ，…に加圧される（ステップ９ａ）。このとき実装バンプ６０，６０，…の表面にはＡｕ層６２，６２，…が形成されており、電極板７１ａ，７１ａ，…、７１ｂ，７１ｂ，…、７１ｃ，７１ｃ，…はＡｌで出来ているので、実装バンプ６０，６０，…と電極板７１ａ，７１ａ，…、７１ｂ，７１ｂ，…、７１ｃ，７１ｃ，…との間にはＡｌ−Ａｕ接合が形成され、電極パッド４１ｂ，４１ｂ，…と電極板７１ａ，７１ａ，…、７１ｂ，７１ｂ，…、７１ｃ，７１ｃ，…との間がＡｕ層６２，Ｎｉ層６１，実装バンプ６０，ＡＣＦ（異方性導電接着剤層）６３ａ〜６３ｃを介してそれぞれ電気的に接合される。こうして、図５（ｊ）に示したような半導体素子７０ａ〜７０ｃが実装された半導体装置５３が得られる。次いで、ＡＣＦ６３ａ〜６３ｃの樹脂を硬化させることにより、図５（ｊ）に示したような半導体装置５３が得られる。
【００２９】
次いで、こうして得られた半導体装置５３下面側の電極板１１，１１，…上にハンダペーストボール１２，１２，…を付着させ、この状態でマザーボード１３上の電極板１４，１４，…に対して位置合わせし（ステップ１０ａ）、加熱下に加圧することにより、図５（ｌ）に示したように、半導体装置５３がマザーボード１３上にマウントされる（ステップ１１ａ）。
【００３０】
なお、このマザーボード１３上にマウントする際に、上記ハンダペーストボール１２，１２，…の代わりに電極板１１，１１，…或いは電極板１４，１４，…上に導電性ペーストを印刷して導電ペーストバンプを形成しておき、この導電ペーストバンプを介して電極板１１，１１，…と電極板１４，１４，…との間を電気的に接合してもよい。
【００３１】
以上説明したように、本実施形態に係る半導体装置５３では、半導体素子７０ａ〜７０ｃを２層板５１上に実装する際に電極パッド４１ｂ，４１ｂ，…上に導電性ペーストを印刷して形成した実装バンプ６０，６０，…を介して接合している。よって、多数個の実装バンプ６０，６０，…を同時に形成できるので、工数を減らし、生産速度を向上させることができる。
【００３２】
また、実装バンプ６０，６０，…を介して実装する場合には金ボールバンプを介して実装する場合のような高温に加熱する必要がないので、実装時の加熱による半導体素子７０の劣化や２層板５１のヒートショックを可及的に低く抑えることができ、高品質で信頼性の高い半導体装置を得ることができる。
【００３３】
更に、本実施形態では金ワイヤに比較して安価な導電性ペーストを用いて実装バンプ６０，６０，…を形成するので、材料コスト、ひいては製造コストを安価に抑えることができる。
【００３４】
（第２の実施の形態）
以下、本発明の第２の実施の形態に係る半導体装置の製造方法について説明する。図６は本実施形態に係る半導体装置の断面図である。
【００３５】
本実施形態に係る半導体装置では、絶縁性基板の両面に半導体素子を実装する構造とした。すなわち図６に示したように、本実施形態に係る半導体装置１Ａでは、絶縁性基板３０の表裏両面に配線パターン４２，４３が形成されており、これら配線パターン４２，４３の上に形成された実装バンプ６０ａ，６０ａ，…及び６０ｂ，６０ｂ，…を介して半導体素子７０ａ〜７０ｄがそれぞれ実装されている。
【００３６】
このように、絶縁性基板３０の両面に半導体素子７０ａ〜７０ｅを実装することにより、より集積度の高いマルチチップモジュールを作成することができる。
【００３７】
（第３の実施の形態）
以下、本発明の第３の実施の形態に係る半導体装置の製造方法について説明する。図７は本実施形態に係る半導体装置の製造方法のフローチャートであり、図８及び図９は製造途中の本実施形態に係る半導体装置の断面図である。
【００３８】
本実施形態に係る半導体装置を製造するには、上記第１の実施形態の図３（ａ）〜（ｅ）に示したステップ１〜８の工程に従って２層板５１を形成する。
【００３９】
次いで、２層板５１の表面に感光性樹脂を塗布などの方法により適用して、図８（ｆ）に示したような、感光性樹脂層８０を形成する（ステップ１ｂ）。次いで２層板５１上の配線パターン４１ａのうち、図８（ｇ）に示すように、半導体素子の電極に対応する位置に形成した電極パッド４１ｂ，４１ｂ，…上に対応する位置の感光性樹脂層８０上面上にメッキホール８１，８１，…を形成する。このメッキホールの形成方法としては、例えば、電極パッド４１ｂ，４１ｂ，…の真上の位置にマスキング（図示省略）を形成し（ステップ２ｂ）、このマスキングの上から露光し（ステップ３ｂ）、溶剤中に浸漬して現像（ステップ４ｂ）する方法などが挙げられる。
【００４０】
メッキホールを形成した感光性樹脂層８０の上から、電解メッキや無電解メッキなどのメッキ処理を施すことにより、図８（ｈ）に示したような、メッキバンプ６４，６４，…を形成する（ステップ５ｂ）。次いで、図８（ｉ）に示したように感光性樹脂層８０を除去し（ステップ６ｂ）、メッキバンプ６４，６４，…を露出させ、このメッキバンプ６４，６４，…の上にＮｉメッキ（ステップ７ｂ）を施して、図８（ｊ）に示したような、バリアメタル層としてのＮｉ層６１を形成し、更に、その上からＡｕメッキ（ステップ８ｂ）を施して、図８（ｋ）に示したような、Ａｕ層６２を形成する。
【００４１】
以下、上記第１の実施形態と同様にして、図９（ｌ）に示したように、ＡＣＦ６３を形成し、半導体素子７０ａ及び７０ｂを位置合わせし（ステップ９ｂ）、次いで図９（ｍ）に示したように押圧して実装する（ステップ１０ｂ）ことにより、図９（ｍ）に示したような半導体装置（マルチチップモジュール）１Ｂが得られる。
【００４２】
本実施形態によれば、金属製のメッキバンプ６４を用いて半導体素子７０ａ，７０ｂを実装するので、より確実に実装することができる。
【００４３】
（第４の実施の形態）
以下、本発明の第３の実施の形態に係る半導体装置の製造について説明する。図１０は本実施形態に係る半導体装置の製造方法のフローチャートであり、図１１及び図１２は製造途中の本実施形態に係る半導体装置の断面図である。
【００４４】
本実施形態に係る半導体装置を製造するには、上記第１の実施形態の図１（ａ）〜（ｅ）に示したステップ１〜８の工程に従って２層板５１を形成する。
【００４５】
次いで図１１（ｆ）に示したように、２層板５１の表面に銅箔などの金属板又は金属層を貼り付けやメッキなどの方法によりＣｕ層６５を形成する（ステップ１ｃ）。次いで、配線パターン４１ａのうち、図１１（ｇ）に示すように、半導体素子の電極に対応する位置に形成した電極パッド４１ｂ，４１ｂ，…上に対応する位置のＣｕ層６５上面上にマスキング８２，８２，…を形成する（ステップ２ｃ）。
【００４６】
マスキング８２，８２，…を形成したＣｕ層６５の上からエッチング処理を施すことにより、図１１（ｈ）に示したような、エッチングバンプ６６，６６，…を形成する（ステップ３ｃ）。次いで図１１（ｉ）に示したように、マスキング８２，８２，…を除去し（ステップ４ｃ）、エッチングバンプ６６，６６，…を露出させ、このエッチングバンプ６６，６６，…の上にＮｉメッキ（ステップ５ｃ）を施す。次に、図１１（ｊ）に示したような、バリアメタル層としてのＮｉ層６１を形成し、更に、その上からＡｕメッキ（ステップ６ｃ）を施して図１１（ｋ）に示したようなＡｕ層６２を形成する。
【００４７】
以下、上記第１の実施形態と同様にして、図１２（ｌ）に示したように、ＡＣＦ６３を形成し、半導体素子７０ａ及び７０ｂを位置合わせをする（ステップ７ｃ）。次いで、図１２（ｍ）に示したように、押圧して実装する（ステップ８ｃ）ことにより、図１２（ｍ）に示したような半導体装置（マルチチップモジュール）１Ｃが得られる。
【００４８】
本実施形態によれば、金属製のエッチングバンプ６６を用いて半導体素子７０を実装するので、より確実に実装することができる。
【００４９】
【発明の効果】
本発明によれば、導電性ペーストを印刷して形成した実装バンプを介して半導体素子を２層板上に実装しているので、高い生産速度、高い品質、及び、安価な製造コストで半導体装置を得ることができる。
【図面の簡単な説明】
【図１】第１の実施形態に係る半導体装置の製造方法のフローチャートである。
【図２】第１の実施形態に係る半導体装置の製造方法のフローチャートである。
【図３】第１の実施形態に係る半導体装置の製造途中のもの断面図である。
【図４】第１の実施形態に係る半導体装置の製造途中のもの断面図である。
【図５】第１の実施形態に係る半導体装置の製造途中のもの断面図である。
【図６】第２の実施形態に係る半導体装置の断面図である。
【図７】第３の実施形態に係る半導体装置の製造方法のフローチャートである。
【図８】第３の実施形態に係る半導体装置の製造途中のものの断面図である。
【図９】第３の実施形態に係る半導体装置の製造途中のものの断面図である。
【図１０】第４の実施形態に係る半導体装置の製造方法のフローチャートである。
【図１１】第４の実施形態に係る半導体装置の製造途中のものの断面図である。
【図１２】第４の実施形態に係る半導体装置の製造途中のものの断面図である。
【図１３】従来の半導体装置の断面図である。
【符号の説明】
１…半導体装置、５１…２層板、４１ａ…配線パターン、４１ｂ…電極パッド、６０…実装バンプ、６１…Ｎｉ層（バリアメタル層）、６２…Ａｕ層、６３…ＡＣＦ、６４…ＡＣＦ、７０…半導体素子、７１…電極板。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device incorporating a semiconductor element and a manufacturing method thereof.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, there has been known a semiconductor device 200 in which a wiring pattern is formed on an insulating substrate and a semiconductor element is mounted on the wiring pattern. FIG. 13 is a diagram showing a manufacturing process of a typical semiconductor device. As shown in FIG. 13A, in this semiconductor device 200, gold ball bumps 103, 103,... Are placed on the aluminum electrode pads 102, 102,. Form one by one. Next, the anisotropic conductive film 105 is attached to a predetermined position of the printed wiring board 110, and the conductor pads 111, 111,... Formed on the upper surface of the printed wiring board 110 and the gold ball bumps 103, 103,. The semiconductor element 100 is pressurized and heated. As a result, the gold ball bumps 103, 103,... And the conductor pads 111, 111,... Are electrically connected through the conductive particles 106 contained in the anisotropic conductive film 105. The semiconductor device 200 is manufactured by mechanically connecting the semiconductor element 100 and the printed wiring board 110.
[0003]
However, in the manufacturing method using the gold ball bonding method as described above, the gold ball bumps 103, 103,... Are formed one by one on the plurality of aluminum electrode pads 102, 102,. There is a problem that productivity is poor because it takes too much. The number of the electrode pads 102, 102,... Tends to increase. As the semiconductor element 100 becomes larger and the number of the electrode pads 102 increases, the time required for bump formation becomes inevitably longer. It includes the problem of slowing down.
[0004]
Further, in the gold ball bump method as described above, when the semiconductor element 100 is mounted, it is necessary to apply pressure to a temperature at which metal diffusion is performed between the gold ball bump 103 and the aluminum electrode pad of the semiconductor element 100 (about 300 ° C. or higher). In addition, there is a problem of reliability of the semiconductor device in which the possibility that the semiconductor element 100 is deteriorated by this heating increases.
[0005]
Furthermore, since the gold ball bump method requires an expensive gold wire, there is a problem that the material cost of the semiconductor device increases, and the manufacturing cost of the semiconductor device increases.
[0006]
[Problems to be solved by the invention]
As described above, the conventional method has a problem that the number of man-hours during manufacturing increases, the quality and reliability of the semiconductor device decrease, and the manufacturing cost increases.
[0007]
The present invention has been made to solve the above-described conventional problems. That is, the present invention provides a semiconductor device and a method for manufacturing the semiconductor device that can reduce man-hours during manufacturing, maintain the quality and reliability of the semiconductor device at a high level, and can suppress the manufacturing cost at a low cost. For the purpose.
[0008]
[Means for Solving the Problems]
In order to achieve the above object, a semiconductor device manufactured by the method for manufacturing a semiconductor device according to the present invention includes an insulating substrate, a wiring pattern disposed on the insulating substrate, and a predetermined position on the wiring pattern. A substantially conical conductor bump that is interposed between the electrode plate of the semiconductor element and the wiring pattern, and electrically connects the electrode plate and the wiring pattern; And a sealing material layer for sealing between the semiconductor element and the insulating substrate.
[0009]
In the semiconductor device, examples of the conductor bump include those having a bottom radius of 25 to 40 μm, a height of 10 to 40 μm, and an aspect ratio of 1: 5 to 1: 2.
[0010]
In the above semiconductor device, examples of the conductor bump include a barrier metal layer covering the bump surface and a weldable metal layer covering the barrier metal layer surface.
[0011]
In the above semiconductor device, examples of the sealing material layer include those made of an anisotropic conductive composition.
[0012]
The semiconductor device manufacturing method of the present invention is a method for manufacturing a semiconductor device on which a plurality of semiconductor elements are mounted, and the first surface of the insulating substrate having the first surface and the second surface is formed on the first surface. A wiring pattern having an electrode pad is formed at a position corresponding to each electrode of a plurality of semiconductor elements to be mounted, a plurality of electrode plates are formed on the second surface, and the wiring pattern and each electrode plate are insulated from each other. forming a wiring board connected by an interlayer connection conductor passing through the gender substrate, forming a conductive bump collectively on the electrode pads of the wiring pattern of the first surface of the wiring substrate, the wiring A step of applying an anisotropic conductive composition on the electrode pads on which the conductive bumps are formed on the first surface of the substrate; an electrode pad on the first surface of the wiring substrate; and an electrode of a semiconductor element to be mounted ; a step of aligning the position A step of bonding the electrode and the conductor bump Align the performed said semiconductor element and said wiring substrate pressurizing under heating, on a plurality of electrode plates formed on the second surface of the wiring substrate And a step of providing an external connection terminal for connection to another wiring board.
[0013]
In the semiconductor device manufacturing method, as an example of the step of forming the conductive bump, a method of forming a conductive paste bump by rubbing a conductive paste from above a template having holes and peeling the template after that. Can be mentioned.
[0014]
In the semiconductor device manufacturing method, as an example of the step of forming the conductor bump, a mask having a hole for forming a bump is formed on the wiring pattern forming surface, and a metal is deposited in the masking hole. The method of forming a plating bump can be mentioned.
[0015]
In the semiconductor device manufacturing method, as an example of the step of forming the conductor bump, a mask is formed at a position corresponding to a bump head on a metal plate, and an etching bump is formed by supplying an etching solution from the mask. The method of doing can be mentioned.
[0016]
The method for manufacturing a semiconductor device may further include a step of forming a barrier metal layer on the surface of the bump and a step of forming a weld metal layer on the surface of the barrier metal layer after forming the bump.
[0017]
In the present invention, the above-described conductor bump is used to mount the semiconductor element on the printed wiring board, so that the number of manufacturing steps can be reduced, and the quality and reliability of the semiconductor device can be maintained at a high level. It is possible to provide a semiconductor device and a method for manufacturing the same that can reduce the manufacturing cost.
[0018]
DETAILED DESCRIPTION OF THE INVENTION
(First embodiment)
Hereinafter, the manufacture of the semiconductor device according to the first embodiment of the present invention will be described. 1 and 2 are flowcharts of a method for manufacturing a semiconductor device according to the present embodiment, and FIGS. 3, 4, and 5 are cross-sectional views of the semiconductor device according to the present embodiment during manufacturing.
[0019]
In order to manufacture the semiconductor device according to this embodiment, first, a so-called two-layer board in which wiring patterns are formed on both surfaces of an insulating substrate is prepared. FIG. 1 shows a flowchart of the manufacturing method of the two-layer board, and FIG. 3 shows a cross-sectional view of the two-layer board in the middle of manufacturing. In order to manufacture this two-layer plate, first, a conductor plate 10 such as a copper foil is prepared as shown in FIG. .. Are formed on the conductor plate 10 by using a printing technique.
[0020]
As a method for forming the conductor bumps 20, 20,..., For example, masking with holes provided in the bump forming portion is performed. (Step 1) Next, a conductive paste, for example, a paste-like composition in which fine metal particles such as silver powder and copper powder are dispersed in a liquid resin such as an epoxy resin is filled in the holes. After (Step 2) Ru only, and squeegee from masking the upper surface (Step 3), peeling the masking (step 4). In this way, after forming the substantially conical conductor bumps 20, 20,... As shown in FIG. 3B, the conductor bumps 20, 20,... Are dried and cured (step 5). .
[0021]
Next, as shown in FIG. 3C, an insulating property such as an epoxy resin in a prepreg (insulating substrate precursor) 30, that is, a reinforcing material such as a glass fiber mat, is formed on the conductor bumps 20, 20,. Stack the ones impregnated with resin. Further, another conductor plate 40 such as a copper foil is overlaid on the prepreg 30 (step 6), and in this state, heat press, that is, pressurizing under heating (step 7).
[0022]
By this heat pressing, the conductor bumps 20, 20,... Pass through the prepreg 30 and the conductor plate 10 and the conductor plate 40 are electrically connected. At the same time, the prepreg 30 is cured to obtain a two-layer printed wiring board 50 as shown in FIG. The conductor plates 10 and 40 on the surface of the two-layer wiring board 50 are subjected to patterning (step 8) by, for example, an etching process to form the two-layer plate 51 on which the wiring patterns 11 and 41 are formed.
[0023]
Next, as shown in FIG. 3 (f) in the wiring pattern 41 on the two-layer plate 51, silver paste is used as mounting bumps on electrode pads 41b, 41b,... Formed at positions corresponding to the electrodes of the semiconductor element. Mounting bumps 60, 60,... Like bumps are formed. The method for forming the mounting bumps 60, 60,... Is substantially the same as the method for forming the conductor bumps 20, 20,.
[0024]
In other words, the bump forming portion is masked with holes (step 1a), and a conductive paste, for example, metal particles such as silver powder and copper powder are dispersed in a liquid resin such as epoxy resin in the holes. It is a method comprising filling with the composition (step 2a), squeegeeing from the upper surface of the masking (step 3a), and peeling off the masking (step 4a).
[0025]
However, the silver paste bumps 60, 60,... Formed here have a height of 10 to 40 μm and a bottom surface radius of 25 to 40 μm. This is to correspond to the size of the semiconductor elements 70a to 70c. A more preferable range of the size of the mounting bumps 60, 60,... Is 15 to 25 μm in height and 30 to 35 μm in the bottom radius.
[0026]
Next, after removing the masking, the mounting bumps 60, 60,... Are cured (step 5a), and thereafter, by performing Ni plating treatment such as electrolytic plating or electroless plating, the mounting bumps 60, 60,. A Ni layer 61 as a barrier metal layer as shown in FIG. 4H is formed on the surface of the electrode pad 41b at the bottom (step 6a). Next, the Au layer 62 is formed by performing an Au plating process (step 7a) on the Ni layer 61. In this way, the bumped substrate 52 as shown in FIG.
[0027]
Next, as shown in FIG. 4 (i), ACFs (anisotropic conductive adhesive layers) 63a to 63c are formed on the formation surface of the mounting bumps 60, 60,. Then, the semiconductor elements 70a to 70c are aligned so that the electrode plates 71a, 71a, ..., 71b, 71b, ..., 71c, 71c, ... face the electrode pads 41b, 41b, ... (step 8a). .
[0028]
Next, when the semiconductor elements 70a to 70c and the bumped substrate 52 are pressed in this state, as shown in FIG. 5 (j), the mounting bumps 60, 60, ... are ACF (anisotropic conductive adhesive layer) 63a. ˜63c, respectively, and pressure is applied to the electrode plates 71a, 71a,..., 71b, 71b, ..., 71c, 71c,. At this time, Au layers 62, 62, ... are formed on the surfaces of the mounting bumps 60, 60, ..., and the electrode plates 71a, 71a, ..., 71b, 71b, ..., 71c, 71c, ... are made of Al. Therefore, an Al-Au bond is formed between the mounting bumps 60, 60, ... and the electrode plates 71a, 71a, ..., 71b, 71b, ..., 71c, 71c, ..., and electrode pads 41b, 41b, ... , 71b, 71b,..., 71c, 71c,... Are Au layer 62, Ni layer 61, mounting bump 60, ACF (anisotropic conductive adhesive layer) 63a-63c. Are electrically connected to each other. Thus, the semiconductor device 53 on which the semiconductor elements 70a to 70c as shown in FIG. Next, by curing the resins of ACFs 63a to 63c, a semiconductor device 53 as shown in FIG. 5 (j) is obtained.
[0029]
Next, solder paste balls 12, 12,... Are attached on the electrode plates 11, 11,... On the lower surface side of the semiconductor device 53 thus obtained, and in this state, the electrode plates 14, 14,. By aligning (step 10a) and pressurizing under heating, the semiconductor device 53 is mounted on the mother board 13 as shown in FIG. 5 (l) (step 11a).
[0030]
When mounting on this mother board 13, instead of the solder paste balls 12, 12,..., A conductive paste is printed on the electrode plates 11, 11,. A bump may be formed, and the electrode plates 11, 11,... And the electrode plates 14, 14,.
[0031]
As described above, in the semiconductor device 53 according to the present embodiment, when the semiconductor elements 70a to 70c are mounted on the two-layer plate 51, the conductive paste is printed on the electrode pads 41b, 41b,. It joins via mounting bump 60,60, .... Therefore, since a large number of mounting bumps 60, 60,... Can be formed simultaneously, the number of steps can be reduced and the production speed can be improved.
[0032]
Further, when mounting via the mounting bumps 60, 60,..., There is no need to heat to a high temperature as when mounting via the gold ball bumps. The heat shock of the layer plate 51 can be suppressed as low as possible, and a high-quality and highly reliable semiconductor device can be obtained.
[0033]
Furthermore, in the present embodiment, the mounting bumps 60, 60,... Are formed using a conductive paste that is less expensive than a gold wire, so that the material cost and thus the manufacturing cost can be kept low.
[0034]
(Second Embodiment)
A method for manufacturing a semiconductor device according to the second embodiment of the present invention will be described below. FIG. 6 is a cross-sectional view of the semiconductor device according to the present embodiment.
[0035]
The semiconductor device according to this embodiment has a structure in which semiconductor elements are mounted on both surfaces of an insulating substrate. That is, as shown in FIG. 6, in the semiconductor device 1 </ b> A according to the present embodiment, the wiring patterns 42 and 43 are formed on both the front and back surfaces of the insulating substrate 30, and are formed on the wiring patterns 42 and 43. Semiconductor elements 70a to 70d are mounted via mounting bumps 60a, 60a,... And 60b, 60b,.
[0036]
Thus, by mounting the semiconductor elements 70a to 70e on both surfaces of the insulating substrate 30, a multichip module with a higher degree of integration can be created.
[0037]
(Third embodiment)
A method for manufacturing a semiconductor device according to the third embodiment of the present invention will be described below. FIG. 7 is a flowchart of the manufacturing method of the semiconductor device according to the present embodiment, and FIGS. 8 and 9 are cross-sectional views of the semiconductor device according to the present embodiment during manufacturing.
[0038]
In order to manufacture the semiconductor device according to the present embodiment, the two-layer plate 51 is formed according to the steps 1 to 8 shown in FIGS. 3A to 3E of the first embodiment.
[0039]
Next, a photosensitive resin is applied to the surface of the two-layer plate 51 by a method such as coating to form a photosensitive resin layer 80 as shown in FIG. 8F (step 1b). Next, in the wiring pattern 41a on the two-layer plate 51, as shown in FIG. 8G, the photosensitive resin at positions corresponding to the electrode pads 41b, 41b,... Formed at positions corresponding to the electrodes of the semiconductor element. .. Are formed on the upper surface of the layer 80. As a method for forming this plated hole, for example, masking (not shown) is formed at a position directly above the electrode pads 41b, 41b,... (Step 2b), and exposure is performed from above the masking (Step 3b). For example, a method of immersing and developing (step 4b) may be used.
[0040]
Plating bumps 64, 64,... As shown in FIG. 8H are formed by performing a plating process such as electrolytic plating or electroless plating on the photosensitive resin layer 80 in which the plated holes are formed. (Step 5b). Next, as shown in FIG. 8 (i), the photosensitive resin layer 80 is removed (step 6b), the plating bumps 64, 64,... Are exposed, and Ni plating ( Step 7b) is performed to form a Ni layer 61 as a barrier metal layer as shown in FIG. 8 (j), and Au plating (step 8b) is further performed thereon to form FIG. 8 (k). An Au layer 62 as shown in FIG.
[0041]
Thereafter, in the same manner as in the first embodiment, as shown in FIG. 9L, the ACF 63 is formed, the semiconductor elements 70a and 70b are aligned (step 9b), and then in FIG. 9M. By pressing and mounting as shown (step 10b), a semiconductor device (multichip module) 1B as shown in FIG. 9 (m) is obtained.
[0042]
According to this embodiment, since the semiconductor elements 70a and 70b are mounted using the metal plating bumps 64, mounting can be performed more reliably.
[0043]
(Fourth embodiment)
The manufacture of the semiconductor device according to the third embodiment of the present invention will be described below. FIG. 10 is a flowchart of a method for manufacturing a semiconductor device according to the present embodiment, and FIGS. 11 and 12 are cross-sectional views of the semiconductor device according to the present embodiment being manufactured.
[0044]
In order to manufacture the semiconductor device according to the present embodiment, the two-layer plate 51 is formed according to the steps 1 to 8 shown in FIGS. 1A to 1E of the first embodiment.
[0045]
Next, as shown in FIG. 11F, a Cu layer 65 is formed on the surface of the two-layer plate 51 by a method such as attaching a metal plate or metal layer such as a copper foil or plating (step 1c). Next, in the wiring pattern 41a, as shown in FIG. 11G, masking 82 is performed on the upper surface of the Cu layer 65 at positions corresponding to the electrode pads 41b, 41b,... Formed at positions corresponding to the electrodes of the semiconductor element. , 82,... (Step 2c).
[0046]
Etching bumps 66, 66,... As shown in FIG. 11 (h) are formed by performing an etching process on the Cu layer 65 on which the masks 82, 82,... Are formed (step 3c). Then, as shown in FIG. 11 (i), the masking 82, 82,... Is removed (step 4c) to expose the etching bumps 66, 66,. (Step 5c) is performed. Next, a Ni layer 61 as a barrier metal layer as shown in FIG. 11 (j) is formed, and Au plating (step 6c) is further performed thereon, as shown in FIG. 11 (k). An Au layer 62 is formed.
[0047]
Thereafter, similarly to the first embodiment, as shown in FIG. 12L, the ACF 63 is formed, and the semiconductor elements 70a and 70b are aligned (step 7c). Next, as shown in FIG. 12 (m), by pressing and mounting (step 8c), a semiconductor device (multichip module) 1C as shown in FIG. 12 (m) is obtained.
[0048]
According to this embodiment, since the semiconductor element 70 is mounted using the metal etching bump 66, it can be mounted more reliably.
[0049]
【The invention's effect】
According to the present invention, since the semiconductor element is mounted on the two-layer board via the mounting bump formed by printing the conductive paste, the semiconductor device can be manufactured at high production speed, high quality, and low manufacturing cost. Can be obtained.
[Brief description of the drawings]
FIG. 1 is a flowchart of a method for manufacturing a semiconductor device according to a first embodiment.
FIG. 2 is a flowchart of a manufacturing method of the semiconductor device according to the first embodiment.
FIG. 3 is a cross-sectional view of the semiconductor device according to the first embodiment that is being manufactured;
FIG. 4 is a cross-sectional view of the semiconductor device according to the first embodiment that is being manufactured;
FIG. 5 is a cross-sectional view of the semiconductor device according to the first embodiment that is being manufactured;
FIG. 6 is a cross-sectional view of a semiconductor device according to a second embodiment.
FIG. 7 is a flowchart of a method for manufacturing a semiconductor device according to a third embodiment.
FIG. 8 is a cross-sectional view of a semiconductor device according to a third embodiment that is being manufactured;
FIG. 9 is a cross-sectional view of a semiconductor device according to a third embodiment that is being manufactured;
FIG. 10 is a flowchart of a method for manufacturing a semiconductor device according to a fourth embodiment.
FIG. 11 is a cross-sectional view of a semiconductor device in the middle of manufacture according to a fourth embodiment.
FIG. 12 is a cross-sectional view of a semiconductor device according to a fourth embodiment that is being manufactured;
FIG. 13 is a cross-sectional view of a conventional semiconductor device.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Semiconductor device, 51 ... Two-layer board, 41a ... Wiring pattern, 41b ... Electrode pad, 60 ... Mounting bump, 61 ... Ni layer (barrier metal layer), 62 ... Au layer, 63 ... ACF, 64 ... ACF, 70 ... semiconductor element, 71 ... electrode plate.

Claims (6)

第１の面と第２の面を有する絶縁性基板の第１の面に、実装される複数の半導体素子の各電極と対応する位置に電極パッドを有する配線パターンが形成され、第２の面には複数の電極板が形成され、前記配線パターンと前記各電極板が前記絶縁性基板を貫通する層間接続導体により接続された配線基板を形成する工程と、
前記配線基板の第１の面の前記配線パターンの電極パッド上に一括して導体バンプを形成する工程と、
前記配線基板の第１の面の前記導体バンプの形成された電極パッド上に異方導電性組成物を塗布する工程と、
前記配線基板の第１の面の電極パッドと実装すべき半導体素子の電極とを位置合わせする工程と、
位置合わせの行われた前記半導体素子と前記配線基板とを加熱下に加圧して前記導体バンプと前記電極とを接合する工程と、
前記配線基板の第２の面に形成した複数の電極板上に他の配線基板に接続するための外部接続端子を設ける工程と
を具備することを特徴とする複数の半導体素子の実装された半導体装置の製造方法。On the first surface of the insulating substrate having the first surface and the second surface , a wiring pattern having electrode pads is formed at positions corresponding to the respective electrodes of the plurality of semiconductor elements to be mounted. a plurality of electrode plates are formed, the step of the said wiring pattern electrode plates to form a wiring board connected by an interlayer connection conductor which penetrates the insulating substrate, the
Forming conductor bumps collectively on the electrode pads of the wiring pattern on the first surface of the wiring board ;
Applying an anisotropic conductive composition on the electrode pads on which the conductive bumps are formed on the first surface of the wiring board ;
A step of aligning the electrode of the semiconductor element to be mounted to the electrode pads of the first surface of the wiring substrate,
Bonding the conductor bump and the electrode by applying pressure to the semiconductor element and the wiring board that have been aligned under heating; and
It mounted semiconductor of a plurality of semiconductor elements, characterized by comprising a step of providing an external connection terminal for connection to another wiring board on a plurality of electrode plates formed on the second surface of the wiring substrate Device manufacturing method. 請求項１に記載の半導体装置の製造方法であって、
前記外部接続端子を設ける工程がハンダペーストボールを付着させる工程であることを特徴とする半導体装置の製造方法。A method of manufacturing a semiconductor device according to claim 1,
The method of manufacturing a semiconductor device, wherein the step of providing the external connection terminal is a step of attaching a solder paste ball. 請求項１に記載の半導体装置の製造方法であって、
前記外部接続端子を設ける工程が印刷により導電ペーストバンプを形成する工程であることを特徴とする半導体装置の製造方法。A method of manufacturing a semiconductor device according to claim 1,
The method of manufacturing a semiconductor device, wherein the step of providing the external connection terminal is a step of forming a conductive paste bump by printing. 請求項１乃至３のいずれか１項に記載の半導体装置の製造方法であって、
前記導体バンプを形成する工程が、孔を備えた型板の上から導電ペーストをすりこみ、しかる後に前記型板を剥がすことにより導電ペーストバンプを形成する工程であることを特徴とする半導体装置の製造方法。A method for manufacturing a semiconductor device according to any one of claims 1 to 3,
The step of forming the conductor bump is a step of forming a conductive paste bump by rubbing a conductive paste from above a template having holes, and then peeling off the template. Method. 請求項１乃至３のいずれか１項に記載の半導体装置の製造方法であって、
前記導体バンプを形成する工程が、前記配線パターン形成面上にバンプ形成用の孔を備えたマスキングを形成し、前記マスキングの孔内に金属を析出することによりメッキバンプを形成する工程であることを特徴とする半導体装置の製造方法。A method for manufacturing a semiconductor device according to any one of claims 1 to 3,
The step of forming the conductor bump is a step of forming a plating bump by forming a mask having a hole for forming a bump on the wiring pattern forming surface and depositing a metal in the hole of the masking. A method of manufacturing a semiconductor device. 請求項１乃至５のいずれか１項に記載の半導体装置の製造方法であって、前記バンプ形成後、前記バンプ表面にバリアメタル層を形成する工程と、前記バリアメタル層表面に溶接金属層を形成する工程を更に具備することを特徴とする半導体装置の製造方法。A method of manufacturing a semiconductor device according to any one of claims 1 to 5, after the bump forming, a step of forming a barrier metal layer on the bump surface, the weld metal layer on the barrier metal layer surface The manufacturing method of the semiconductor device characterized by further comprising the process of forming.
JP2002237127A 2001-09-27 2002-08-15 Manufacturing method of semiconductor device Expired - Fee Related JP3966786B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2002237127A JP3966786B2 (en) 2001-09-27 2002-08-15 Manufacturing method of semiconductor device

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2001-298291 2001-09-27
JP2001298291 2001-09-27
JP2002237127A JP3966786B2 (en) 2001-09-27 2002-08-15 Manufacturing method of semiconductor device

Publications (2)

Publication Number Publication Date
JP2003174060A JP2003174060A (en) 2003-06-20
JP3966786B2 true JP3966786B2 (en) 2007-08-29

Family

ID=26623159

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002237127A Expired - Fee Related JP3966786B2 (en) 2001-09-27 2002-08-15 Manufacturing method of semiconductor device

Country Status (1)

Country Link
JP (1) JP3966786B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090020870A1 (en) * 2005-04-05 2009-01-22 Shinji Watanabe Electronic device provided with wiring board, method for manufacturing such electronic device and wiring board for such electronic device

Also Published As

Publication number Publication date
JP2003174060A (en) 2003-06-20

Similar Documents

Publication Publication Date Title
JP3889856B2 (en) Method for manufacturing printed wiring board with protruding electrodes
KR100495957B1 (en) Wiring Circuit Substrate and Manufacturing Method Therefor
JP4418833B2 (en) Circuit board manufacturing method
US8152953B2 (en) Method of making printed wiring board and method of making printed circuit board unit
JP4040389B2 (en) Manufacturing method of semiconductor device
US20090294160A1 (en) Method of making printed wiring board and electrically-conductive binder
JP2002050871A (en) Build-up circuit board and manufacturing method thereof
JPH06120670A (en) Multilayer wiring board
JP4378511B2 (en) Electronic component built-in wiring board
JP2013512581A (en) Printed circuit board and manufacturing method thereof
JP2003007916A (en) Method of manufacturing circuit device
JP2003007917A (en) Method manufacturing circuit device
JP4416874B2 (en) Manufacturing method of semiconductor chip
US8062927B2 (en) Wiring board and method of manufacturing the same, and electronic component device using the wiring board and method of manufacturing the same
JP3966786B2 (en) Manufacturing method of semiconductor device
JP4593599B2 (en) Manufacturing method of wiring board with built-in electronic components
JP2009212160A (en) Wiring board and manufacturing method therefor
JP2014220402A (en) Method of semiconductor package substrate
JP4794714B2 (en) Semiconductor integrated circuit device and manufacturing method thereof
JP3918828B2 (en) Semiconductor device
JP3682500B2 (en) Printed wiring board and method for manufacturing printed wiring board
JP4330855B2 (en) Wiring board manufacturing method
JP4161463B2 (en) Chip carrier manufacturing method
JP4040388B2 (en) Manufacturing method of semiconductor device
JP2003174059A (en) Semiconductor device and manufacturing method therefor

Legal Events

Date Code Title Description
A625 Written request for application examination (by other person)

Free format text: JAPANESE INTERMEDIATE CODE: A625

Effective date: 20050811

A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A711

Effective date: 20060215

Free format text: JAPANESE INTERMEDIATE CODE: A712

Effective date: 20060215

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20061128

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20061205

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20070205

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20070227

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20070501

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20070529

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20070529

R150 Certificate of patent (=grant) or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110608

Year of fee payment: 4

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110608

Year of fee payment: 4

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120608

Year of fee payment: 5

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120608

Year of fee payment: 5

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130608

Year of fee payment: 6

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140608

Year of fee payment: 7

LAPS Cancellation because of no payment of annual fees