JP2004031818A - Package for storing semiconductor element and semiconductor device - Google Patents

Package for storing semiconductor element and semiconductor device Download PDF

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Publication number
JP2004031818A
JP2004031818A JP2002188459A JP2002188459A JP2004031818A JP 2004031818 A JP2004031818 A JP 2004031818A JP 2002188459 A JP2002188459 A JP 2002188459A JP 2002188459 A JP2002188459 A JP 2002188459A JP 2004031818 A JP2004031818 A JP 2004031818A
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Japan
Prior art keywords
electrode
base
semiconductor element
conductor
package
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JP2002188459A
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Japanese (ja)
Inventor
Yoshiaki Ueda
植田 義明
Masakazu Yasui
安井 正和
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Kyocera Corp
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Kyocera Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To obtain sufficient reliability of electric connection by increasing the junction strength of a lead pin. <P>SOLUTION: A semiconductor element storing package is provided with a base body 1 consisting of ceramics and forming a loading part of a semiconductor element A consisting of a metalized layer 2 on the upper surface, an approximately circular electrode 5 formed on the lower surface of the base body 1 and electrically connected to the metalized layer 2 through through-conductors 3 whose cross section is approximately circular, and a lead pin 6 in which an approximately circular large diameter part 6a formed on one end is coaxially brazed to the electrode 5. When it is defined that the diameter of the large diameter part 6a is R, three through-conductors 3 are arranged at an approximately equal interval so that the lower ends of the through-conductors 3 are inscribed with the circumference of a circle having a diameter of 0.8-1.0R whose center coincides with the center of the electrode 5, and the lower ends of the three through conductors 3 are projected from the lower surface of the base body 1 by approximately the same length of R/8-R/4 to form projected parts 8 on the electrode 5. <P>COPYRIGHT: (C)2004,JPO

Description

【0001】
【発明の属する技術分野】
本発明は、LSI,ICなどの半導体素子を収容するピングリッドアレイパッケージやフラットパッケージ等として用いられる半導体素子収納用パッケージおよび半導体装置に関する。
【0002】
【従来の技術】
従来、アルミナ質焼結体(アルミナセラミックス)や窒化アルミニウム質焼結体等からなるPGA(Pin Grid Array)パッケージやフラットパッケージにおけるリードピンの接合構造としては、図3に示すような構造が一般的であった。すなわち、例えばアルミナセラミックスからなる基体1の上面に、タングステン(W)やモリブデン(Mo)、マンガン(Mn)などからなる、半導体素子Aの搭載部としてのメタライズ層2が形成されている。
【0003】
このメタライズ層2は、基体1を上下方向に貫通する複数本の貫通導体3によって内層導体層4に接続されるとともに、下面の電極5に接続される。メタライズ層2や電極5の表面には、ニッケル(Ni)、またはNiおよび金(Au)からなるメッキ層が形成されており、Fe(鉄)−Ni−Co(コバルト)合金やFe−Ni合金からなるリードピン6の一端の大径部6aが、銀(Ag)ロウ7を介して接合されている。
【0004】
この接合に際しては、ロウ材からなる半球状の先端部(バンプ)を大径部6a上に有するリードピン6を、カーボン治具に形成された所定の貫通穴に大径部6aを上にして予め配置しておき、リードピン6上に基体1の下面の電極5が当接するようにして基体1を載置し、必要な荷重をかけながらブレージング炉で加熱することによってリードピン6が電極5に接合され立設する。
【0005】
また、貫通導体3と基体1とを隙間なく接合させるために、貫通導体3となる導体ペーストの収縮率は基体1となるセラミックグリーンシートの収縮率よりも若干小さく設定されており、そのため貫通導体3は基体1の下面から数μm〜十数μm突出している。
【0006】
そして、厚さが十数μm〜30μmの電極5が貫通導体3の下端面を覆うように形成されることにより、基体1上面のメタライズ層2と電気的に接続される。このとき、基体1下面で突出している貫通導体3の下端部に相当する電極5の部位は、数μm〜十数μmの長さで下方に突出している。
【0007】
【発明が解決しようとする課題】
しかしながら、上記従来の半導体素子収納用パッケージにおいては、大径部6aと電極5との接合に際して、予め大径部6aに設けられたバンプが加熱されて溶解する際に、リードピン6の長さや大径部6aの厚さにバラツキがあるため、大径部6aと電極5との間のAgロウの厚さが数μm〜十数μmと薄くなるものが生ずる。この場合、大径部6aと電極5との間に溜まるべきAgロウが外に押し出され、大径部6aの側面にAgロウが多く溜まって良好なメニスカスが形成されなくなり、リードピン6の接合強度が劣化することになる。
【0008】
また、リードピン6の大径部6aの側面に溜まったAgロウが、電極5の外周部に流れてこの付近の電極5の熱膨張を高めに変化させてしまい、例えば−55〜+125℃のヒートサイクル試験を行うと、電極5の外周部から基体1の内部方向にマイクロクラックが発生して、その後リードピン6の引張り試験を行うと電極5がその外周部から基体1をえぐるようにして剥れてしまうことがあった。このように、従来の引張り強度の半分以下の強度で電極5が基体1から剥がれる場合があった。
【0009】
また、貫通導体3の導体抵抗が導体ペーストの充填不良により大きくなったり、貫通導体3が途中で断線するという不具合が発生する場合があった。
【0010】
従って、本発明は上記従来の問題点に鑑みて完成されたものであり、その目的は、基板の下面に接合したリードピンが容易に剥がれることがなく、信頼性の高い半導体パッケージを提供することにある。
【0011】
【課題を解決するための手段】
本発明の半導体素子収納用パッケージは、上面にメタライズ層から成る半導体素子の搭載部が形成されたセラミックスから成る基体と、該基体の下面に形成され、断面が略円形の貫通導体を介して前記メタライズ層に電気的に接続された略円形の電極と、一端に形成された略円形の大径部が前記電極に同軸状にロウ付けされたリードピンとを具備しており、前記貫通導体は、前記大径部の直径をRとしたとき、前記電極の中心を中心とし0.8R〜Rの直径を有する円の円周に下端が内接するようにして3本が略等間隔に配置されているとともに、それら3本の下端が前記基体の下面からR/8〜R/4の略同じ長さで突出してそれぞれ前記電極に突出部を形成していることを特徴とする。
【0012】
本発明の半導体素子収納用パッケージは、貫通導体は、リードピンの大径部の直径をRとしたとき、電極の中心を中心とし0.8R〜Rの直径を有する円の円周に下端が内接するようにして3本が略等間隔に配置されているとともに、それら3本の下端が基体の下面からR/8〜R/4の略同じ長さで突出してそれぞれ電極に突出部を形成していることから、半導体素子収納用パッケージがブレージング炉で加熱された際に、リードピンの大径部上に設けられたロウ材のバンプが溶解することにより、貫通導体の下端に形成された電極の表面において、下方に突出して形成された突出部に大径部が接触する状態となりブレージングが完了する。このとき、ロウ材が電極の突出部の表面にも流れて突出部間にロウ材が速やかに行き渡ることとなり、よって大径部の側面から電極の突出部の周囲にかけて良好な形状のメニスカスが速やかに生成される。従って、大径部と電極との隙間に溜まったロウ材と併せてリードピンの強固な接合を実現することができる。
【0013】
本発明の半導体装置は、上記本発明の半導体素子収納用パッケージと、前記搭載部に下面が接合されて搭載された半導体素子と、該半導体素子の上方を覆うように前記基体の上面の外周部に接合された蓋体とを具備したことを特徴とする。
【0014】
本発明の半導体装置は、上記の構成により、上記本発明の半導体素子収納用パッケージを用いた信頼性が高いものとなる。
【0015】
【発明の実施の形態】
本発明の半導体素子収納用パッケージを以下に詳細に説明する。図1,図2は本発明の半導体パッケージについて実施の形態の一例を示すものであり、図1は半導体パッケージの断面図、図2(a)は半導体パッケージの要部拡大断面図、(b)は要部拡大平面図である。図1において、1は基体、2はメタライズ層、3は貫通導体、3aは下端、4は導体層、5は電極、6はリードピン、6aは大径部、7はロウ材、7aはメニスカスである。また図2において、8は突出部を示す。
【0016】
本発明の半導体パッケージは、上面にメタライズ層2から成る半導体素子Aの搭載部が形成されたセラミックスから成る基体1と、基体1の下面に形成され、断面が略円形の貫通導体3を介してメタライズ層2に電気的に接続された略円形の電極5と、一端に形成された略円形の大径部6aが電極5に同軸状にロウ付けされたリードピン6とを具備し、貫通導体3は、大径部6aの直径をRとしたとき、電極5の中心を中心とし0.8R〜Rの直径を有する円の円周に下端が内接するようにして3本が略等間隔に配置されているとともに、それら3本の下端が基体1の下面からR/8〜R/4の略同じ長さで突出してそれぞれ電極5に突出部8を形成している。
【0017】
本発明の基体1は、半導体素子Aの搭載部としてのメタライズ層2が上面に、電極5が下面に形成されており、メタライズ層2と電極5とは基体1の内部に形成された貫通導体3により互いに電気的に接続されている。また、メタライズ層2および電極5は、表面の酸化を防止するとともにロウ材7との濡れ性を良好にするために、ニッケル(Ni)メッキ層や金(Au)メッキ層などのメッキ層を被着させておくと良い。
【0018】
半導体素子Aは、例えば基体1の上面に半田を介して接合されている。また、基体1の電極5にはロウ材7を介してリードピン6が接合されている。リードピン6は半導体素子Aを外部の電気回路装置に接合するために用いられる。
【0019】
この基体1を有する半導体パッケージは以下のようにして作製される。基体1が酸化アルミニウム(Al)質焼結体(セラミックス)から成る場合、Al粉末に焼結助材としてシリカ(SiO),マグネシア(MgO),カルシア(BaO)等の粉末を添加し、さらに適当なバインダ、溶剤および可塑剤を添加し、次にこれらの混合物を混錬してスラリー状となす。その後、従来周知のドクターブレード法等の成形方法によって多数個取り用のセラミックグリーンシートを得る。
【0020】
このセラミックグリーンシートを用いて以下の[1]〜[11]で示す工程により基体1が作製される。
【0021】
[1]貫通導体3を上面から下面にかけて形成するための貫通孔を打ち抜き法で形成する。
【0022】
[2]貫通孔にタングステンを主成分とする導体ペーストを充填する。
【0023】
[3]メタライズ層2および電極5となる導体層をスクリーン印刷法により形成する。
【0024】
[4]セラミックグリーンシートを積層してセラミックグリーンシート積層体を作製する。
【0025】
[5]貫通孔に充填された貫通導体3となる導体の下端面に、導体ペーストをスクリーン印刷法により印刷することにより、突出部8となる柱状導体を形成する。このとき、柱状導体の高さはスクリーン印刷において版に貼りつける目止め用樹脂の厚さを変えることによって任意な高さとすることができる。また、乾燥後にグリーンシートを低圧でプレスすることで柱状導体の高さを略揃えることができる。
【0026】
そして、突出部8が形成されることにより、リードピン6をロウ材7を介して接合するに際し、リードピン6は大径部6aとメタライズ層2との間で速やかに均一なメニスカス7aが形成され、またその表面積を略一定とすることができ、これにより強固かつ信頼性の高い接合構造を実現できる。
【0027】
[6]このセラミックグリーンシート積層体を個々の基体1となる積層体に切断分離し、これらを例えば約1600℃の高温で約2時間焼成して各導体層を有する焼結体を得る。このとき、基体1は突出部8が形成される下面を上にして焼成され、よって基体1の下面において基体1から突出する突出部8が形成される。
【0028】
本発明の貫通導体3は、大径部6aの直径をRとしたとき、電極5の中心を中心とし0.8R〜Rの直径を有する円5a{図2(b)}の円周に下端が内接するようにして3本が略等間隔に配置されているとともに、それら3本の下端が基体1の下面からR/8〜R/4の略同じ長さで突出している。
【0029】
円5aの直径が0.8R未満では、突出部8によるメニスカス7aの誘導形成が困難になり、接合強度が小さくなり易い。また、円5aの直径がRを超えると、リードピン6が斜めに傾いて接合されてしまう場合がある。
【0030】
また突出部8の高さ(上下方向の長さ)がR/8未満では、メニスカス7aの面積が小さくなるとともに、大径部6aと電極5との間におけるロウ材7の体積が少なくなるため、リードピン6の充分な接合強度が得られなくなる傾向がある。突出部8の高さがR/4を超えると、ロウ材7中にボイドが発生し易くなり、このボイドにより接合強度が小さくなったり、導体抵抗が増加して、例えば高周波信号を伝送する場合に伝送遅延などを招来してしまう。
【0031】
[7]各導体層を保護して酸化防止するとともにロウ付けを容易にするために、Niメッキ層やAuメッキ層から成る金属メッキ層を各導体層の表面に被着する。
【0032】
[8]リードピン6の大径部6aに、ロウ材7となる例えば円柱状のAgロウを横にして接着剤などで仮止めした状態で、非酸化性雰囲気とされたブレージング炉内で約900℃の温度で溶融させることにより、大径部6aにAgロウから成る半球状の先端部(バンプ)を形成する。
【0033】
[9]複数のリードピン6を、これを挿通させる孔が所定の間隔で複数穿設されたカーボン治具(図示せず)を用いて基体1表面の所定位置に配置する。このとき、予めカーボン治具の各孔にリードピン6を振動させながら振り込ませることのできる治具を用意し、各孔にリードピン6の本体を下にして1本ずつ挿入する。リードピン6の表面には、酸化防止とロウ材7や半田との濡れ性を向上させるために、厚さ0.5〜9μmのNiメッキ層などの金属メッキ層をあらかじめ被着させておくと良い。
【0034】
[10]基体1をカーボン治具上に、基体1の電極5が各リードピン6の大径部6aに当接するように載置し、ブレージング炉中で870℃程度の温度で加熱することにより、基体1の所定位置にリードピン6をロウ材7を介して突設する。
【0035】
[11]リードピン6が突設された半導体パッケージの全体に厚さ0.5〜9μmのNiメッキ層および厚さ0.5〜5μmのAuメッキ層を被着する。
【0036】
以上の工程により、基体1は、ロウ材7を介してリードピン6が下面の電極5に突設された状態となり、リードピン6の接合部には突出部8の作用によりロウ材7による良好な形状のメニスカス7aが形成されるとともに接合強度を確保するのに充分な体積のロウ材7が接合部に保持された状態となる。その結果、リードピン6の接合強度が向上するとともに、リードピン6を介して伝送される高周波信号の反射損失を小さくすることができ、半導体装置として良好な作動状態が得られる。
【0037】
また、それぞれの電極5に対して3本形成した貫通導体3のいずれかが導通不良となったとしても、残る貫通導体によってカバーされるので、導体抵抗異常や断線不良は解消される。この貫通導体3の直径は0.15〜0.3mm程度が好ましい。0.15mm未満では、量産性に難がある。0.3mmを超えると、電極5の面積を大きくしなければならなくなり、そのために基体1の大きさが大きくなってしまう。
【0038】
さらに、メニスカス7aは、突出部8が形成されているために、突出部8によってロウ材7の流れが誘導され、ロウ材7の流れ性が良好となり、その結果、表面が極めて滑らかなものとなっている。
【0039】
上記のようにして得られた基体1の搭載部に半導体素子Aを固定し、基体1の上面の外周部にキャップ状等の蓋体を接合したり、基体1の上面の外周部に枠体を介して板状の蓋体を接合することにより、半導体装置が得られる。そして、リードピン6が、外部電気回路基板等における半田バンプが予め形成された電極上に当接され、半田が再溶融する温度に加熱される。これにより、リードピン6が半田を介して外部電気回路基板等の電極に接合され、半導体装置と外部電気回路装置との電気的な接合がなされる。
【0040】
本発明の半導体装置は、本発明の半導体パッケージと、搭載部に下面が接合されて搭載された半導体素子Aと、半導体素子Aの上方を覆うように基体1の上面の外周部に接合された蓋体とを具備している。本発明の半導体装置は、接合の信頼性が良くかつ接合強度が大きいリードピン6を介して高周波信号を半導体素子Aに伝送することができる。従って、大容量の情報を高速に処理する半導体装置として機能し、LSI用以外に例えばMCM(Multi Chip Module)等にも好適に用いられる。
【0041】
【実施例】
本発明の半導体素子収納用パッケージの実施例を以下に説明する。
【0042】
まず、電極5におけるリードピン6を接合する円5aの直径を種々に設定したサンプルを以下の工程[1]〜[5]のようにして作製した。
【0043】
[1]厚さが1.5mm、縦約20mm、横約30mmのセラミックグリーンシートにおいて、電極5に対する円5aの位置を次のようにした。電極5の直径を2mmとし、リードピン6の大径部6aの直径Rを0.5,0.75,1,1.25,1.5(mm)として、Rが0.5mmの場合に円5aの直径を0.35,0.4,0.45,0.5,0.55(mm)とし、Rが0.75mmの場合に円5aの直径を0.525,0.6,0.675,0.75,0.825(mm)とし、Rが1mmの場合に円5aの直径を0.7,0.8,0.9,1、1.1(mm)とし、Rが1.25mmの場合に円5aの直径を0.875,1,1.125,1.25,1.375(mm)とし、Rが1.5mmの場合に円5aの直径を1.05,1.2,1.35,1.5,1.65mmとした。
【0044】
[2]上記セラミックグリーンシートにおいて上記円5aの円周に内接するようにして、円周を3等分した位置に焼成後に直径が0.15mmとなる貫通孔を、一つの電極5に対して3本を1セットとして10セットを打抜き法で形成した。得られた貫通孔に、タングステンを主成分とする粘度が約10000ポイズの導体ペーストを圧入した。これを各場合につき2枚ずつ作製した。次に、電極5となる導体層をスクリーン印刷法で2枚のうち1枚の上面に形成した。
【0045】
[3]セラミックグリーンシート2枚を積層して、厚さが3mmの積層体を得た。
【0046】
[4]積層体における3本の貫通導体3の下端に柱状導体をスクリーン印刷法で形成し、次いで80℃で乾燥した後、100kgf/cmの圧力でグリーンシートを加圧して表面を略平坦なものとし、その後電極5となる導体パターンをスクリーン印刷法により形成した。このとき柱状導体の高さを変えて実施例に用いるテスト用基板となる積層体とした。
【0047】
[5]次いで、80℃で乾燥後、1600℃で焼成して、25枚のテスト用基板を得た。このテスト用基板に、バンプが上端面に設けられるとともに直径が1mmの大径部6aを有するリードピン6を870℃の非酸化性雰囲気で接合した。
【0048】
このようにして得られたテスト用基板について、リードピン6を上方に引張る引張り試験を行った結果を表1に示す。
【0049】
【表1】

Figure 2004031818
【0050】
表1より、電極5に対する円5aの直径は0.8R〜Rである必要があることが判明した。本実施例では、リードピン6の傾斜は数度という僅かなものであったが、この傾斜が多ピンの製品で発生すると修正に多大の時間と労力が必要となる。また、メニスカス7aの不均一は表面の形成時間に部分的に差が生じたことで発生したと思われ、この場合、接合強度の差となって現われている。
【0051】
次に、円5aの直径を0.9Rとして、Rを0.6,0.8,1,1.2,1.4(mm)とし、Rが0.6mmの場合に突出部8の高さを50,75,100,125,150,175(μm)とし、Rが0.8mmの場合に突出部8の高さを80,100,150,175,200,220(μm)とし、Rが1mmの場合に突出部8の高さを100,125,150,200,250,300(μm)とし、Rが1.2mmの場合に突出部8の高さを125,150,200,250,300,350(μm)とし、Rが1.4mmの場合に突出部8の高さを150,175,250,300,350,375(μm)として、突出部8の高さを変えたサンプルを各場合について10個ずつ1枚の基板に作製することで、計36枚のテスト用基板を作製し、リードピンの接合強度およびロウ付け部の状態の良否を評価した。その結果を表2に示す。
【0052】
【表2】
Figure 2004031818
【0053】
表2より、突出部8の高さが小さい場合は接合強度が劣化することが判明した。これはメニスカスの生成状態が不良であり、さらにロウ材7の体積が小さいことによるものと思われる。また、突出部8の高さが高すぎる場合には、ロウ材7の内部にボイドが発生する場合があり、この場合、接合強度が低下した。
【0054】
なお、本発明は上記実施の形態および実施例に限定されず、本発明の要旨を逸脱しない範囲内で種々の変更を施すことは何等支障ない。
【0055】
【発明の効果】
本発明の半導体素子収納用パッケージは、上面にメタライズ層から成る半導体素子の搭載部が形成されたセラミックスから成る基体と、基体の下面に形成され、断面が略円形の貫通導体を介してメタライズ層に電気的に接続された略円形の電極と、一端に形成された略円形の大径部が電極に同軸状にロウ付けされたリードピンとを具備し、貫通導体は、大径部の直径をRとしたとき、電極の中心を中心とし0.8R〜Rの直径を有する円の円周に下端が内接するようにして3本が略等間隔に配置されているとともに、それら3本の下端が基体の下面からR/8〜R/4の略同じ長さで突出してそれぞれ電極に突出部を形成していることにより、半導体素子収納用パッケージがブレージング炉で加熱された際に、リードピンの大径部上に設けられたロウ材のバンプが溶解するとともに、貫通導体の下端に形成された電極の表面において、下方に突出して形成された突出部に大径部が接触する状態となり、ブレージングが完了するが、このときロウ材が電極の突出部の表面にも流れて突出部間にロウ材が速やかに行き渡ることとなり、よって大径部の側面から電極の突出部の周囲にかけて良好な形状のメニスカスが速やかに生成される。従って、大径部と電極との隙間に溜まったロウ材と併せてリードピンの強固な接合を実現することができる。
【0056】
本発明の半導体装置は、上記本発明の半導体素子収納用パッケージと、搭載部に下面が接合されて搭載された半導体素子と、半導体素子の上方を覆うように基体の上面の外周部に接合された蓋体とを具備したことにより、上記本発明の半導体素子収納用パッケージを用いた信頼性が高いものとなる。
【図面の簡単な説明】
【図1】本発明の半導体素子収納用パッケージについて実施の形態の一例を示す断面図である。
【図2】(a)は図1の半導体素子収納用パッケージにおけるリードピン周辺を示す要部拡大断面図であり、(b)は(a)のリードピン周辺を示す要部拡大平面図である。
【図3】従来の半導体素子収納用パッケージの断面図である。
【符号の説明】
1:基体
2:メタライズ層
3:貫通導体
3a:下端
5:電極
5a:円
6:リードピン
6a:大径部
7:ロウ材
8:突出部
A:半導体素子[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor element housing package and a semiconductor device used as a pin grid array package or flat package for housing semiconductor elements such as LSIs and ICs.
[0002]
[Prior art]
Conventionally, as a joining structure of lead pins in a PGA (Pin Grid Array) package or a flat package made of an alumina-based sintered body (alumina ceramics) or an aluminum nitride-based sintered body, a structure as shown in FIG. there were. That is, a metallized layer 2 made of tungsten (W), molybdenum (Mo), manganese (Mn), or the like, as a mounting portion of the semiconductor element A, is formed on the upper surface of a substrate 1 made of, for example, alumina ceramics.
[0003]
The metallized layer 2 is connected to the inner conductor layer 4 by a plurality of through conductors 3 penetrating the base 1 in the vertical direction, and is connected to the electrode 5 on the lower surface. A plating layer made of nickel (Ni) or Ni and gold (Au) is formed on the surface of the metallized layer 2 and the electrode 5, and is made of an Fe (iron) -Ni-Co (cobalt) alloy or an Fe-Ni alloy. A large-diameter portion 6a at one end of a lead pin 6 is joined via a silver (Ag) solder 7.
[0004]
In this joining, a lead pin 6 having a hemispherical tip portion (bump) made of brazing material on the large diameter portion 6a is inserted into a predetermined through hole formed in the carbon jig with the large diameter portion 6a facing up. The base 1 is placed in such a manner that the electrode 5 on the lower surface of the base 1 abuts on the lead pin 6, and the lead pin 6 is joined to the electrode 5 by heating in a brazing furnace while applying a required load. Stand up.
[0005]
Further, in order to join the through conductor 3 and the base 1 without gaps, the shrinkage of the conductor paste that becomes the through conductor 3 is set to be slightly smaller than the shrinkage of the ceramic green sheet that becomes the base 1. Reference numeral 3 protrudes from the lower surface of the base 1 by several μm to several tens μm.
[0006]
The electrode 5 having a thickness of more than 10 μm to 30 μm is formed so as to cover the lower end surface of the through conductor 3, so that the electrode 5 is electrically connected to the metallized layer 2 on the upper surface of the base 1. At this time, the portion of the electrode 5 corresponding to the lower end of the through conductor 3 protruding from the lower surface of the base 1 protrudes downward with a length of several μm to several tens μm.
[0007]
[Problems to be solved by the invention]
However, in the above-mentioned conventional package for housing a semiconductor element, when the large diameter portion 6a and the electrode 5 are joined and the bumps provided on the large diameter portion 6a are heated and melted in advance, the length and length of the lead pin 6 are increased. Since the thickness of the diameter portion 6a varies, the thickness of the Ag solder between the large diameter portion 6a and the electrode 5 may be as thin as several μm to several tens μm. In this case, Ag solder to be accumulated between the large-diameter portion 6a and the electrode 5 is pushed out, and a large amount of Ag wax accumulates on the side surface of the large-diameter portion 6a to prevent a good meniscus from being formed. Will deteriorate.
[0008]
Also, Ag solder accumulated on the side surface of the large diameter portion 6a of the lead pin 6 flows to the outer peripheral portion of the electrode 5 and changes the thermal expansion of the electrode 5 in the vicinity thereof to a higher value. When the cycle test is performed, microcracks are generated from the outer peripheral portion of the electrode 5 toward the inside of the base 1. Thereafter, when the tensile test of the lead pin 6 is performed, the electrode 5 peels off from the outer peripheral portion so as to go through the base 1. Sometimes happened. As described above, there is a case where the electrode 5 is peeled off from the base 1 at a strength less than half of the conventional tensile strength.
[0009]
In addition, there have been cases where the conductor resistance of the through conductor 3 becomes large due to insufficient filling of the conductor paste, or the through conductor 3 is disconnected in the middle in some cases.
[0010]
Accordingly, the present invention has been completed in view of the above conventional problems, and an object of the present invention is to provide a highly reliable semiconductor package in which a lead pin bonded to a lower surface of a substrate is not easily peeled off. is there.
[0011]
[Means for Solving the Problems]
The package for accommodating a semiconductor element of the present invention includes a base made of ceramics on which a mounting portion of a semiconductor element formed of a metallized layer is formed on an upper surface, and a through conductor formed on the lower surface of the base and having a substantially circular cross section. A substantially circular electrode electrically connected to the metallization layer, and a substantially circular large-diameter portion formed at one end includes a lead pin coaxially brazed to the electrode, and the through conductor includes: When the diameter of the large diameter portion is R, three are arranged at substantially equal intervals such that the lower end is inscribed in the circumference of a circle having a diameter of 0.8R to R with the center of the electrode as the center. In addition, the three lower ends protrude from the lower surface of the base with substantially the same length of R / 8 to R / 4 to form protrusions on the electrodes.
[0012]
In the package for housing a semiconductor element of the present invention, when the diameter of the large diameter portion of the lead pin is R, the through conductor has a lower end inside the circumference of a circle having a diameter of 0.8R to R centered on the center of the electrode. Three of them are arranged at substantially equal intervals so as to be in contact with each other, and the lower ends of the three project from the lower surface of the base with substantially the same length of R / 8 to R / 4 to form projecting portions on the respective electrodes. Therefore, when the semiconductor element housing package is heated in the brazing furnace, the solder bumps provided on the large diameter portions of the lead pins are melted, thereby forming the electrodes formed at the lower ends of the through conductors. At the surface, the large-diameter portion comes into contact with the protruding portion formed to protrude downward, and the brazing is completed. At this time, the brazing material also flows on the surface of the protruding portion of the electrode, and the brazing material quickly spreads between the protruding portions, so that a meniscus having a good shape is quickly formed from the side surface of the large diameter portion to the periphery of the protruding portion of the electrode. Is generated. Therefore, it is possible to realize strong joining of the lead pin together with the brazing material accumulated in the gap between the large diameter portion and the electrode.
[0013]
The semiconductor device according to the present invention includes a semiconductor element storage package according to the present invention, a semiconductor element mounted on the mounting portion with a lower surface joined thereto, and an outer peripheral portion of an upper surface of the base so as to cover above the semiconductor element. And a lid joined to the lid.
[0014]
With the above configuration, the semiconductor device of the present invention has high reliability using the semiconductor element housing package of the present invention.
[0015]
BEST MODE FOR CARRYING OUT THE INVENTION
The package for housing a semiconductor element of the present invention will be described in detail below. 1 and 2 show an embodiment of a semiconductor package according to the present invention. FIG. 1 is a sectional view of the semiconductor package, FIG. 2A is an enlarged sectional view of a main part of the semiconductor package, and FIG. FIG. 4 is an enlarged plan view of a main part. In FIG. 1, 1 is a base, 2 is a metallized layer, 3 is a through conductor, 3a is a lower end, 4 is a conductor layer, 5 is an electrode, 6 is a lead pin, 6a is a large diameter portion, 7 is a brazing material, and 7a is a meniscus. is there. In FIG. 2, reference numeral 8 denotes a protruding portion.
[0016]
The semiconductor package of the present invention includes a base 1 made of ceramics on which a mounting portion of a semiconductor element A formed of a metallized layer 2 is formed on an upper surface, and a through conductor 3 formed on the lower surface of the base 1 and having a substantially circular cross section. A substantially circular electrode 5 electrically connected to the metallized layer 2; and a lead pin 6 having a substantially circular large-diameter portion 6a formed at one end brazed to the electrode 5 coaxially. When the diameter of the large diameter portion 6a is R, three are arranged at substantially equal intervals such that the lower end is inscribed in the circumference of a circle having a diameter of 0.8R to R with the center of the electrode 5 as the center. In addition, the three lower ends project from the lower surface of the base 1 with substantially the same length of R / 8 to R / 4 to form projecting portions 8 on the electrodes 5 respectively.
[0017]
The base 1 of the present invention has a metallized layer 2 as a mounting portion for the semiconductor element A on the upper surface and an electrode 5 on the lower surface. The metallized layer 2 and the electrode 5 are formed by a through conductor formed inside the base 1. 3 are electrically connected to each other. The metallized layer 2 and the electrode 5 are covered with a plating layer such as a nickel (Ni) plating layer or a gold (Au) plating layer in order to prevent oxidation of the surface and improve wettability with the brazing material 7. It is good to wear it.
[0018]
The semiconductor element A is joined to, for example, the upper surface of the base 1 via solder. A lead pin 6 is joined to the electrode 5 of the base 1 via a brazing material 7. The lead pins 6 are used to join the semiconductor element A to an external electric circuit device.
[0019]
The semiconductor package having the base 1 is manufactured as follows. When the base 1 is made of an aluminum oxide (Al 2 O 3 ) sintered body (ceramic), silica (SiO 2 ), magnesia (MgO), calcia (BaO) or the like is used as a sintering aid in the Al 2 O 3 powder. The powder is added, the appropriate binder, solvent and plasticizer are added, and then the mixture is kneaded to a slurry. Thereafter, ceramic green sheets for multi-cavity are obtained by a conventionally known molding method such as a doctor blade method.
[0020]
Using this ceramic green sheet, the base 1 is manufactured by the steps shown in the following [1] to [11].
[0021]
[1] A through hole for forming the through conductor 3 from the upper surface to the lower surface is formed by a punching method.
[0022]
[2] Fill the through holes with a conductive paste containing tungsten as a main component.
[0023]
[3] A metallized layer 2 and a conductor layer to be the electrode 5 are formed by a screen printing method.
[0024]
[4] Laminate ceramic green sheets to produce a ceramic green sheet laminate.
[0025]
[5] A columnar conductor to be the protruding portion 8 is formed on the lower end surface of the conductor to be the through conductor 3 filled in the through hole by printing a conductor paste by a screen printing method. At this time, the height of the columnar conductor can be set to an arbitrary height by changing the thickness of the sealing resin attached to the plate in screen printing. Further, by pressing the green sheet at a low pressure after drying, the heights of the columnar conductors can be substantially equalized.
[0026]
When the protruding portion 8 is formed, when the lead pin 6 is joined via the brazing material 7, the lead pin 6 quickly forms a uniform meniscus 7a between the large diameter portion 6a and the metallized layer 2, In addition, the surface area can be made substantially constant, whereby a strong and highly reliable bonding structure can be realized.
[0027]
[6] This ceramic green sheet laminate is cut and separated into laminates to be individual substrates 1 and fired at a high temperature of, for example, about 1600 ° C. for about 2 hours to obtain a sintered body having each conductor layer. At this time, the base 1 is fired with the lower surface on which the protruding portions 8 are formed facing upward, so that the protruding portions 8 protruding from the base 1 on the lower surface of the base 1 are formed.
[0028]
When the diameter of the large-diameter portion 6a is R, the through conductor 3 of the present invention has a lower end at the circumference of a circle 5a having a diameter of 0.8R to R centered on the center of the electrode 5 {FIG. Are inscribed so that they are inscribed at substantially equal intervals, and the lower ends of the three protrude from the lower surface of the base 1 with substantially the same length of R / 8 to R / 4.
[0029]
If the diameter of the circle 5a is less than 0.8R, it is difficult to form the meniscus 7a by the projection 8 and the joining strength tends to be small. If the diameter of the circle 5a exceeds R, the lead pins 6 may be joined obliquely.
[0030]
If the height (length in the vertical direction) of the protruding portion 8 is less than R / 8, the area of the meniscus 7a decreases, and the volume of the brazing material 7 between the large-diameter portion 6a and the electrode 5 decreases. However, there is a tendency that sufficient bonding strength of the lead pin 6 cannot be obtained. If the height of the protruding portion 8 exceeds R / 4, voids are easily generated in the brazing material 7, and the voids reduce the bonding strength or increase the conductor resistance. This causes transmission delay and the like.
[0031]
[7] In order to protect each conductor layer to prevent oxidation and facilitate brazing, a metal plating layer made of a Ni plating layer or an Au plating layer is applied to the surface of each conductor layer.
[0032]
[8] For example, in a brazing furnace in a non-oxidizing atmosphere, a state in which, for example, a columnar Ag wax serving as the brazing material 7 is laid sideways on the large diameter portion 6a of the lead pin 6 with an adhesive or the like is used. By melting at a temperature of ° C., a hemispherical tip portion (bump) made of Ag wax is formed on the large diameter portion 6a.
[0033]
[9] A plurality of lead pins 6 are arranged at predetermined positions on the surface of the base 1 using a carbon jig (not shown) in which a plurality of holes for inserting the lead pins 6 are formed at predetermined intervals. At this time, a jig is prepared in advance that can lead the lead pins 6 into each hole of the carbon jig while vibrating while vibrating, and each lead is inserted one by one with the main body of the lead pin 6 downward. In order to prevent oxidation and improve the wettability with the brazing material 7 and the solder, a metal plating layer such as a Ni plating layer having a thickness of 0.5 to 9 μm is preferably applied to the surface of the lead pin 6 in advance. .
[0034]
[10] The substrate 1 is placed on a carbon jig such that the electrode 5 of the substrate 1 is in contact with the large diameter portion 6a of each lead pin 6, and heated at a temperature of about 870 ° C. in a brazing furnace. A lead pin 6 is provided at a predetermined position of the base 1 via a brazing material 7.
[0035]
[11] A Ni plating layer having a thickness of 0.5 to 9 μm and an Au plating layer having a thickness of 0.5 to 5 μm are applied to the entire semiconductor package having the lead pins 6 protruded.
[0036]
Through the above steps, the base 1 is in a state in which the lead pins 6 are protruded from the lower electrode 5 via the brazing material 7, and a good shape of the brazing material 7 is formed at the joint of the lead pins 6 by the action of the protruding portion 8. Is formed, and the brazing material 7 having a sufficient volume for securing the bonding strength is held at the bonding portion. As a result, the bonding strength of the lead pin 6 is improved, and the reflection loss of the high-frequency signal transmitted via the lead pin 6 can be reduced, so that a favorable operation state of the semiconductor device can be obtained.
[0037]
Further, even if one of the three through conductors 3 formed for each of the electrodes 5 becomes defective in conduction, it is covered by the remaining through conductors, so that the conductor resistance abnormality and the disconnection defect are eliminated. The diameter of the through conductor 3 is preferably about 0.15 to 0.3 mm. If it is less than 0.15 mm, there is a difficulty in mass productivity. If it exceeds 0.3 mm, the area of the electrode 5 must be increased, and therefore, the size of the base 1 increases.
[0038]
Further, since the protrusion 8 is formed, the flow of the brazing material 7 is guided by the protrusion 8 to improve the flowability of the brazing material 7, and as a result, the surface of the meniscus 7 a is extremely smooth. Has become.
[0039]
The semiconductor element A is fixed to the mounting portion of the base 1 obtained as described above, and a cap such as a cap is joined to the outer periphery of the upper surface of the base 1, or the frame is attached to the outer periphery of the upper surface of the base 1. The semiconductor device can be obtained by joining the plate-shaped lids via the substrate. Then, the lead pins 6 are brought into contact with the electrodes of the external electric circuit board or the like on which the solder bumps are formed in advance, and are heated to a temperature at which the solder is re-melted. Thus, the lead pins 6 are joined to the electrodes of the external electric circuit board or the like via the solder, and the semiconductor device and the external electric circuit device are electrically connected.
[0040]
The semiconductor device of the present invention is bonded to the semiconductor package of the present invention, a semiconductor element A mounted on the lower surface of the mounting portion, and an outer peripheral portion of the upper surface of the base 1 so as to cover above the semiconductor element A. And a lid. The semiconductor device of the present invention can transmit a high-frequency signal to the semiconductor element A via the lead pin 6 having high bonding reliability and high bonding strength. Therefore, the semiconductor device functions as a semiconductor device that processes a large amount of information at high speed, and is suitably used for, for example, an MCM (Multi Chip Module) in addition to an LSI.
[0041]
【Example】
Embodiments of the package for housing a semiconductor element of the present invention will be described below.
[0042]
First, samples in which the diameter of a circle 5a for joining the lead pin 6 of the electrode 5 was variously set were prepared as in the following steps [1] to [5].
[0043]
[1] In a ceramic green sheet having a thickness of 1.5 mm, a length of about 20 mm and a width of about 30 mm, the position of the circle 5a with respect to the electrode 5 was set as follows. The diameter of the electrode 5 is 2 mm, the diameter R of the large diameter portion 6a of the lead pin 6 is 0.5, 0.75, 1, 1.25, 1.5 (mm). The diameter of 5a is 0.35, 0.4, 0.45, 0.5, 0.55 (mm), and the diameter of circle 5a is 0.525, 0.6, 0 when R is 0.75 mm. .675, 0.75, 0.825 (mm), and when R is 1 mm, the diameter of the circle 5a is 0.7, 0.8, 0.9, 1, 1.1 (mm), and R is When the diameter is 1.25 mm, the diameter of the circle 5a is 0.875, 1, 1.125, 1.25, 1.375 (mm), and when R is 1.5 mm, the diameter of the circle 5a is 1.05, 1.2, 1.35, 1.5, 1.65 mm.
[0044]
[2] In the ceramic green sheet, a through hole having a diameter of 0.15 mm after firing is formed at a position where the circumference is divided into three so as to be inscribed in the circumference of the circle 5 a with respect to one electrode 5. Three sets were formed as one set, and 10 sets were formed by a punching method. A conductor paste containing tungsten as a main component and having a viscosity of about 10,000 poise was press-fitted into the obtained through-hole. Two of these were produced in each case. Next, a conductor layer to be the electrode 5 was formed on the upper surface of one of the two by screen printing.
[0045]
[3] Two ceramic green sheets were laminated to obtain a laminate having a thickness of 3 mm.
[0046]
[4] A columnar conductor is formed at the lower end of the three through conductors 3 in the laminate by screen printing, and then dried at 80 ° C., and then the green sheet is pressed at a pressure of 100 kgf / cm 2 to make the surface substantially flat. Then, a conductor pattern to be the electrode 5 was formed by a screen printing method. At this time, the height of the columnar conductor was changed to obtain a laminate that became a test substrate used in the examples.
[0047]
[5] Next, after drying at 80 ° C., baking was performed at 1600 ° C. to obtain 25 test substrates. A lead pin 6 having a large-diameter portion 6a having a diameter of 1 mm and having a bump provided on the upper end surface was bonded to this test substrate in a non-oxidizing atmosphere at 870 ° C.
[0048]
Table 1 shows the results of a tensile test in which the lead pins 6 were pulled upward on the test substrate thus obtained.
[0049]
[Table 1]
Figure 2004031818
[0050]
From Table 1, it has been found that the diameter of the circle 5a with respect to the electrode 5 needs to be 0.8R to R. In the present embodiment, the inclination of the lead pin 6 is only a few degrees, but if this inclination occurs in a multi-pin product, a large amount of time and labor is required for correction. Further, it is considered that the nonuniformity of the meniscus 7a is caused by a partial difference in the surface formation time, and in this case, it appears as a difference in bonding strength.
[0051]
Next, the diameter of the circle 5a is set to 0.9R, R is set to 0.6, 0.8, 1, 1.2, 1.4 (mm). The height is set to 50, 75, 100, 125, 150, 175 (μm). When R is 0.8 mm, the height of the protrusion 8 is set to 80, 100, 150, 175, 200, 220 (μm). Is 1 mm, the height of the protrusion 8 is 100, 125, 150, 200, 250, 300 (μm), and when R is 1.2 mm, the height of the protrusion 8 is 125, 150, 200, 250. , 300, 350 (μm) and a sample in which the height of the protrusion 8 is changed when the height of the protrusion 8 is 150, 175, 250, 300, 350, 375 (μm) when R is 1.4 mm. Were fabricated on a single substrate, 10 in each case, for a total of 36 tests. A substrate was prepared, and the bonding strength of the lead pin and the state of the brazed portion were evaluated. Table 2 shows the results.
[0052]
[Table 2]
Figure 2004031818
[0053]
From Table 2, it was found that when the height of the protruding portion 8 was small, the bonding strength was deteriorated. This is considered to be due to the poor meniscus formation state and the small volume of the brazing material 7. If the height of the protrusion 8 is too high, voids may be generated inside the brazing material 7, and in this case, the bonding strength is reduced.
[0054]
It should be noted that the present invention is not limited to the above embodiments and examples, and that various changes may be made without departing from the spirit of the present invention.
[0055]
【The invention's effect】
The semiconductor device housing package according to the present invention includes a base made of ceramics on which a mounting portion of a semiconductor element formed of a metallized layer is formed on an upper surface, and a metallized layer formed on a lower surface of the base via a through conductor having a substantially circular cross section. A substantially circular electrode electrically connected to the electrode, a substantially circular large-diameter portion formed at one end is provided with a lead pin coaxially brazed to the electrode, and the through conductor has a diameter of the large-diameter portion. Assuming that R is the center of the electrode, three are arranged at substantially equal intervals so that the lower ends are inscribed in the circumference of a circle having a diameter of 0.8R to R, and the lower ends of the three are set. Project from the lower surface of the base with substantially the same length of R / 8 to R / 4 to form projecting portions on the respective electrodes, so that when the semiconductor element housing package is heated in the brazing furnace, Provided on the large diameter part The brazing material is melted, and at the surface of the electrode formed at the lower end of the through conductor, the large diameter portion comes into contact with the protruding portion formed to protrude downward, and the brazing is completed. The brazing material also flows on the surface of the protruding portion of the electrode, and the brazing material quickly spreads between the protruding portions, so that a meniscus of a good shape is quickly generated from the side surface of the large diameter portion to the periphery of the protruding portion of the electrode. You. Therefore, it is possible to realize the strong joining of the lead pins together with the brazing material accumulated in the gap between the large diameter portion and the electrode.
[0056]
The semiconductor device of the present invention includes the semiconductor element housing package of the present invention, a semiconductor element mounted with the lower surface bonded to the mounting portion, and a semiconductor device bonded to an outer peripheral portion of an upper surface of the base so as to cover above the semiconductor element. With such a lid, the reliability using the package for housing a semiconductor element of the present invention is high.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing an example of an embodiment of a package for housing a semiconductor element of the present invention.
FIG. 2A is an enlarged cross-sectional view of a main part showing the periphery of a lead pin in the package for housing a semiconductor element of FIG. 1, and FIG. 2B is an enlarged plan view of a main part showing the periphery of the lead pin of FIG.
FIG. 3 is a cross-sectional view of a conventional semiconductor element storage package.
[Explanation of symbols]
1: Base 2: Metallized layer 3: Through conductor 3a: Lower end 5: Electrode 5a: Circle 6: Lead pin 6a: Large diameter portion 7: Brazing material 8: Projecting portion A: Semiconductor element

Claims (2)

上面にメタライズ層から成る半導体素子の搭載部が形成されたセラミックスから成る基体と、該基体の下面に形成され、断面が略円形の貫通導体を介して前記メタライズ層に電気的に接続された略円形の電極と、一端に形成された略円形の大径部が前記電極に同軸状にロウ付けされたリードピンとを具備しており、前記貫通導体は、前記大径部の直径をRとしたとき、前記電極の中心を中心とし0.8R〜Rの直径を有する円の円周に下端が内接するようにして3本が略等間隔に配置されているとともに、それら3本の下端が前記基体の下面からR/8〜R/4の略同じ長さで突出してそれぞれ前記電極に突出部を形成していることを特徴とする半導体素子収納用パッケージ。A base made of ceramics, on the upper surface of which a mounting portion of a semiconductor element formed of a metallized layer is formed, and a substantially formed on the lower surface of the base and electrically connected to the metallized layer via a through conductor having a substantially circular cross section. A circular electrode, a substantially circular large-diameter portion formed at one end is provided with a lead pin coaxially brazed to the electrode, and the through conductor has a diameter of the large-diameter portion R. At this time, the three electrodes are arranged at substantially equal intervals so that the lower ends are inscribed in the circumference of a circle having a diameter of 0.8R to R around the center of the electrode, and the lower ends of the three electrodes are A package for housing a semiconductor element, wherein a projecting portion is formed on each of the electrodes by projecting from the lower surface of the base at substantially the same length of R / 8 to R / 4. 請求項1記載の半導体素子収納用パッケージと、前記搭載部に下面が接合されて搭載された半導体素子と、該半導体素子の上方を覆うように前記基体の上面の外周部に接合された蓋体とを具備したことを特徴とする半導体装置。2. The package for semiconductor device storage according to claim 1, a semiconductor device mounted on the mounting portion with a lower surface bonded thereto, and a lid bonded to an outer peripheral portion of an upper surface of the base so as to cover above the semiconductor device. And a semiconductor device comprising:
JP2002188459A 2002-06-27 2002-06-27 Package for storing semiconductor element and semiconductor device Pending JP2004031818A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113725085A (en) * 2021-08-31 2021-11-30 深圳技术大学 Assembly process method of packaging part and packaging part

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113725085A (en) * 2021-08-31 2021-11-30 深圳技术大学 Assembly process method of packaging part and packaging part
CN113725085B (en) * 2021-08-31 2024-03-29 深圳技术大学 Assembling process method of packaging part and packaging part

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