JP2004031531A - High-density wiring board and its manufacturing method - Google Patents

High-density wiring board and its manufacturing method Download PDF

Info

Publication number
JP2004031531A
JP2004031531A JP2002183868A JP2002183868A JP2004031531A JP 2004031531 A JP2004031531 A JP 2004031531A JP 2002183868 A JP2002183868 A JP 2002183868A JP 2002183868 A JP2002183868 A JP 2002183868A JP 2004031531 A JP2004031531 A JP 2004031531A
Authority
JP
Japan
Prior art keywords
wiring
output timing
diameter
wiring board
signal output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2002183868A
Other languages
Japanese (ja)
Other versions
JP3912199B2 (en
Inventor
Kenshiro Ikeda
池田 剣志郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toppan Inc
Original Assignee
Toppan Printing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toppan Printing Co Ltd filed Critical Toppan Printing Co Ltd
Priority to JP2002183868A priority Critical patent/JP3912199B2/en
Publication of JP2004031531A publication Critical patent/JP2004031531A/en
Application granted granted Critical
Publication of JP3912199B2 publication Critical patent/JP3912199B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Landscapes

  • Structure Of Printed Boards (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a high-density wiring board in which the elongation of a wiring length or the shape change of a wiring pattern is reduced and a skew is decreased by other methods in the high-density wiring board in which density is increased, and to provide its manufacturing method. <P>SOLUTION: The output timing of wiring as the latest output timing in a plurality of wiring requiring the matching of output timings is used as a reference time. Output timing at the output ends of a plurality of the wiring are aligned with the reference time, by enlarging the land diameters of vias in the paths of a plurality of other wiring, or reducing the via diameters of the vias, or increasing pad diameters at input ends and output ends in response to the reference time and lag times with the output timings of a plurality of other wiring in the wiring installed to the high-density wiring board. <P>COPYRIGHT: (C)2004,JPO

Description

【0001】
【発明の属する技術分野】
本発明は、情報機器内の高周波回路用の配線板に係り、特に、スキューの少ない高密度配線を備えた高周波回路用の高密度配線板及びその製造方法に関する。
【0002】
【従来の技術】
従来の技術では、高周波回路用の高密度配線板において、スキューを低減する方法は最短経路となる配線の線路長を確保するため蛇行させ延長して調整することが行われている。
【0003】
前記線路長を確保するため配線の蛇行させ延長するバス配線においては、配線の引き回しのため余分な配線領域が必要となり、又、必要な電気特性のクロストークを抑えるため、配線間のスペースを広くとらなければならず、引き回しのための配線領域に余裕がない場合が発生する。
【0004】
そのため、配線間のスペースを広くとれず、引き回しのための配線領域に余裕がない場合、配線板のサイズを拡大するか、又は、層数を増やして前記線路長を確保する必要がある。
【0005】
上述のように、線路長を延長するバス配線は、配線板のサイズを拡大や、層数を増加する方法で製造するため、前記製造コストアップとなり敬遠されている。
【0006】
前記バス配線について具体的に記述する。最初は、配線領域を拡張する方法である。引き回しの余裕がない場合は、基板サイズ(基板寸法)を大きくして回路グループ間に未配線領域を予め設け、該領域に線路長を確保するため延長配線して調整する。
【0007】
次は、層数を増加する方法である。基板サイズ(基板寸法)を拡大出来ない場合は、他の層内にスルーホールのビアを介して回路を形成し、前記他の層内領域に線路長を確保するため延長配線して等長配線に調整する。
【0008】
前記等長配線は回路に冗長パターンを付与するため、回路的に不要パターンや、ビアを形成する必要があり製造工程上にも不都合が発生する場合がある。
【0009】
近年の技術では、搭載するチップやパッケージの小型化、アレイの多ピン(端子)化により、各端子まで等長配線によるスキューを低減する方法は幾何的(パターンの形状)にも困難になっている。そのため、スキューを低減するために線路長を延長するバス配線方法では全て解決することが困難になってきた。
【0010】
当然電気特性においても同じ悩みがある。高密度化がすすむ配線板において、等長配線によるスキューの低減を実現することが困難になりつつある。
【0011】
上述のように、最短経路となる配線は線路長を確保するため蛇行させなければならない。又、クロストークを抑えるため配線間のスペースを広くとらなければならず、配線領域に引き回しの余裕がない。また、搭載するチップやパッケージの小型化、アレイ多ピン(端子)化により、各端子まで等長配線は電気特性以前に配線パターン的にも困難になっている。
【0012】
【発明が解決しようとする課題】
本発明の課題は、高密度化がすすむ高密度配線板において、配線長の延長、又は配線パターンの形状変更を減らし、他の方法でスキューを低減する高密度配線板及びその製造方法を提供することである。
【0013】
【課題を解決するための手段】
本発明の請求項1に係る発明は、高密度配線板に設けられた配線であって、信号出力タイミングの整合を必要とする複数の配線のうち、最も遅い出力タイミングとなる配線からの信号出力タイミングを基準時間とし、前記基準時間と、他の複数の配線からの信号出力タイミング時間とのずれ時間に応じて、前記他の複数の配線の経路途中のビアのランド径を大きく、又はビアのビア径を小さくしたことにより、前記複数の配線の出力端での信号出力タイミング時間を前記基準時間に揃えたことを特徴とした高密度配線板である。
【0014】
本発明の請求項2に係る発明は、高密度配線板に設けられた配線であって、信号出力タイミングの整合を必要とする複数の配線のうち、最も遅い出力タイミングとなる配線からの信号出力タイミングを基準時間とし、前記基準時間と、他の複数の配線からの信号出力タイミング時間とのずれ時間に応じて、前記他の複数の配線の入力端、及び出力端のパッド径を大きくしたことにより、前記複数の配線の出力端での信号出力タイミング時間を前記基準時間に揃えたことを特徴とした請求項1記載の高密度配線板である。
【0015】
本発明の請求項3に係る発明は、高密度配線板に設けられた配線であって、信号出力タイミングの整合を必要とする複数の配線のうち、最も遅い出力タイミングとなる配線からの信号出力タイミングを基準時間とし、前記基準時間と、他の複数の配線からの信号出力タイミング時間とのずれ時間に応じて、前記他の複数の配線の経路途中のビアのランド径を大きく、又はビアのビア径を小さく、若しくは入力端、及び出力端のパッド径を大きくすることにより、前記複数の配線の出力端での信号出力タイミング時間を前記基準時間に揃えることを特徴とする請求項1、又は請求項2記載の高密度配線板の製造方法である。
【0016】
【作用】
高密度配線板においてスキューを低減する方法は、従来の技術は、最短経路となる配線の線路長を確保するため蛇行させ延長して調整することが行われている。本発明は、配線の経路途中のビアのランド径を大きく、又はビアのビア径を小さく、若しくは入力端、及び出力端のパッド径を大きくすることにより、前記複数の配線の出力端での信号出力タイミング時間を前記基準時間に揃える方法である。
【0017】
【発明の実施の形態】
以下に、本発明の配線の特徴について図面を用いて説明する。
【0018】
一般に配線中にビアが存在する場合、単純な伝送路と比較して、層厚の分だけ配線長が長くなるため遅延が生じる。図4に示すように、ビアのビア径と、ランド径との遅延時間の関係をシュミレーションした結果である。ランド径が大きく、ビア径が小さいほど、遅延が長くなる。図4は、試料1、2,3の関連式である。
【0019】
従って、最長経路以外の配線は、最長経路の出力タイミングに合わせて経路途中の各ビアのランド径やビア径の大小を選ぶことにより、スキューを減少することができる。
【0020】
図5に示すように、入力端、出力端のパット径と、遅延時間との関係をシュミレーションした結果である。パット径が大きいほど遅延が長くなる。図5は、関連グラフである。
【0021】
図5に示すように、パッド径が大きいほど遅延が長くなるため、径を選ぶことにより、スキューを減少することができる。
【0022】
図1は、本発明に係る高周波回路用の高密度配線板の一実施例を示す平面図である。
【0023】
図1は、配線A(12)と、配線B(13)との間の信号出力タイミングを説明する図である。配線の線路長は配線Aの方が長い線路長で形成されている。配線A(12)と、配線B(13)との間の信号出力タイミングは配線Aの方が遅延して出力される。本発明では、信号出力タイミングの速い配線B(13)の経路途中の各小型のビア20Aのランド径21Aやビア径22A、及びパッド径31Aを、各々、大型のビア20Bのランド径21B、小型のビア径22B、及び大型のパッド径31Bに変更して、信号出力タイミングを遅らせることにより、配線A(12)の信号出力タイミングに合わせる方法である。その結果によりスキューを減少することができる。ここで、前記小型のビア20Aとは、小型のランド径21Aと、大型のビア径22Aから構成した構造のビアであり、前記大型のビア20Bは、大型のランド径21Bと、小型のビア径22Bから構成した構造のビアを示している。
【0024】
次に、図2は、本発明に係る高周波回路用の高密度配線板の一実施例を示す側断面図である。ビア20は、図1に示すように、円形ドーナツ形状の導体層で形成され、中心近傍の孔の内壁には導体層を形成した貫通孔(以下ビア20と記す)が具備された構造である。該ビア20は、他の層の導体層と電気的に接続する役割を備えている。ビアのランド21はビア20の外周径領域内の導体層をしめす。ビアのビア22は、内径領域を示している。図2に示すように、上層の信号線10の延長線上に、大型のビアのランド21がある。該ビアのランド21と、下層の信号線11は小型のビアのビア22を介して電気的に接続されている。すなわち、上層の信号線10は、大型のビア20を介して、例えば、大型のビアのランド21、小型のビアのビア22を通電して、下層の信号線11迄電気回路を形成する。
【0025】
図3は、本発明に係る高周波回路用の高密度配線板の一実施例を示す側断面図である。入力端、及び出力端のパッド30は外部回路と接続するためのバンプを配置形成する端子であり、該パッド30は導体層で形成されている。前記バンプ配置形成する領域の外周形領域が大型のパッド径31Bである。下層の信号線11とバンプ40はパッド30を介して電気的に接続されている。すなわち、下層の信号線11は、パッド30を介してバンプ40迄電気回路を形成する。
【0026】
【実施例】
次に、本発明の、以下に具体的な実施例に従って説明する。
【0027】
<実施例1>
高周波回路用の高密度配線板からなるテスト配線板(配線板1と記す)に配線の線路長の異なる配線を2配線形成いた。前記2系統の配線は線路長の長い配線を配線A(12)とした。同様に、残の配線を配線B(13)とした。前記配線板1の配線A(12)と、配線B(13)の経路途中に小型のビア20Aの形状をランド径21Aを50μm、ビア径22Aを30μmの形状で形成した。該小型のビア20Aを10個と、BGAパッドのパッド31の形状を小型のパッド径31Aを500μmで形成した。(図面表示省)次に、配線を有する配線A(12)と、配線B(13)の各々信号出力タイミング時間を測定した。その結果、配線A(12)は配線B(13)に対し1.5psの遅延差があった。そこで、配線B(13)の経路途中の小型のビア20Aから大型のビア20Bに変更した。すなわち、大型のランド径21Bを62μm、小型のビア径22Bを26μmに変更し、再度測定の結果、約0.4psの遅延差が短縮し、配線A(12)は配線B(13)に対し1.1psの遅延差があった。(図1参照)
【0028】
さらに、配線B(13)の経路途中のパッド31を変更した。すなわち、大型のパッド径31bを560μmに変更した。経路途中を変更した前記配線Bを再測定した。その結果、更に1.1psの遅延差が短縮し、配線Aと配線Bは略信号出力タイミングが合致した。以上の変更より、配線パターンを変更することなく、遅延差(スキュー)をなくすことができた。
【0029】
【発明の効果】
上記の通り、本発明に係る高周波回路用の高密度配線板によれば、前記配線の経路途中の個々のビアのランド径を大きく、又はビアのビア径を小さく、若しくは入力端、及び出力端のパッド径を選択することにより、低スキュー化が実現できる。
【図面の簡単な説明】
【図1】本発明に係る高周波回路用配線板の実施例を示す平面図。
【図2】本発明に係る高周波回路用配線板の実施例を示す断面図。
【図3】本発明に係る高周波回路用配線板の実施例を示す断面図。
【図4】ビア径及びランド径と遅延量の関係を示すシミュレーション結果である。
【図5】パッド径と遅延量の関係を示すシミュレーション結果である。
【符号の説明】
1…配線板
10…信号線
11…他層に形成した信号線
12…配線A
13…配線B
20…ビア
20A…(小型の)ビア
20B…(大型の)ビア
21…ビアのランド
21A…(小型の)ランド径
21B…(大型の)ランド径
22…ビアのビア
22A…(大型の)ビア径
22B…(小型の)ビア径
30…入出端のパッド
31…パッド
31A…(小型の)パッド径
31B…(大型の)パッド径
40…バンプ
[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a wiring board for a high-frequency circuit in an information device, and more particularly to a high-density wiring board for a high-frequency circuit provided with a high-density wiring with less skew and a method for manufacturing the same.
[0002]
[Prior art]
In the prior art, in a high-density wiring board for a high-frequency circuit, a method of reducing skew is to adjust the length of the wiring in a meandering manner in order to secure the line length of the wiring that is the shortest path.
[0003]
In the case of a bus wiring which extends in a meandering manner in order to secure the line length, an extra wiring area is required for routing the wiring, and a space between the wirings is increased in order to suppress crosstalk of necessary electric characteristics. This has to be taken, and there is a case where there is not enough room in the wiring area for routing.
[0004]
Therefore, if the space between the wirings cannot be widened and the wiring area for the wiring has no margin, it is necessary to increase the size of the wiring board or increase the number of layers to secure the line length.
[0005]
As described above, the bus wiring for extending the line length is manufactured by a method of increasing the size of the wiring board or increasing the number of layers.
[0006]
The bus wiring will be specifically described. The first is a method of expanding the wiring area. If there is no room for routing, the board size (board size) is increased to provide an unwired area between circuit groups in advance, and the wiring is extended and adjusted to secure the line length in this area.
[0007]
Next is a method of increasing the number of layers. If the substrate size (substrate size) cannot be increased, a circuit is formed in another layer via a through-hole via, and extended wiring is performed in the other layer area to secure a line length, and isometric wiring. Adjust to
[0008]
Since the above-mentioned equal-length wiring provides a redundant pattern to a circuit, it is necessary to form an unnecessary pattern or a via in a circuit, which may cause a problem in a manufacturing process.
[0009]
In recent technology, the miniaturization of chips and packages to be mounted and the increase in the number of pins (terminals) in arrays have made geometric (pattern shape) difficult to reduce the skew due to equal-length wiring up to each terminal. I have. For this reason, it has become difficult to solve all the problems with the bus wiring method in which the line length is extended to reduce the skew.
[0010]
Naturally, there is the same problem in electrical characteristics. It is becoming difficult to reduce the skew by using equal-length wiring in a wiring board that is increasing in density.
[0011]
As described above, the wiring that is the shortest path must meander to secure the line length. In addition, a space between wirings must be widened in order to suppress crosstalk, and there is no room for routing in the wiring area. In addition, due to the miniaturization of chips and packages to be mounted and the increase in the number of pins (terminals) in an array, it has become difficult to make equal-length wiring to each terminal in terms of wiring patterns before electrical characteristics.
[0012]
[Problems to be solved by the invention]
An object of the present invention is to provide a high-density wiring board and a method for manufacturing the high-density wiring board, in which a wiring length is increased or a change in the shape of a wiring pattern is reduced, and a skew is reduced by another method. That is.
[0013]
[Means for Solving the Problems]
The invention according to claim 1 of the present invention is a wiring provided on a high-density wiring board, wherein a signal output from a wiring having the latest output timing among a plurality of wirings requiring signal output timing matching is provided. The timing is set as a reference time, and the land diameter of the via in the middle of the route of the other plurality of wirings is increased, or the size of the via is changed according to the time difference between the reference time and the signal output timing from the other plurality of wirings. A high-density wiring board characterized in that a signal output timing time at an output end of the plurality of wirings is made equal to the reference time by reducing a via diameter.
[0014]
According to a second aspect of the present invention, there is provided a wiring provided on a high-density wiring board, wherein a signal output from a wiring having the latest output timing among a plurality of wirings requiring signal output timing matching is provided. The timing is set as a reference time, and the pad diameter of the input end and the output end of the other plurality of wirings is increased according to a time difference between the reference time and the signal output timing time from the other plurality of wirings. 2. The high-density wiring board according to claim 1, wherein signal output timing times at output ends of the plurality of wirings are aligned with the reference time.
[0015]
According to a third aspect of the present invention, there is provided a wiring provided on a high-density wiring board, wherein a signal output from a wiring having the latest output timing among a plurality of wirings requiring signal output timing matching is provided. The timing is set as a reference time, and the land diameter of the via in the middle of the route of the other plurality of wirings is increased, or the size of the via is changed according to the time difference between the reference time and the signal output timing from the other plurality of wirings. The signal output timing at the output ends of the plurality of wirings is made equal to the reference time by reducing the via diameter or increasing the pad diameters of the input end and the output end. A method for manufacturing a high-density wiring board according to claim 2.
[0016]
[Action]
As a method of reducing skew in a high-density wiring board, in the related art, adjustment is performed by meandering and extending the wiring in order to secure the line length of the wiring that is the shortest path. According to the present invention, the signal at the output end of the plurality of wirings is increased by increasing the land diameter of the via in the middle of the wiring path, reducing the via diameter of the via, or increasing the pad diameter of the input end and the output end. This is a method of adjusting the output timing time to the reference time.
[0017]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, features of the wiring of the present invention will be described with reference to the drawings.
[0018]
In general, when a via exists in a wiring, a delay occurs because the wiring length is increased by the layer thickness as compared with a simple transmission line. As shown in FIG. 4, this is a result of simulating the relationship between the via diameter of the via and the delay time between the land diameter. The longer the land diameter and the smaller the via diameter, the longer the delay. FIG. 4 is a relational expression of samples 1, 2, and 3.
[0019]
Therefore, for wiring other than the longest route, the skew can be reduced by selecting the land diameter and the via diameter of each via in the middle of the route in accordance with the output timing of the longest route.
[0020]
As shown in FIG. 5, this is a result of simulating the relationship between the pad diameter at the input end and the output end and the delay time. The larger the pad diameter, the longer the delay. FIG. 5 is a related graph.
[0021]
As shown in FIG. 5, as the pad diameter is larger, the delay is longer. Therefore, by selecting the diameter, the skew can be reduced.
[0022]
FIG. 1 is a plan view showing one embodiment of a high-density wiring board for a high-frequency circuit according to the present invention.
[0023]
FIG. 1 is a diagram for explaining signal output timing between the wiring A (12) and the wiring B (13). The wiring A has a longer line length than the wiring A. The signal output timing between the wiring A (12) and the wiring B (13) is delayed and output from the wiring A. In the present invention, the land diameter 21A and the via diameter 22A of each small via 20A and the pad diameter 31A in the middle of the route of the wiring B (13) having a fast signal output timing are respectively changed to the land diameter 21B of the large via 20B and the small diameter. In this method, the signal output timing is delayed by changing the via diameter 22B and the large pad diameter 31B to match the signal output timing of the wiring A (12). As a result, skew can be reduced. Here, the small via 20A is a via having a structure including a small land diameter 21A and a large via diameter 22A, and the large via 20B is a large land diameter 21B and a small via diameter. A via having a structure composed of 22B is shown.
[0024]
Next, FIG. 2 is a side sectional view showing one embodiment of a high-density wiring board for a high-frequency circuit according to the present invention. As shown in FIG. 1, the via 20 is formed of a circular donut-shaped conductor layer, and has a structure in which a through hole (hereinafter, referred to as a via 20) in which a conductor layer is formed is provided on the inner wall of the hole near the center. . The via 20 has a role of electrically connecting to another conductor layer. The via land 21 indicates a conductor layer in the outer diameter region of the via 20. The via 22 of the via indicates an inner diameter region. As shown in FIG. 2, there is a land 21 of a large via on an extension of the signal line 10 in the upper layer. The land 21 of the via and the lower signal line 11 are electrically connected via a via 22 of a small via. That is, the upper-layer signal line 10 conducts electricity through, for example, a land 21 of a large via and a via 22 of a small via via a large-sized via 20 to form an electric circuit up to the signal line 11 in a lower layer.
[0025]
FIG. 3 is a side sectional view showing one embodiment of a high-density wiring board for a high-frequency circuit according to the present invention. The pads 30 at the input and output terminals are terminals for arranging and forming bumps for connection to an external circuit, and the pads 30 are formed of a conductive layer. The outer peripheral area of the area where the bumps are formed is a large pad diameter 31B. The lower signal line 11 and the bump 40 are electrically connected via the pad 30. That is, the lower signal line 11 forms an electric circuit up to the bump 40 via the pad 30.
[0026]
【Example】
Next, the present invention will be described below in accordance with specific examples.
[0027]
<Example 1>
Two test wirings having different line lengths were formed on a test wiring board (referred to as wiring board 1) formed of a high-density wiring board for a high-frequency circuit. The wiring of the two systems is a wiring having a long line length, which is referred to as a wiring A (12). Similarly, the remaining wiring was used as wiring B (13). A small via 20A was formed in the middle of the route of the wiring A (12) and the wiring B (13) of the wiring board 1 with a land diameter 21A of 50 μm and a via diameter 22A of 30 μm. Ten small vias 20A and the pad 31 of the BGA pad were formed with a small pad diameter 31A of 500 μm. Next, the signal output timing time of each of the wiring A (12) having the wiring and the wiring B (13) was measured. As a result, the wiring A (12) had a delay difference of 1.5 ps with respect to the wiring B (13). Therefore, the small via 20A in the middle of the route of the wiring B (13) was changed to a large via 20B. That is, the large land diameter 21B was changed to 62 μm, and the small via diameter 22B was changed to 26 μm. As a result of the measurement again, the delay difference of about 0.4 ps was shortened, and the wiring A (12) was compared with the wiring B (13). There was a 1.1 ps delay difference. (See Fig. 1)
[0028]
Further, the pad 31 in the middle of the route of the wiring B (13) was changed. That is, the large pad diameter 31b was changed to 560 μm. The wiring B whose path was changed midway was measured again. As a result, the delay difference of 1.1 ps was further reduced, and the signal output timings of the wiring A and the wiring B substantially matched. With the above change, the delay difference (skew) could be eliminated without changing the wiring pattern.
[0029]
【The invention's effect】
As described above, according to the high-density wiring board for a high-frequency circuit according to the present invention, the land diameter of each via in the middle of the wiring path is increased, or the via diameter of the via is reduced, or the input end and the output end are reduced. The skew can be reduced by selecting the pad diameter of.
[Brief description of the drawings]
FIG. 1 is a plan view showing an embodiment of a wiring board for a high-frequency circuit according to the present invention.
FIG. 2 is a sectional view showing an embodiment of the wiring board for a high-frequency circuit according to the present invention.
FIG. 3 is a sectional view showing an embodiment of the wiring board for a high-frequency circuit according to the present invention.
FIG. 4 is a simulation result showing a relationship between a via diameter, a land diameter, and a delay amount.
FIG. 5 is a simulation result showing a relationship between a pad diameter and a delay amount.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Wiring board 10 ... Signal line 11 ... Signal line 12 formed in another layer ... Wiring A
13. Wiring B
20 via 20A ... (small) via 20B ... (large) via 21 ... via land 21A ... (small) land diameter 21B ... (large) land diameter 22 ... via via 22A ... (large) via Diameter 22B ... (small) via diameter 30 ... In / out end pad 31 ... pad 31A ... (small) pad diameter 31B ... (large) pad diameter 40 ... bump

Claims (3)

高密度配線板に設けられた配線であって、信号出力タイミングの整合を必要とする複数の配線のうち、最も遅い出力タイミングとなる配線からの信号出力タイミングを基準時間とし、前記基準時間と、他の複数の配線からの信号出力タイミング時間とのずれ時間に応じて、前記他の複数の配線の経路途中のビアのランド径を大きく、又はビアのビア径を小さくしたことにより、前記複数の配線の出力端での信号出力タイミング時間を前記基準時間に揃えたことを特徴とした高密度配線板。The wiring provided on the high-density wiring board, among a plurality of wirings that need to match the signal output timing, the signal output timing from the wiring that is the slowest output timing as the reference time, the reference time, By increasing the land diameter of the via in the middle of the route of the other plurality of wirings or reducing the via diameter of the via in accordance with the time lag from the signal output timing time from the other plurality of wirings, A high-density wiring board, wherein a signal output timing time at an output end of a wiring is set to the reference time. 高密度配線板に設けられた配線であって、信号出力タイミングの整合を必要とする複数の配線のうち、最も遅い出力タイミングとなる配線からの信号出力タイミングを基準時間とし、前記基準時間と、他の複数の配線からの信号出力タイミング時間とのずれ時間に応じて、前記他の複数の配線の入力端、及び出力端のパッド径を大きくしたことにより、前記複数の配線の出力端での信号出力タイミング時間を前記基準時間に揃えたことを特徴とした請求項1記載の高密度配線板。The wiring provided on the high-density wiring board, among a plurality of wirings that need to match the signal output timing, the signal output timing from the wiring that is the slowest output timing as the reference time, the reference time, By increasing the pad diameters of the input ends and the output ends of the other plurality of wirings according to the time lag from the signal output timing time from the other plurality of wirings, 2. The high-density wiring board according to claim 1, wherein a signal output timing time is set to the reference time. 高密度配線板に設けられた配線であって、信号出力タイミングの整合を必要とする複数の配線のうち、最も遅い出力タイミングとなる配線からの信号出力タイミングを基準時間とし、前記基準時間と、他の複数の配線からの信号出力タイミング時間とのずれ時間に応じて、前記他の複数の配線の経路途中のビアのランド径を大きく、又はビアのビア径を小さく、若しくは入力端、及び出力端のパッド径を大きくすることにより、前記複数の配線の出力端での信号出力タイミング時間を前記基準時間に揃えることを特徴とする請求項1、又は請求項2記載の高密度配線板の製造方法。The wiring provided on the high-density wiring board, among a plurality of wirings that need to match the signal output timing, the signal output timing from the wiring that is the slowest output timing as the reference time, the reference time, The land diameter of the via in the middle of the paths of the other wirings is increased, or the via diameter of the via is reduced, or the input end, and the output, in accordance with the time lag from the signal output timing time from the other wirings. 3. The high-density wiring board according to claim 1, wherein a signal output timing time at an output end of the plurality of wirings is made equal to the reference time by increasing an end pad diameter. Method.
JP2002183868A 2002-06-25 2002-06-25 High density wiring board and manufacturing method thereof Expired - Fee Related JP3912199B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2002183868A JP3912199B2 (en) 2002-06-25 2002-06-25 High density wiring board and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002183868A JP3912199B2 (en) 2002-06-25 2002-06-25 High density wiring board and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JP2004031531A true JP2004031531A (en) 2004-01-29
JP3912199B2 JP3912199B2 (en) 2007-05-09

Family

ID=31179901

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002183868A Expired - Fee Related JP3912199B2 (en) 2002-06-25 2002-06-25 High density wiring board and manufacturing method thereof

Country Status (1)

Country Link
JP (1) JP3912199B2 (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007149805A (en) * 2005-11-25 2007-06-14 Funai Electric Co Ltd Printed wiring board
JP2013251303A (en) * 2012-05-30 2013-12-12 Canon Inc Semiconductor package and lamination type semiconductor package
JP2014110269A (en) * 2012-11-30 2014-06-12 Fujitsu Ltd Wiring board and method of designing the same
JP2014143231A (en) * 2013-01-22 2014-08-07 Fujitsu Ltd Wiring board and design method thereof
US9265147B2 (en) 2012-11-14 2016-02-16 Fujikura Ltd. Multi-layer wiring board
US9864826B2 (en) 2014-11-03 2018-01-09 Toshiba Memory Corporation Multilayer printed board and layout method for multilayer printed board

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007149805A (en) * 2005-11-25 2007-06-14 Funai Electric Co Ltd Printed wiring board
JP2013251303A (en) * 2012-05-30 2013-12-12 Canon Inc Semiconductor package and lamination type semiconductor package
US9265147B2 (en) 2012-11-14 2016-02-16 Fujikura Ltd. Multi-layer wiring board
JP2014110269A (en) * 2012-11-30 2014-06-12 Fujitsu Ltd Wiring board and method of designing the same
JP2014143231A (en) * 2013-01-22 2014-08-07 Fujitsu Ltd Wiring board and design method thereof
US9179539B2 (en) 2013-01-22 2015-11-03 Fujitsu Limited Wiring board and design method for wiring board
US9864826B2 (en) 2014-11-03 2018-01-09 Toshiba Memory Corporation Multilayer printed board and layout method for multilayer printed board

Also Published As

Publication number Publication date
JP3912199B2 (en) 2007-05-09

Similar Documents

Publication Publication Date Title
US8319351B2 (en) Planar multi semiconductor chip package
US7705423B2 (en) Device having an array of embedded capacitors for power delivery and decoupling of high speed input/output circuitry of an integrated circuit
JP2009239318A (en) Optimized circuit design layout for high performance ball grid array packages
US6750403B2 (en) Reconfigurable multilayer printed circuit board
JP5172341B2 (en) Substrate assembly, multilayer circuit board assembly, ball grid array package, electronic assembly, method of minimizing parasitic capacitance in substrate assembly, and method of manufacturing substrate assembly
JP7394495B2 (en) Wiring design methods, wiring structures, and flip chips
US7466021B2 (en) Memory packages having stair step interconnection layers
JP2004031531A (en) High-density wiring board and its manufacturing method
US20140312488A1 (en) Method of manufacturing wiring board unit, method of manufacturing insertion base, wiring board unit, and insertion base
JP2006128687A (en) Substrate layer used together with semiconductor package and its forming method
CN114093810A (en) Chip and design method thereof
US6459049B1 (en) High density signal routing
TW202147929A (en) Electronic assembly
US20100320602A1 (en) High-Speed Memory Package
CN216902914U (en) Silicon-based substrate and chip
CN114222422B (en) Method and system for switching bus wiring
JP4342508B2 (en) Semiconductor device
US20080157385A1 (en) IC package with integral vertical passive delay cells
JPH0464279A (en) Multilayer thin film wiring board
JP4123572B2 (en) Semiconductor device
JPWO2009153912A1 (en) Semiconductor device and manufacturing method of semiconductor device
JP2010021495A (en) Wiring circuit board and its manufacturing method
JP2004022907A (en) Semiconductor device and its manufacturing method
CN117119678A (en) Bonding pad suitable for ball grid array chip and ball grid array chip
TW202145852A (en) Substrate structure with increased routing area of core layer and the manufacturing method thereof for providing additional circuit layout in the core layer to improve the space utilization and the flexibility of circuit layout

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20050324

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20050930

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20061010

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20061207

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20070109

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20070122

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100209

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110209

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120209

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130209

Year of fee payment: 6

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140209

Year of fee payment: 7

LAPS Cancellation because of no payment of annual fees