JP2004031407A - Semiconductor integrated circuit and its design method and design device - Google Patents

Semiconductor integrated circuit and its design method and design device Download PDF

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JP2004031407A
JP2004031407A JP2002181347A JP2002181347A JP2004031407A JP 2004031407 A JP2004031407 A JP 2004031407A JP 2002181347 A JP2002181347 A JP 2002181347A JP 2002181347 A JP2002181347 A JP 2002181347A JP 2004031407 A JP2004031407 A JP 2004031407A
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circuit
sub
differential
input terminal
output terminal
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Hiroshi Kodama
兒玉　浩志
Masayuki Mizuno
水野　正之
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NEC Corp
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NEC Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit capable of canceling the asymmetry of characteristics of a differential pair in the design of a differential circuit and compensating differential characteristics, and to provide a method for designing the circuit. <P>SOLUTION: In the design and layout of a differential circuit having a pair of differential input terminals and a pair of differential output terminals, the differential circuit is divided into two sub-semiconductor circuits 2. Each of the circuits 2 has a pair of differential input terminals respectively having a half of the input capacitor of one of the input terminals making the differential input terminal pair of the differential circuit, and a pair of differential output terminals respectively having a half of the driving capacity of one of the output terminals making the differential output terminal pair of the differential circuit and has a capacity equal to that of the differential circuit. The differential input terminals and the differential output terminals of respective sub-semiconductor circuits are mutually connected, mask layout is performed so that the mask layouts of the sub-semiconductor circuits and wiring have mirror inversion relation. In order to cancel the unbalance of characteristics of the differential pairs, the differential terminal pairs are connected staggeredly. <P>COPYRIGHT: (C)2004,JPO

Description

【０００１】
【本発明の属する技術分野】
本発明は、半導体集積回路に関し、特に、差動動作の半導体回路の差動特性のアンバランスを抑制する半導体集積回路及び半導体集積回路の設計方法と設計自動化装置に関する。
【０００２】
【従来の技術】
例えば平衡伝送路を差動で伝送される信号を差動入力端子対から差動で入力し差動出力端子対から差動で出力する差動動作の半導体回路（「差動回路」という）は、単信号（不平衡伝送路を伝送される）のみを用いるシングル（ｓｉｎｇｌｅ−ｅｎｄｅｄ）動作の半導体回路に比べ、一般に雑音耐性が良好なこと等の理由から、高い精度を必要とするアナログ回路、高速デジタル伝送回路等などに多用されている。従来より、差動回路を設計する際は、回路シミュレーションを行い、抵抗値やトランジスタサイズなどの各素子サイズを最適化し、そのサイズを基にし、対称になるように、マスクレイアウトが行われている。
【０００３】
【発明が解決しようとする課題】
しかしながら、上述の設計方法で設計及びレイアウトした場合、レイアウトする前の回路シミュレーションでは、差動回路の差動特性の良い結果が得られているが、対称にレイアウトすることが困難である場合がある。このため、差動端子対の間の特性に、アンバランスが生じ、差動回路の差動特性が劣化する、という問題がある。
【０００４】
したがって、本発明は、上記課題に鑑みて創案されたものであって、差動特性のアンバランスを抑制するために有効な構成の半導体集積回路及び設計方法と、回路情報に基づきレイアウトを行う設計自動化装置を提供することにある。
【０００５】
【問題を解決するための手段】
上記目的を達成する本発明に係る半導体集積回路は、１つの差動入力端子対をなす２つの入力端子と、１つの差動出力端子対をなす２つの出力端子とを少なくとも含み、前記差動入力端子対から入力信号を差動入力し、出力信号を前記差動出力端子対から差動出力する回路（「元の回路」という）が、同一のチップ上に集積化される回路群の少なくとも１つとなる半導体集積回路であって、前記元の回路の代わりに、前記元の回路と同一又は等価な回路構成の２つのサブ回路を備えており、前記２つのサブ回路をなす第１及び第２のサブ回路のそれぞれが、前記元の回路の前記差動入力端子対をなす入力端子１つあたりの半分の入力容量を有し、各サブ回路の差動入力端子対をなす第１及び第２の入力端子と、前記元の回路の前記差動出力端子対をなす出力端子１つあたりの半分の駆動能力を有し、各サブ回路の差動出力端子対をなす第１及び第２の出力端子と、を有し、前記第１及び第２のサブ回路に対して、共通に設けられている、１つの差動入力端子対と１つの差動出力端子対とを有し、前記第１のサブ回路の第１の入力端子と前記第２のサブ回路の第２の入力端子とが、前記第１及び第２のサブ回路に共通の前記差動入力端子対の１つの入力端子に接続され、前記第１のサブ回路の第２の入力端子と前記第２のサブ回路の第１の入力端子とが、前記第１及び第２のサブ回路に共通の前記差動入力端子対の他の入力端子に接続され、前記第１のサブ回路の第１の出力端子と前記第２のサブ回路の第２の出力端子とが、前記第１及び第２のサブ回路に共通の前記差動出力端子対の１つの出力端子に接続され、前記第１のサブ回路の第２の出力端子と前記第２のサブ回路の第１の出力端子とが、前記第１及び第２のサブ回路に共通の前記差動出力端子対の他の出力端子に接続されている構成とされる。
【０００６】
本発明において、前記第１のサブ回路の配置と前記第２のサブ回路の配置、及び、前記第１のサブ回路と前記第２のサブ回路間の配線が、互いに鏡面反転の関係になるようにレイアウトされる。
【０００７】
本発明に係る設計方法は、半導体回路の回路情報を基に、半導体基板上への集積化のための、配置及び配線のレイアウト処理をコンピュータで行う半導体集積回路の設計方法であって、
（ａ）１つの差動入力端子対をなす２つの入力端子と、１つの差動出力端子対をなす２つの出力端子とを少なくとも有し、前記差動入力端子対からの信号を差動入力し、出力信号を前記差動出力端子対から差動出力する回路（「元の回路」という）の回路情報を記憶手段から入力し、前記元の回路を、前記元の回路と同一又は等価な機能の回路構成の２つのサブ回路で置き換え、前記２つのサブ回路の回路情報を記憶手段に記憶するステップを有し、
前記２つのサブ回路をなす第１及び第２のサブ回路のそれぞれが、前記元の回路の前記差動入力端子対をなす入力端子１つあたりの半分の入力容量を有し、各サブ回路の差動入力端子対をなす第１及び第２の入力端子と、前記元の回路の前記差動出力端子対をなす出力端子の半分の駆動能力を有し、各サブ回路の差動出力端子対をなす第１及び第２の出力端子と、を有するものであり、前記第１及び第２のサブ回路に対して、共通に、１つの差動入力端子対と１つの差動出力端子対とを用意し、
（ｂ）前記記憶手段より、前記第１及び第２のサブ回路の回路情報を入力し、前記第１のサブ回路の第１の入力端子と前記第２のサブ回路の第２の入力端子とを接続して、前記第１及び第２のサブ回路に共通の前記差動入力端子対の１つの入力端子とするステップと、
（ｃ）前記第１のサブ回路の第２の入力端子と前記第２のサブ回路の第１の入力端子とを接続して、前記第１及び第２のサブ回路に共通の前記差動入力端子対の他の入力端子とするステップと、
（ｄ）前記第１のサブ回路の第１の出力端子と前記第２のサブ回路の第２の出力端子とを接続して、前記第１及び第２のサブ回路に共通の前記差動出力端子対の１つの出力端子とし、
（ｅ）前記第１のサブ回路の第２の出力端子と第２のサブ回路の第１の出力端子を接続して、前記第１及び第２のサブ回路に共通の前記差動出力端子対の他の出力端子とするステップと、を含む。
【０００８】
本発明に係る設計方法において、前記第１のサブ半導体回路の配置と前記第２のサブ半導体回路の配置、及び、前記第１のサブ半導体回路と前記第２のサブ半導体回路間の配線が、互いに鏡面反転の関係になるようにレイアウトされる。
【０００９】
本発明に係る装置は、半導体回路の回路情報を基に、半導体基板上への集積化のための配置及び配線のレイアウト処理をコンピュータで行う設計自動化装置であって、１つの差動入力端子対をなす２つの入力端子と、１つの差動出力端子対をなす２つの出力端子とを少なくとも有し、前記差動入力端子対からの信号を差動入力し、出力信号を前記差動出力端子対から差動出力する回路（「元の回路」という）の回路情報を記憶手段から入力し、前記元の回路を、前記元の回路と同一又は等価な機能の回路構成の２つのサブ回路で置き換える手段を有し、前記２つのサブ回路をなす第１及び第２のサブ回路のそれぞれが、前記元の回路の前記差動入力端子対をなす入力端子１つあたりの半分の入力容量を有し、各サブ回路の差動入力端子対をなす第１及び第２の入力端子と、前記元の回路の前記差動出力端子対をなす出力端子１つあたりの半分の駆動能力を有し、各サブ回路の差動出力端子対をなす第１及び第２の出力端子と、を有し、前記第１及び第２のサブ回路に対して、共通に設けられた、１つの差動入力端子対と１つの差動出力端子対とを有し、前記第１のサブ回路の第１の入力端子と前記第２のサブ回路の第２の入力端子とを接続して、前記第１及び第２のサブ回路に共通の前記差動入力端子対の１つの入力端子とする手段と、前記第１のサブ回路の第２の入力端子と前記第２のサブ回路の第１の入力端子とを接続して、前記第１及び第２のサブ回路に共通の前記差動入力端子対の他の入力端子とする手段と、前記第１のサブ回路の第１の出力端子と前記第２のサブ回路の第２の出力端子とを接続して、前記第１及び第２のサブ回路に共通の前記差動出力端子対の１つの出力端子とする手段と、前記第１のサブ回路の第２の出力端子と前記第２のサブ回路の第１の出力端子を接続して、前記第１及び第２のサブ回路に共通の前記差動出力端子対の他の出力端子とする手段と、を備えている。
【００１０】
本発明に係るプログラムは、半導体回路の回路情報を基に、半導体基板上への集積化のための配置及び配線のレイアウト処理を行う設計自動化装置を構成するコンピュータで実行されるプログラムであって、１つの差動入力端子対をなす２つの入力端子と、１つの差動出力端子対をなす２つの出力端子とを少なくとも有し、前記差動入力端子対からの信号を差動入力し、出力信号を前記差動出力端子対から差動出力する回路（「元の回路」という）の回路情報を記憶手段から入力し、前記元の回路を、前記元の回路と同一又は等価な機能の回路構成の２つのサブ回路に分割し、前記２つのサブ回路の回路情報を記憶手段に記憶する第１の処理を有し、前記２つのサブ回路をなす第１及び第２のサブ回路のそれぞれが、前記元の回路の前記差動入力端子対をなす入力端子１つあたりの半分の入力容量を有し、各サブ回路の差動入力端子対をなす第１及び第２の入力端子と、前記元の回路の前記差動出力端子対をなす出力端子の半分の駆動能力を有し、各サブ回路の差動出力端子対をなす第１及び第２の出力端子と、を有するものであり、前記第１及び第２のサブ回路に対して、共通に、１つの差動入力端子対と１つの差動出力端子対とを用意し、前記記憶手段より、前記第１及び第２のサブ回路の回路情報を入力し、前記第１のサブ回路の第１の入力端子と前記第２のサブ回路の第２の入力端子とを接続して、前記第１及び第２のサブ回路に共通の前記差動入力端子対の１つの入力端子とし、前記第１のサブ回路の第２の入力端子と前記第２のサブ回路の第１の入力端子とを接続して、前記第１及び第２のサブ回路に共通の前記差動入力端子対の他の入力端子とする第２の処理と、前記第１のサブ回路の第１の出力端子と前記第２のサブ回路の第２の出力端子とを接続して、前記第１及び第２のサブ回路に共通の前記差動出力端子対の１つの出力端子とし、前記第１のサブ回路の第２の出力端子と第２のサブ回路の第１の出力端子を接続して、前記第１及び第２のサブ回路に共通の前記差動出力端子対の他の出力端子とする第３の処理と、を含み、前記第１乃至第３の処理を前記コンピュータに実行させるプログラムよりなる。
【００１１】
【発明の実施の形態】
本発明の実施の形態について説明する。本発明に係る半導体集積回路は、対をなす第１及び第２の差動入力端子と、対をなす第１及び第２の差動出力端子を有し、前記第１及び第２の差動入力端子からの信号を差動入力し、出力信号を前記第１及び第２の差動出力端子から差動出力する差動回路（「元の差動回路」ともいう）（図１の２１）を、この半導体回路と同一又は等価な機能の回路構成の、２つのサブ差動回路（「サブ半導体回路」ともいう）（図２の１、６）に分割して、元の差動回路を、これら２つのサブ差動回路で置き換えて構成したものである。
【００１２】
２つのサブ差動回路をなす第１及び第２のサブ差動回路のそれぞれは、元の差動回路の差動入力端子対（２２、２３）をなす第１又は第２の差動入力端子１つあたりの半分の入力容量を有し、各サブ差動回路の差動入力端子対をなす第１及び第２の差動入力端子（図２の２、３）（７、８）と、元の差動回路の差動出力端子対（２４、２５）をなす第１又は第２の差動出力端子１つあたりの半分の駆動能力を有し、各サブ差動回路の差動出力端子対をなす第１及び第２の差動出力端子（４、５）（９、１０）を有している。
【００１３】
また第１及び第２のサブ差動回路（図２の１、６）に対して、共通に、１つの差動入力端子対（１１、１２）と１つの差動出力端子対（１３、１４）が設けられている。
【００１４】
第１のサブ差動回路（１）の第１の差動入力端子（２）と、第２のサブ差動回路（６）の第２の差動入力端子（８）とを接続して、第１及び第２のサブ差動回路に対して共通の差動入力端子対（１１、１２）の１つの入力端子（１１）とし、第１のサブ差動回路（１）の第２の差動入力端子（３）と第２のサブ差動回路（６）の第１の差動入力端子（７）とを接続して、第１及び第２のサブ差動回路に対して共通の差動入力端子対（１１、１２）の他の入力端子（１２）とし、第１のサブ差動回路（１）の第１の差動出力端子（４）と第２のサブ差動回路（６）の第２の差動出力端子（１０）とを接続して、第１及び第２のサブ差動回路に対して共通の差動出力端子対（１３、１４）の１つの出力端子（１３）とし、第１のサブ差動回路（１）の第２の差動出力端子（５）と第２のサブ差動回路（６）の第１の差動出力端子（９）を接続して、第１及び第２のサブ差動回路に対して共通の差動出力端子対（１３、１４）の他の出力端子（１４）としている。
【００１５】
第１のサブ差動回路（１）の配置と第２のサブ差動回路（６）の配置、及び、第１のサブ差動回路（１）と第２のサブ差動回路（６）間の配線は、互いに鏡面反転の関係になるようにレイアウトされている。例えば図２の破線に関して、回路の配置、相互の位置、配線パタン、配線長等は、鏡面反転の関係とされている。
【００１６】
本発明に係る方法においては、回路設計フェーズにより回路最適化後の差動回路の回路情報を記憶装置から読み出し、差動回路を同じ回路構成の複数のサブ差動回路に分割する。複数のサブ差動回路は、回路構成（回路トポロジー）は元の差動回路と同一であるが、サイズが縮減されている。
【００１７】
また、各サブ差動回路及び配線が鏡面反転の関係になるように、レイアウト配置し、各サブ回路の対応する端子を、前記回路と同じ入力容量、駆動能力となるようにそれぞれ接続して差動端子対とする。
【００１８】
このとき、鏡面反転の関係にあるサブ差動回路対の対応する端子を互い違いに接続すれば、差動端子対間の特性のアンバランスがキャンセルされて、差動特性が改善するとともに、分割前の元の差動回路と同特性をもつ差動回路を構成することができる。
【００１９】
本発明において、レイアウト処理は、半導体回路の回路情報を基に、半導体基板上への集積化のための配置及び配線処理をコンピュータで行う設計自動化装置で行われる。
【００２０】
この設計自動化装置は、１つの差動入力端子対をなす２つの入力端子と、１つの差動出力端子対をなす２つの出力端子とを少なくとも有し、前記差動入力端子対からの信号を差動入力し、出力信号を前記差動出力端子対から差動出力する回路（「元の回路」という）の回路情報を記憶手段から入力し、前記元の回路を、前記元の回路と同一又は等価な機能の回路構成の２つのサブ回路で置き換える手段を有している。前記２つのサブ回路をなす第１及び第２のサブ回路のそれぞれが、前記元の回路の前記差動入力端子対をなす入力端子１つあたりの半分の入力容量を有し、各サブ回路の差動入力端子対をなす第１及び第２の入力端子と、前記元の回路の前記差動出力端子対をなす出力端子１つあたりの半分の駆動能力を有し、各サブ回路の差動出力端子対をなす第１及び第２の出力端子と、を有する。
【００２１】
分割された前記第１及び第２のサブ回路に対して、共通に、１つの差動入力端子対１つの差動出力端子対とを用意する。
【００２２】
前記第１のサブ回路の第１の入力端子と前記第２のサブ回路の第２の入力端子とを接続して、前記第１及び第２のサブ回路に共通の前記差動入力端子対の１つの入力端子とし、前記第１のサブ回路の第２の入力端子と前記第２のサブ回路の第１の入力端子とを接続して、前記第１及び第２のサブ回路に共通の前記差動入力端子対の他の入力端子とし、前記第１のサブ回路の第１の出力端子と前記第２のサブ回路の第２の出力端子とを接続して、前記第１及び第２のサブ回路に共通の前記差動出力端子対の１つの出力端子とし、前記第１のサブ回路の第２の出力端子と前記第２のサブ回路の第１の出力端子を接続して、前記第１及び第２のサブ回路に共通の前記差動出力端子対の他の出力端子とし、レイアウト結果情報を記憶手段に出力する手段を備えている。この設計自動化装置の上記各処理は、コンピュータで実行されるプログラムによりその処理が実現される。
【００２３】
本発明は、別の実施の形態において、さらに、上記第１のサブ回路（図２の１）は、該第１のサブ回路と同一又は等価な機能の回路構成のＮ個（Ｎは２以上の整数）の第１群の子の回路（図３の３１、…４１）で置き換えられて構成され、上記第２のサブ回路（図２の６）は、該第２のサブ回路と同一又は等価な機能の回路構成のＮ個の第２群の子の回路（図３の３６、…４６）で置き換えられて構成されており、前記Ｎ個の第１群の子の回路と前記Ｎ個の第２群の子回路に対して、共通に設けられている、１つの差動入力端子対（図３の５１、５２）と１つの差動出力端子対（図３の５３、５４）とを有する。前記Ｎ個の第１群の子の回路のそれぞれは、前記第１のサブ回路（図２の１）の前記差動入力端子対（図２の２、３）をなす入力端子１つあたりのＮ分の１の入力容量を有し、各子の回路の差動入力端子対をなす第１及び第２の入力端子（３２、３３）と、前記第１のサブ回路の前記差動出力端子対（図２の４、５）をなす出力端子１つあたりのＮ分の１の駆動能力を有し、各子の回路の差動出力端対をなす第１及び第２の出力端子（３４、３５）と、を有する。前記Ｎ個の第２群の子の回路のそれぞれは、前記第２のサブ回路（図２の６）の前記差動入力端子対（７、８）をなす入力端子１つあたりのＮ分の１の入力容量を有し、各子の回路の差動入力端子対をなす第１及び第２の入力端子と第２の入力端子（３７、３８）と、前記第２のサブ回路の前記差動出力端子対（９、１０）をなす出力端子１つあたりのＮ分の１の駆動能力を有し、各子の回路の差動出力端子対をなす第１及び第２の出力端子（３９、４０）と、を有し、Ｎ個の前記第１群の子の回路とＮ個の前記第２群の子の回路とのそれぞれについて、前記第１群の子の回路と、前記第１群の子の回路に対応する前記第２群の子の回路とは、互いに鏡面反転の関係になるように、レイアウトされており、互いに鏡面反転の関係にあり対をなす第１の子の回路と第２の子の回路について、前記第１の子の回路の第１の入力端子（３３）と前記第２の子の回路の第２の入力端子（３８）とが接続され、共通に設けられた前記差動入力端子対（５２、５４）の１つの入力端子に接続され、前記第１の子の回路の第２の入力端子（３３）と前記第２の子の回路の第１の入力端子（３７）とが接続され、共通に設けられた前記差動入力端子対（５２、５４）の他の入力端子に接続され、前記第１の子の回路の第１の出力端子（３４）と前記第２の子の回路の第２の出力端子（４０）とが接続され、前記共通に設けられた前記差動出力端子対（５３、５４）の１つの出力端子に接続され、前記第１の子の回路の第２の出力端子（３５）と前記第２の子の回路の第１の出力端子（３９）とが接続され、共通に設けられた前記差動出力端子対（５３、５４）の他の出力端子に接続されている。以下、具体的な実施例に即して詳細に説明する。
【００２４】
【実施例】
上記した本発明の実施の形態についてさらに詳細に説明すべく、本発明の実施例について図面を参照して以下に説明する。図１は、本発明の一実施例を説明するための図である。図１には、一対の差動入力端子２２及び２３と、一対の差動出力端子２４及び２５を有する差動回路２１が示されている。差動回路２１は、差動入力端子対２２及び２３に供給される入力信号を差動で入力し、差動出力端子対２４及び２５から差動で出力する。
【００２５】
図２は、本発明の一実施例を説明するための図であり、図１の差動回路２１を２つのサブ半導体回路で置き換える場合の一例が示されている。図２を参照すると、この実施例において、図１の差動回路２１の代わりに、半導体集積回路に集積化され、それぞれがサブ差動回路をなす２つのサブ半導体回路１及び６は、図１の差動回路２１と同一又は等価な機能の回路構成の回路よりなり、それぞれが、差動入力端子対と差動出力端子対とを有し、後述するように、互いに鏡面反転の関係となるように、配置・配線されている。
【００２６】
それぞれのサブ半導体回路１、６の各入力端子２、３、７、８の入力容量は、差動回路２１の差動入力端子対をなす第１又は第２の入力端子２２、２３の１つあたりの入力容量の半分である。それぞれのサブ半導体回路１、６の各出力端子４、５、９、１０の駆動能力（電流駆動能力）は、差動回路２１の差動出力端子対をなす第１又は第２の出力端子２４、２５の１つあたりの駆動能力の半分である。
【００２７】
第１及び第２のサブ半導体回路１及び６は、互いに鏡面反転の関係になるようにしてレイアウトされている。すなわち第１及び第２のサブ半導体回路１及び６の配置は、図２の破線に関して対称である。第１のサブ半導体回路１の第１の差動入力端子２と第２のサブ半導体回路６の第１の差動入力端子７の配置は、図２の破線に関して対称とされ、第１のサブ半導体回路１の第２の差動入力端子３と第２のサブ半導体回路６の第２の差動入力端子８の配置は、図２の破線に関して対称とされている。第１のサブ半導体回路１の第１の差動出力端子４と第２のサブ半導体回路６の第１の差動出力端子９の配置は、図２の破線に関して対称とされ、第１のサブ半導体回路１の第２の差動出力端子５と第２のサブ半導体回路６の第２の差動出力端子１０の配置は、図２の破線に関して対称とされている。さらに第１及び第２のサブ半導体回路１及び６に対して共通に設けられている差動入力端子対１１と１２との配置、差動出力端子対１３と１４との配置は、図２の破線に関して対称である。
【００２８】
第１のサブ半導体回路１の第１の差動入力端子２と第２のサブ半導体回路６の第２の差動入力端子８とを接続して、第１及び第２のサブ半導体回路１及び６に共通に設けられている第１の差動入力端子１１とする。
【００２９】
同様に、第１のサブ半導体回路１の第２の差動入力端子３と第２のサブ半導体回路６の第１の差動入力端子７とを接続して、第１及び第２のサブ半導体回路１及び６に共通に設けられている第２の差動入力端子１２とする。
【００３０】
第１のサブ半導体回路１の第１の差動入力端子２から第１の差動入力端子１１までの配線長と、第２のサブ半導体回路６の第２の差動入力端子８から第１の差動入力端子１１までの配線長の和は、第１のサブ半導体回路１の第２の差動入力端子３から第２の差動入力端子１２までの配線長と、第２のサブ半導体回路６の第１の差動入力端子７から第２の差動入力端子１２までの配線長との和に等しい。
【００３１】
第１のサブ半導体回路１の第１の差動出力端子４と第２のサブ半導体回路６の第２の差動出力端子１０とを接続して、第１及び第２のサブ半導体回路１及び６に共通に設けられている第１の差動出力端子１３とする。
【００３２】
第１のサブ半導体回路１の第２の差動出力端子５と第２のサブ半導体回路６の第１の差動出力端子９とを接続して、第１及び第２のサブ半導体回路１及び６に共通に設けられている第２の差動出力端子１４とする。
【００３３】
第１のサブ半導体回路１の第１の差動出力端子４から第１の差動出力端子１３までの配線長と、第２のサブ半導体回路６の第２の差動出力端子１０から第１の差動出力端子１３までの配線長との和は、第１のサブ半導体回路１の第２の差動出力端子５から第２の差動出力端子１４までの配線長と第２のサブ半導体回路６の第１の差動出力端子９から第２の差動出力端子１４までの配線長との和に等しい。
【００３４】
以上のように配置及び配線することで、図２の差動回路は、図１の差動回路２１と同じ入力容量、駆動能力を持ち、差動端子対間の特性のアンバランスをキャンセルできる。
【００３５】
例えば図２の第１の差動入力端子１１の入力容量は、サブ半導体回路１の第１の差動入力端子２とサブ半導体回路６の第２の差動入力端子８の入力容量の和となり、第２の差動入力端子１２の入力容量は、サブ半導体回路１の第２の差動入力端子３とサブ半導体回路６の第１の差動入力端子７の入力容量の和となる。このため、図１の差動回路２１において、例えば第１の差動入力端子２２の入力容量が及び第２の差動入力端子２３の入力容量よりも大である場合であっても、第１の差動入力端子１１の入力容量と第２の差動入力端子１２の入力容量は等しくなる。すなわち、元の回路の差動入力端子対のおける入力容量のばらつきが、図２の差動入力端子対１１及び１２の構成においては、バランスする。各サブ半導体回路の差動入力端子対から、共通の差動入力端子対１１及び１２に交叉接続される配線長の和が等しいことも、差動入力端子対１１及び１２おける特性のバランスに貢献している。
【００３６】
図２の第１の差動出力端子１１の駆動能力は、サブ半導体回路１の第１の差動出力端子４とサブ半導体回路６の第２の差動入力端子１０駆動能力の和となり、第２の差動出力端子１４の駆動能力は、サブ半導体回路１の第２の差動出力端子５とサブ半導体回路６の第１の差動出力端子９の駆動能力の和となる。このため、図１の差動回路２１において第１の差動出力端子及び第２の差動出力端子２４及び２５の駆動能力とが異なる場合であっても、第１の差動出力端子１３と第２の差動出力端子１４の駆動能力が等しくなる。すなわち、図２の差動出力端子対１３、１４の駆動能力はバランスする。各サブ半導体回路の差動出力端子対から、共通の差動出力端子対１３及び１４に交叉接続される配線長の和が等しいことも、差動入力端子対１３及び１４おける特性のバランスに貢献している。
【００３７】
例えばサブ半導体回路１（６）が、ＭＯＳトランジスタよりなる差動入力段（不図示）を備えている場合、差動入力端子対２、３（７、８）にそれぞれ接続されるゲート容量（例えばゲート幅）は、差動回路２１の差動入力端子対２２、２３に接続されるＭＯＳ差動入力段のゲート容量の半分とされる。また、出力端子の駆動能力を差動回路２１の半分とするサブ半導体回路１（６）においては、各出力端子４、５（９、１０）にそれぞれ接続される、図示されない出力段のＭＯＳトランジスタの利得係数β（β＝（με／ｔＯＸ）（Ｗ／Ｌ）、ただし、μはキャリアの移動度、εはゲート絶縁膜の誘電率、ｔＯＸはゲート絶縁膜の膜厚、Ｗはチャネル幅、Ｌはチャネル長である）は、差動回路２１の差動出力端子対２４、２５のそれぞれ接続される出力段のＭＯＳトランジスタの利得係数βの半分としてもよい。
【００３８】
磁気ディスク、半導体メモリ、あるいはネットワーク等の通信媒体より図１の差動回路２１の回路情報を入力するコンピュータ等の情報処理装置において、差動回路２１の回路情報に基づき、図３に示した２つのサブ差動回路１及び６を生成して、２つのサブ差動回路１及び６の回路情報をメモリに格納し、必要に応じて表示装置にグラフィックス等で表示し、さらに、２つのサブ差動回路１及び６を互いに鏡面反転となるように配置し、２つのサブ差動回路１及び６の差動入力端子対２、３と７、８の、共通の差動入力端子対１１及び１２への配線接続、２つのサブ差動回路１及び６の差動出力端子対４、５と９、１０の、共通の差動出力端子対１３及び１４への配線接続をコンピュータで行う構成としてもよい。
【００３９】
図３は、本発明の第２の実施例の構成を示している。図３を参照すると、この実施例においては、図１の差動回路２１と同一の構成であり、２Ｎ個の子半導体回路３１、３６、…、４１及び４６が、鏡面反転の関係になるように、レイアウト配置されている。子半導体回路３１、３６、…、４１及び４６の差動入力端子対の１つの入力端子の入力容量と、差動出力端子対の１つの出力端子の駆動能力は、図１の差動回路２１の差動入力端子対の１つの入力端子と２Ｎ分の１（Ｎは、正整数）図１の差動回路２１の差動出力端子対の１つの出力端子と２Ｎ分の１（Ｎは、正整数）とされる。
【００４０】
図３に示した構成は、図２の第１のサブ半導体回路１を、第１のサブ半導体回路と同一の回路構成のＮ個の第１群の子半導体回路３１、…４１で置き換えて構成し、図２の第２のサブ半導体回路６を、第２のサブ半導体回路と同一の回路構成のＮ個の第２群の子半導体回路３６、…４６で置き換えて構成している。
【００４１】
Ｎ個の第１群の子半導体回路は、第１のサブ半導体回路の第１又は第２の差動入力端子（２又は３）のＮ分の１の入力容量を有し、対をなす第１及び第２の差動入力端子（３２、３３）…（４２、４３）と、第１のサブ半導体回路１の第１又は第２の差動出力端子（４又は５）のＮ分の１の駆動能力を有し、対をなす第１及び第２の差動出力端子（３４、３５）…（４４、４５）と、を有する。
【００４２】
Ｎ個の第２群の子半導体回路３６、…４６は、第２のサブ半導体回路６の第１又は第２の差動入力端子７又は８のＮ分の１の入力容量を有し、対をなす第１、第２の差動入力端子と第２の差動入力端子（３７、３８）…（４７、４８）と、第２のサブ半導体回路の第１又は第２の差動出力端子９又は１０のＮ分の１の駆動能力を有し、対をなす第１及び第２の差動出力端子（３９、４０）…（４９、５０）と、を有する。２Ｎ個の子半導体回路は、鏡面反転の関係になるようにレイアウトされている。
【００４３】
互いに鏡面反転の関係にあり対をなす第１の子半導体回路と第２の子半導体回路のそれぞれについて、例えば第１の子半導体回路３１の第１の差動入力端子３２と第２の子半導体回路３６の第２の差動入力端子３８とを接続して、共通の第１の差動入力端子５１に接続し、第１の子半導体回路３１の第２の差動入力端子３２と第２の子半導体回路３６の第１の差動入力端子３７とを接続して、共通の第２の差動入力端子５２に接続し、第１の子半導体回路３１の第１の差動出力端子３４と第２の子半導体回路３６の第２の差動出力端子４０とを接続して、共通の第１の差動出力端子５３に接続し、第１の子半導体回路３１の第２の差動出力端子３５と第２の子半導体回路３６の第１の差動出力端子３９とを接続して、共通の第１の差動出力端子５４に接続している。鏡面反転の関係にある他の対をなす第１の子半導体回路と第２の子半導体回路についても同様とされる。
【００４４】
サブ半導体回路の差動端子対間の特性のアンバランスをキャンセルするために、鏡面反転の関係にあり互いに対をなす各サブ半導体回路対の差動端子対同士が交叉接続されて差動端子とされている。すなわち、上記した通り、鏡面反転の関係にあり対をなす第１群の第１の子半導体回路３１と第２群の第２の子半導体回路３６〜第１群の第Ｎの子半導体回路４１と第２群の第Ｎの子半導体回路４６において、子半導体回路３１の第１の差動入力端子３２と子半導体回路３６の第２の差動入力端子３８が交叉接続され、…子半導体回路４１の第１の差動入力端子４２と子半導体回路４６の第２の差動入力端子４８とが交叉接続されて、共通の差動入力端子５１とされ、子半導体回路３１の第２の差動入力端子３３と子半導体回路３６の第１の差動入力端子３７が交叉接続され、…、子半導体回路４１の第２の差動入力端子４３と子半導体回路４６の第１の差動入力端子４７とが交叉接続されて、共通の差動入力端子５３とされている。第１群の第１の子半導体回路３１と第２群の第２の子半導体回路３６〜第１群の第Ｎの子半導体回路４１と第２群の第Ｎの子半導体回路４６の出力端子対と共通の出力端子対５３、５４についても同様とされる。
【００４５】
図４は、多差動入力端子対、多差動出力端子対（Ａ組の差動入力端子対とＢ組の差動出力端子対）を持つ差動回路６９の構成を示す図である。例えば、第１の差動入力端子対は、第１の差動入力端子６１と第２の差動入力端子６２、第Ａ（Ａは自然数）の差動入力端子対は、第１の差動入力端子６３と第２の差動入力端子６４で構成される。第１の差動出力端子対は、第１の差動出力端子６５と第２の差動出力端子６６、第Ｂ（Ｂは自然数）の差動出力端子対は、第１の差動出力端子６７と第２の差動入力端子６８で構成される。
【００４６】
図５は、本発明の第３の実施例の構成を示す図である。図５を参照すると、この実施例では、図４に示した差動回路６９と同一の回路構成とされ、差動入力端子対の入力容量、差動出力端子対の容量が差動回路６９の差動入力端子と差動出力端子のそれぞれの端子の１／Ｎ（ただし、Ｎは所定の正整数）の、Ｎ個の第１群の子半導体回路７１、…８９と、Ｎ個の第２群の子半導体回路８０、…９８で図４に示した差動回路６９を置き換えたものである。Ｎ個の第１群の子半導体回路７１、…８９と、Ｎ個の第２群の子半導体回路８０、…９８のそれぞれは、鏡面反転の関係になるようにレイアウト配置される。このとき、鏡面反転の関係にあり対をなす子半導体回路（例えば第１群の第１の子半導体回路７１と第２群の第１の子半導体回路８０、あるいは、第１群の第Ｎの子半導体回路８９と第２群の第Ｎの子半導体回路９８等）の差動端子対間の特性のアンバランスをキャンセルするために、鏡面反転の関係にあるサブ半導体回路同士の端子を互い違いに接続して差動端子とする。
【００４７】
例えば、第１群の第１の子半導体回路７１の第１の差動入力端子対の第１の差動入力端子７２と、第２群の第１のサブ半導体回路８０の第１の差動入力端子対の第２の差動入力端子８２とを交叉接続し、…、第１群の第Ｎのサブ半導体回路８９の第１の差動入力端子対の第１の差動入力端子９０と、第２群の第Ｎのサブ半導体回路９８の第１の差動入力端子対の第２の差動入力端子１００とを交叉接続して、第１の差動端子対の第１の差動入力端子１０７としている。また第１群の第１の子半導体回路７１の第１の差動入力端子対の第２の差動入力端子７３と、第２群の第１のサブ半導体回路８０の第１の差動入力端子対の第１の差動入力端子８１とを交叉接続し、…、第１群の第Ｎのサブ半導体回路８９の第１の差動入力端子対の第２の差動入力端子９１と、第２群の第Ｎのサブ半導体回路９８の第１の差動入力端子対の第１の差動入力端子９９とを交叉接続して、第１の差動端子対の第２の差動入力端子１０８としている。
【００４８】
差動回路の具体的な一例について説明する。図６を参照すると、この差動回路は、ソースが接地された電流源トランジスタ２０５のドレインに、ソースが共通に接続され、ゲートがそれぞれ差動入力端子２０６及び２０７に接続され差動対をなすＮチャネルＭＯＳトランジスタ２０３及び２０４と、ＮチャネルＭＯＳトランジスタ２０３及び２０４のドレインと電源ＶＤＤ間に接続される抵抗負荷２０１及び２０２を備えた抵抗負荷型ＣＭＬ（ｃｕｒｒｅｎｔ　ｍｏｄｅ　ｌｏｇｉｃ）インバータ回路である。ＭＯＳトランジスタ２０３及び２０４のドレインは差動出力端子２０８及び２０９に接続されている。
【００４９】
また、図７は、本発明の第４の実施例を示しており、図６に示した抵抗負荷型ＣＭＬインバータ回路の差動対トランジスタ２０３及び２０４、電流源トランジスタ２０５のゲート幅（Ｗ）のサイズを半分とし、負荷抵抗の抵抗値を半分にして、２つのサブＣＭＬインバータ回路に分割し、その端子を互い違いに接続している。図７を参照すると、ソースが接地された電流源トランジスタ３０９のドレインに、ソースが共通に接続され、ゲートがそれぞれ差動入力端子３１１及び３１２に接続され差動対をなすＮチャネルＭＯＳトランジスタ３０５及３０６と、ＮチャネルＭＯＳトランジスタ３０５及び３０６のドレインと電源ＶＤＤ間に接続される抵抗負荷３０１及び３０２を備えた第１のサブＣＭＬインバータ回路と、ソースが接地された電流源トランジスタ３１０のドレインに、ソースが共通に接続され、ゲートがそれぞれ差動入力端子３１３及び３１４に接続され差動対をなすＮチャネルＭＯＳトランジスタ３０７及３０８と、ＮチャネルＭＯＳトランジスタ３０７及び３０８のドレインと電源ＶＤＤ間に接続される抵抗負荷３０３及び３０４を備えた第２のサブＣＭＬインバータ回路と、を備え、共通の差動入力端子対の第１の差動入力端子３１９が、第１のサブＣＭＬインバータ回路の第１の差動入力端子３１１及び第２のサブＣＭＬインバータ回路の第２の差動入力端子３１４に接続されており、共通の差動入力端子対の第２の差動入力端子３２０が、第１のサブＣＭＬインバータ回路の第２の差動入力端子３１２及び第２のサブＣＭＬインバータ回路の第１の差動入力端子３１３に接続されている。また、共通の差動出力端子対の第１の差動出力端子３２１が、第１のサブＣＭＬインバータ回路の第１の差動出力端子３１５及び第２のサブＣＭＬインバータ回路の第２の差動出力端子３１８に接続されており、共通の差動出力端子対の第２の差動出力端子３２２が、第１のサブＣＭＬインバータ回路の第２の差動出力端子３１６及び第２のサブＣＭＬインバータ回路の第１の差動出力端子３１７に接続されている。
【００５０】
図７に示す回路では。電流源用のトランジスタ３０９及び３１０のバイアス端子３２３及び３２４を接続して共通のバイアス電圧を供給し、第１、第２のサブＣＭＬ回路の差動対をそれぞれ駆動している。かかる構成により、図６の抵抗負荷型ＣＭＬインバータ回路と同じ入力容量、駆動能力を持ち、また差動端子間の特性のアンバランスをキャンセルできる。
【００５１】
図８は、図７に示した回路のレイアウトの一例を示す図である。負荷抵抗４０１及び４０２、差動対をなす入力トランジスタ対４０７及び４０８、電流源用のトランジスタ４０５で構成される第１のサブＣＭＬ回路と、負荷抵抗４０３及び４０４、差動対をなす入力トランジスタ対４０９及び４１０、電流源のトランジスタ４０６で構成される第２のサブＣＭＬインバータ回路が、鏡面反転の関係になるように配置されている。上述したように、２つのサブＣＭＬインバータ回路の差動入力端子対について第１のサブＣＭＬインバータ回路の第１の差動入力端子と第２のサブＣＭＬインバータ回路の第２の差動入力端子とを交叉接続し、第１のサブＣＭＬインバータ回路の第２の差動入力端子と第２のサブＣＭＬインバータ回路の第１の差動入力端子とを交叉接続し、２つのサブＣＭＬインバータ回路の差動出力端子対についても同様に交叉接続されている。
【００５２】
以上本発明を上記各実施例に即して説明したが、本発明は上記実施例の構成にのみ限定されるものでなく、特許請求の範囲の各請求項の発明の範囲内で当業者であればなし得るであろう各種変形、修正を含むことは勿論である。
【００５３】
【発明の効果】
以上説明したように、本発明によれば、入力容量や駆動能力といった特性が等しいまま、差動端子対間の特性のアンバランスをキャンセルすることができ、差動特性を容易に改善することができるという効果を奏する。
【図面の簡単な説明】
【図１】差動回路の構成の一例を示す図である。
【図２】本発明の第１の実施例の回路構成の一例を示す図である。
【図３】本発明の第２の実施例の回路構成の一例を示す図である。
【図４】多差動入力端子対、多差動出力端子対を持つ差動回路の一例を示す図である。
【図５】本発明の第３の実施例の回路構成の一例を示す図である。
【図６】抵抗負荷型ＣＭＬインバータ回路の一例を示す図である。
【図７】本発明の第４の実施例の回路構成の一例を示す図である。
【図８】本発明の第４の実施例を示すレイアウトの一例を示す図である。
【符号の説明】
２１　差動回路
２２　第１の差動入力端子
２３　第２の差動入力端子
２４　第１の差動出力端子
２５　第２の差動出力端子
１　第１のサブ半導体回路
２　第１の差動入力端子
３　第２の差動入力端子
４　第１の差動出力端子
５　第２の差動出力端子
６　第２のサブ半導体回路
７　第１の差動入力端子
８　第２の差動入力端子
９　第１の差動出力端子
１０　第２の差動出力端子
１１　第１の差動入力端子
１２　第２の差動入力端子
１３　第１の差動出力端子
１４　第２の差動出力端子
３１　第１群の第１のサブ半導体回路
３２　第１の差動入力端子
３３　第２の差動入力端子
３４　第１の差動出力端子
３５　第２の差動出力端子
３６　第２群の第２のサブ半導体回路
３７　第１の差動入力端子
３８　第２の差動入力端子
３９　第１の差動出力端子
４０　第２の差動出力端子
４１　第１群の第Ｎのサブ半導体回路
４２　第１の差動入力端子
４３　第２の差動入力端子
４４　第１の差動出力端子
４５　第２の差動出力端子
４６　第２群の第Ｎのサブ半導体回路
４７　第１の差動入力端子
４８　第２の差動入力端子
４９　第１の差動出力端子
５０　第２の差動出力端子
５１　第１の差動入力端子
５２　第２の差動入力端子
５３　第１の差動出力端子
５４　第２の差動出力端子
６１　第１の差動入力端子
６２　第２の差動入力端子
６３　第１の差動入力端子
６４　第２の差動入力端子
６５　第１の差動出力端子
６６　第２の差動出力端子
６７　第１の差動出力端子
６８　第２の差動出力端子
６９　差動回路
７１　第１群の第１のサブ半導体回路
７２　第１の差動入力端子対の第１の差動入力端子
７３　第１の差動入力端子対の第２の差動入力端子
７４　第Ａの差動入力端子対の第１の差動入力端子
７５　第Ａの差動入力端子対の第２の差動入力端子
７６　第１の差動出力端子対の第１の差動出力端子
７７　第１の差動出力端子対の第２の差動出力端子
７８　第Ｂの差動出力端子対の第１の差動出力端子
７９　第Ｂの差動出力端子対の第２の差動出力端子
８０　第２群の第１のサブ半導体回路
８１　第１の差動入力端子対の第１の差動入力端子
８２　第１の差動入力端子対の第２の差動入力端子
８３　第Ａの差動入力端子対の第１の差動入力端子
８４　第Ａの差動入力端子対の第２の差動入力端子
８５　第１の差動出力端子対の第１の差動出力端子
８６　第１の差動出力端子対の第２の差動出力端子
８７　第Ｂの差動出力端子対の第１の差動出力端子
８８　第Ｂの差動出力端子対の第２の差動出力端子
８９　第１群の第Ｎのサブ半導体回路
９０　第１の差動入力端子対の第１の差動入力端子
９１　第１の差動入力端子対の第２の差動入力端子
９２　第Ａの差動入力端子対の第１の差動入力端子
９３　第Ａの差動入力端子対の第２の差動入力端子
９４　第１の差動出力端子対の第１の差動出力端子
９５　第１の差動出力端子対の第２の差動出力端子
９６　第Ｂの差動出力端子対の第１の差動出力端子
９７　第Ｂの差動出力端子対の第２の差動出力端子
９８　第２群の第Ｎのサブ半導体回路
９９　第１の差動入力端子対の第１の差動入力端子
１００　第１の差動入力端子対の第２の差動入力端子
１０１　第Ａの差動入力端子対の第１の差動入力端子
１０２　第Ａの差動入力端子対の第２の差動入力端子
１０３　第１の差動出力端子対の第１の差動出力端子
１０４　第１の差動出力端子対の第２の差動出力端子
１０５　第Ｂの差動出力端子対の第１の差動出力端子
１０６　第Ｂの差動出力端子対の第２の差動出力端子
１０７　第１の差動入力端子対の第１の差動入力端子
１０８　第１の差動入力端子対の第２の差動入力端子
１０９　第１の差動出力端子対の第１の差動出力端子
１１０　第１の差動出力端子対の第２の差動出力端子
２０１　第１の抵抗
２０２　第２の抵抗
２０３　第１の入力トランジスタ
２０４　第２の入力トランジスタ
２０５　電流源用のトランジスタ
２０６　第１の差動入力端子
２０７　第２の差動入力端子
２０８　第１の差動出力端子
２０９　第２の差動出力端子
２１０　電流源用のトランジスタのバイアス端子
３０１　第１のサブ回路の第１の抵抗
３０２　第１のサブ回路の第２の抵抗
３０３　第２のサブ回路の第１の抵抗
３０４　第２のサブ回路の第２の抵抗
３０５　第１のサブ回路の第１の入力トランジスタ
３０６　第１のサブ回路の第２の入力トランジスタ
３０７　第２のサブ回路の第１の入力トランジスタ
３０８　第２のサブ回路の第２の入力トランジスタ
３０９　第１のサブ回路の電流源トランジスタ
３１０　第２のサブ回路の電流源トランジスタ
３１１　第１のサブ回路の第１の差動入力端子
３１２　第１のサブ回路の第２の差動入力端子
３１３　第２のサブ回路の第１の差動入力端子
３１４　第２のサブ回路の第２の差動入力端子
３１５　第１のサブ回路の第１の差動出力端子
３１６　第１のサブ回路の第２の差動出力端子
３１７　第２のサブ回路の第１の差動出力端子
３１８　第２のサブ回路の第２の差動出力端子
３１９　第１の差動入力端子
３２０　第２の差動入力端子
３２１　第１の差動出力端子
３２２　第２の差動出力端子
３２３　第１のサブ回路の電流源トランジスタのバイアス端子
３２４　第２のサブ回路の電流源トランジスタのバイアス端子
４０１　第１のサブ回路の第１の抵抗
４０２　第１のサブ回路の第２の抵抗
４０３　第２のサブ回路の第１の抵抗
４０４　第２のサブ回路の第２の抵抗
４０５　第１のサブ回路の電流源用のトランジスタ
４０６　第２のサブ回路の電流源用のトランジスタ
４０７　第１のサブ回路の第１の入力トランジスタ
４０８　第１のサブ回路の第２の入力トランジスタ
４０９　第２のサブ回路の第１の入力トランジスタ
４１０　第２のサブ回路の第２の入力トランジスタ[0001]
[Technical field to which the present invention pertains]
The present invention relates to a semiconductor integrated circuit, and more particularly, to a semiconductor integrated circuit that suppresses imbalance in differential characteristics of a semiconductor circuit in a differential operation, a method of designing a semiconductor integrated circuit, and a design automation apparatus.
[0002]
[Prior art]
For example, a differential operation semiconductor circuit (referred to as a “differential circuit”) that differentially inputs a signal transmitted differentially through a balanced transmission line from a differential input terminal pair and outputs differentially from a differential output terminal pair An analog circuit that requires high precision because it generally has better noise immunity than a single-ended operation semiconductor circuit using only a single signal (transmitted through an unbalanced transmission line); It is frequently used in high-speed digital transmission circuits and the like. Conventionally, when designing a differential circuit, a circuit simulation is performed to optimize each element size such as a resistance value and a transistor size, and based on the size, a mask layout is performed so as to be symmetrical. .
[0003]
[Problems to be solved by the invention]
However, when the circuit is designed and laid out by the above-described design method, a good result of the differential characteristics of the differential circuit is obtained in the circuit simulation before the layout, but it may be difficult to lay out the circuit symmetrically. . For this reason, there is a problem that unbalance occurs in the characteristics between the differential terminal pairs and the differential characteristics of the differential circuit deteriorate.
[0004]
Therefore, the present invention has been made in view of the above-described problems, and has a semiconductor integrated circuit and a design method that are effective for suppressing imbalance in differential characteristics, and a design that performs layout based on circuit information. An object of the present invention is to provide an automation device.
[0005]
[Means to solve the problem]
A semiconductor integrated circuit according to the present invention that achieves the above object includes at least two input terminals forming one differential input terminal pair and two output terminals forming one differential output terminal pair. A circuit that differentially inputs an input signal from an input terminal pair and differentially outputs an output signal from the differential output terminal pair (referred to as an “original circuit”) is included in at least a circuit group integrated on the same chip. A single semiconductor integrated circuit, comprising, in place of the original circuit, two sub-circuits having the same or equivalent circuit configuration as the original circuit, and first and second sub-circuits forming the two sub-circuits; Each of the two sub-circuits has half the input capacitance of one input terminal forming the differential input terminal pair of the original circuit, and the first and second sub-circuits form the differential input terminal pair of each sub circuit. 2 and the differential output of the original circuit A first output terminal and a second output terminal, each having a half driving capability per one output terminal forming a pair, and a first output terminal and a second output terminal forming a differential output terminal pair of each sub-circuit; The circuit has one differential input terminal pair and one differential output terminal pair provided in common with the circuit, and has a first input terminal of the first sub circuit and the second sub terminal. A second input terminal of the circuit is connected to one input terminal of the differential input terminal pair common to the first and second sub-circuits, and a second input terminal of the first sub-circuit is connected to a second input terminal of the first sub-circuit. A first input terminal of the second sub-circuit is connected to another input terminal of the differential input terminal pair common to the first and second sub-circuits; 1 output terminal and a second output terminal of the second sub-circuit are connected to the differential output terminal pair common to the first and second sub-circuits. A second output terminal of the first sub-circuit and a first output terminal of the second sub-circuit, wherein the second output terminal of the first sub-circuit is connected to a first output terminal of the first sub-circuit. It is configured to be connected to another output terminal of the dynamic output terminal pair.
[0006]
In the present invention, the arrangement of the first sub-circuit and the arrangement of the second sub-circuit, and the wiring between the first sub-circuit and the second sub-circuit may have a mirror-inverted relationship with each other. Is laid out.
[0007]
A design method according to the present invention is a method for designing a semiconductor integrated circuit in which, based on circuit information of a semiconductor circuit, a computer performs layout processing of arrangement and wiring for integration on a semiconductor substrate,
(A) At least two input terminals forming one differential input terminal pair and two output terminals forming one differential output terminal pair, and a signal from the differential input terminal pair is differentially input. Then, circuit information of a circuit (referred to as an “original circuit”) that differentially outputs an output signal from the differential output terminal pair is input from a storage unit, and the original circuit is set to be the same as or equivalent to the original circuit. Replacing with two sub-circuits having a functional circuit configuration, and storing circuit information of the two sub-circuits in storage means,
Each of the first and second sub-circuits forming the two sub-circuits has a half input capacitance per input terminal forming the differential input terminal pair of the original circuit, and each of the sub-circuits has First and second input terminals forming a differential input terminal pair, and a driving capability of half of the output terminals forming the differential output terminal pair of the original circuit, and a differential output terminal pair of each sub-circuit. And a first output terminal and a second output terminal. The first and second sub-circuits each have one differential input terminal pair and one differential output terminal pair. Prepare
(B) circuit information of the first and second sub-circuits is input from the storage unit, and a first input terminal of the first sub-circuit and a second input terminal of the second sub-circuit; To make one input terminal of the differential input terminal pair common to the first and second sub-circuits;
(C) connecting a second input terminal of the first sub-circuit to a first input terminal of the second sub-circuit, and connecting the differential input common to the first and second sub-circuits; Making it another input terminal of the terminal pair;
(D) connecting a first output terminal of the first sub-circuit and a second output terminal of the second sub-circuit to produce a differential output common to the first and second sub-circuits; One output terminal of the terminal pair,
(E) connecting a second output terminal of the first sub-circuit and a first output terminal of the second sub-circuit to form a differential output terminal pair common to the first and second sub-circuits; As another output terminal.
[0008]
In the design method according to the present invention, the arrangement of the first sub-semiconductor circuit and the arrangement of the second sub-semiconductor circuit, and the wiring between the first sub-semiconductor circuit and the second sub-semiconductor circuit, The layout is performed so that they are mirror-inverted with each other.
[0009]
An apparatus according to the present invention is a design automation apparatus that performs layout processing of arrangement and wiring for integration on a semiconductor substrate by a computer based on circuit information of a semiconductor circuit, and includes one differential input terminal pair. And at least two output terminals forming one differential output terminal pair, differentially inputting a signal from the differential input terminal pair and outputting an output signal to the differential output terminal Circuit information of a circuit (referred to as “original circuit”) that differentially outputs from a pair is input from a storage unit, and the original circuit is divided into two sub-circuits having the same or equivalent function as the original circuit. Means for replacing, wherein each of the first and second sub-circuits forming the two sub-circuits has a half input capacitance per input terminal forming the differential input terminal pair of the original circuit. The differential input terminal pairs of each subcircuit. A first and a second input terminal, and a first output terminal forming a differential output terminal pair of each sub-circuit, having half the driving capability of one output terminal forming the differential output terminal pair of the original circuit. And one second output terminal, and one differential input terminal pair and one differential output terminal pair provided in common to the first and second sub-circuits. Connecting a first input terminal of the first sub-circuit and a second input terminal of the second sub-circuit to form a differential input terminal pair common to the first and second sub-circuits. A first input terminal of the first sub-circuit and a first input terminal of the second sub-circuit by connecting the second input terminal of the first sub-circuit to the first input terminal of the second sub-circuit. Means common to the differential input terminal pair as another input terminal, a first output terminal of the first sub-circuit and a second output terminal of the second sub-circuit. A second output terminal of the first sub-circuit, the second output terminal of the first sub-circuit being connected to a second output terminal of the first and second sub-circuits; And a means for connecting the first output terminal of the second sub-circuit to another output terminal of the differential output terminal pair common to the first and second sub-circuits. .
[0010]
A program according to the present invention is a program executed by a computer constituting a design automation apparatus that performs layout processing of arrangement and wiring for integration on a semiconductor substrate based on circuit information of a semiconductor circuit, It has at least two input terminals forming one differential input terminal pair and two output terminals forming one differential output terminal pair, differentially inputs a signal from the differential input terminal pair, and outputs Circuit information of a circuit (referred to as an "original circuit") for differentially outputting a signal from the differential output terminal pair is input from storage means, and the original circuit is replaced with a circuit having the same or equivalent function as the original circuit. A first process of dividing the configuration into two sub-circuits and storing circuit information of the two sub-circuits in a storage unit, wherein each of the first and second sub-circuits forming the two sub-circuits is , The differential of the original circuit A first input terminal and a second input terminal each having a half input capacitance per input terminal forming a pair of input terminals and forming a differential input terminal pair of each sub-circuit; and the differential output terminal of the original circuit. The first and second sub-circuits, each having half the driving capability of the pair of output terminals and having first and second output terminals forming a differential output terminal pair of each sub-circuit. In common, one differential input terminal pair and one differential output terminal pair are prepared, and circuit information of the first and second sub-circuits is input from the storage means. A first input terminal of one sub-circuit is connected to a second input terminal of the second sub-circuit, and one of the differential input terminal pairs common to the first and second sub-circuits is connected. Connecting the second input terminal of the first sub-circuit with the first input terminal of the second sub-circuit as an input terminal; A second processing to be another input terminal of the differential input terminal pair common to the first and second sub-circuits; a first output terminal of the first sub-circuit and the second sub-circuit; And a second output terminal of the differential output terminal pair common to the first and second sub-circuits, and a second output terminal of the first sub-circuit is connected to the second output terminal of the first sub-circuit. Connecting a first output terminal of a second sub-circuit to another output terminal of the differential output terminal pair common to the first and second sub-circuits; The program comprises a program for causing the computer to execute the first to third processes.
[0011]
BEST MODE FOR CARRYING OUT THE INVENTION
An embodiment of the present invention will be described. A semiconductor integrated circuit according to the present invention includes a pair of first and second differential input terminals, and a pair of first and second differential output terminals, and the first and second differential input terminals. A differential circuit that differentially inputs a signal from an input terminal and differentially outputs an output signal from the first and second differential output terminals (also referred to as an “original differential circuit”) (21 in FIG. 1) Is divided into two sub-differential circuits (also referred to as “sub-semiconductor circuits”) (1, 6 in FIG. 2) having a circuit configuration having the same or equivalent function as the semiconductor circuit, and the original differential circuit is , And these two sub differential circuits are replaced.
[0012]
Each of the first and second sub differential circuits forming two sub differential circuits is a first or second differential input terminal forming a differential input terminal pair (22, 23) of the original differential circuit. First and second differential input terminals (2, 3 in FIG. 2) (7, 8) each having a half input capacitance and forming a differential input terminal pair of each sub differential circuit; The first and second differential output terminals forming the differential output terminal pair (24, 25) of the original differential circuit have half the driving capability, and the differential output terminals of each sub differential circuit It has a pair of first and second differential output terminals (4, 5) (9, 10).
[0013]
Further, one differential input terminal pair (11, 12) and one differential output terminal pair (13, 14) are commonly used for the first and second sub differential circuits (1, 6 in FIG. 2). ) Is provided.
[0014]
A first differential input terminal (2) of the first sub differential circuit (1) is connected to a second differential input terminal (8) of the second sub differential circuit (6), One input terminal (11) of a common differential input terminal pair (11, 12) is used for the first and second sub differential circuits, and the second differential circuit of the first sub differential circuit (1) is used. The dynamic input terminal (3) and the first differential input terminal (7) of the second sub differential circuit (6) are connected to provide a common differential for the first and second sub differential circuits. The other input terminal (12) of the dynamic input terminal pair (11, 12), the first differential output terminal (4) of the first sub differential circuit (1) and the second sub differential circuit (6) ) Is connected to the second differential output terminal (10) and one output terminal (13, 14) of the differential output terminal pair (13, 14) common to the first and second sub differential circuits. ) And the first sub differential circuit (1 Is connected to the first differential output terminal (9) of the second sub differential circuit (6) so that the first and second sub differential circuits can be connected to each other. And the other output terminal (14) of the common differential output terminal pair (13, 14).
[0015]
The arrangement of the first sub differential circuit (1) and the arrangement of the second sub differential circuit (6), and between the first sub differential circuit (1) and the second sub differential circuit (6) Are laid out so as to have a mirror-inverted relationship with each other. For example, regarding the broken line in FIG. 2, the arrangement of the circuits, mutual positions, wiring patterns, wiring lengths, and the like are in a mirror-inverted relationship.
[0016]
In the method according to the present invention, the circuit information of the differential circuit after the circuit optimization in the circuit design phase is read from the storage device, and the differential circuit is divided into a plurality of sub differential circuits having the same circuit configuration. The plurality of sub differential circuits have the same circuit configuration (circuit topology) as the original differential circuit, but are reduced in size.
[0017]
Also, the layout is arranged so that each sub-differential circuit and the wiring have a mirror-inverted relationship, and the corresponding terminals of each sub-circuit are connected to each other so as to have the same input capacitance and drive capability as those of the circuit. It is a moving terminal pair.
[0018]
At this time, if the corresponding terminals of the sub-differential circuit pair in a mirror-inverted relationship are connected alternately, the imbalance in characteristics between the differential terminal pairs is canceled, the differential characteristics are improved, and And a differential circuit having the same characteristics as the original differential circuit.
[0019]
In the present invention, the layout processing is performed by a design automation apparatus that performs arrangement and wiring processing for integration on a semiconductor substrate by a computer based on circuit information of a semiconductor circuit.
[0020]
This design automation apparatus has at least two input terminals forming one differential input terminal pair and two output terminals forming one differential output terminal pair, and outputs a signal from the differential input terminal pair. The circuit information of a circuit (referred to as an "original circuit") that receives a differential input and differentially outputs an output signal from the differential output terminal pair is input from a storage unit, and the original circuit is identical to the original circuit. Alternatively, there is provided a means for replacing with two sub-circuits having a circuit configuration having an equivalent function. Each of the first and second sub-circuits forming the two sub-circuits has a half input capacitance per input terminal forming the differential input terminal pair of the original circuit, and each of the sub-circuits has A first input terminal and a second input terminal that form a differential input terminal pair, and a driving capability that is half that of one output terminal that forms the differential output terminal pair of the original circuit; First and second output terminals forming an output terminal pair.
[0021]
One differential input terminal pair and one differential output terminal pair are prepared in common for the divided first and second sub-circuits.
[0022]
A first input terminal of the first sub-circuit and a second input terminal of the second sub-circuit are connected to each other to connect the differential input terminal pair common to the first and second sub-circuits; One input terminal is connected to a second input terminal of the first sub-circuit and a first input terminal of the second sub-circuit, and the common input terminal is connected to the first and second sub-circuits. The first and second sub-circuits are connected to a first output terminal of the first sub-circuit and a second output terminal of the second sub-circuit as another input terminal of the differential input terminal pair. A second output terminal of the first sub-circuit and a first output terminal of the second sub-circuit are connected to one output terminal of the differential output terminal pair common to the sub-circuits; A means for outputting the layout result information to the storage means as another output terminal of the differential output terminal pair common to the first and second sub-circuits; It is equipped with a. Each of the above processes of the design automation apparatus is realized by a program executed by a computer.
[0023]
According to the present invention, in another embodiment, the first sub-circuit (1 in FIG. 2) has N (N is 2 or more) circuit configurations having the same or equivalent function as the first sub-circuit. ) Of the first group (31,... 41 in FIG. 3), and the second sub-circuit (6 in FIG. 2) is the same as or similar to the second sub-circuit. The circuit is replaced with N second group child circuits (36,..., 46 in FIG. 3) having a circuit configuration of an equivalent function, wherein the N first group child circuits and the N , One differential input terminal pair (51, 52 in FIG. 3) and one differential output terminal pair (53, 54 in FIG. 3) which are provided in common to the second group of sub-circuits. Having. Each of the N first-group child circuits is connected to one of the differential input terminal pairs (2, 3 in FIG. 2) of the first sub-circuit (1 in FIG. 2). First and second input terminals (32, 33) having an input capacitance of 1 / N and forming a differential input terminal pair of each child circuit; and the differential output terminal of the first sub-circuit The first and second output terminals (34) having a driving capability of 1 / N for each pair of output terminals (4, 5 in FIG. 2) and forming a differential output terminal pair of each child circuit. , 35). Each of the N second group of child circuits is configured to have N components per one of the differential input terminal pairs (7, 8) of the second sub-circuit (6 in FIG. 2). A first input terminal and a second input terminal (37, 38), each having an input capacitance of 1, and forming a differential input terminal pair of each child circuit; The first and second output terminals (39) each have a driving capability of 1 / N of each output terminal forming a dynamic output terminal pair (9, 10), and form a differential output terminal pair of each child circuit. , 40), and for each of the N child circuits of the first group and the N child circuits of the second group, the child circuits of the first group, The child circuits of the second group corresponding to the child circuits of the group are laid out so as to have a mirror-inverted relationship with each other, and have a mirror-inverted relationship with each other. Regarding the first child circuit and the second child circuit, the first input terminal (33) of the first child circuit and the second input terminal (38) of the second child circuit are connected to each other. Connected to one input terminal of the differential input terminal pair (52, 54) provided in common with the second input terminal (33) of the first child circuit and the second child terminal. The first input terminal (37) of the first child circuit is connected to another input terminal of the differential input terminal pair (52, 54) provided in common. 1 output terminal (34) and the second output terminal (40) of the second child circuit are connected, and one output of the differential output terminal pair (53, 54) provided in common is provided. And a second output terminal (35) of the first child circuit is connected to a first output terminal (39) of the second child circuit. It is, and is connected to the other output terminal of the differential output terminal pair provided commonly (53, 54). Hereinafter, the present invention will be described in detail with reference to specific examples.
[0024]
【Example】
Embodiments of the present invention will be described below in detail with reference to the drawings in order to explain the above-described embodiments of the present invention in further detail. FIG. 1 is a diagram for explaining an embodiment of the present invention. FIG. 1 shows a differential circuit 21 having a pair of differential input terminals 22 and 23 and a pair of differential output terminals 24 and 25. The differential circuit 21 differentially inputs an input signal supplied to the differential input terminal pairs 22 and 23, and outputs differentially from the differential output terminal pairs 24 and 25.
[0025]
FIG. 2 is a diagram for explaining an embodiment of the present invention, and shows an example in which the differential circuit 21 of FIG. 1 is replaced with two sub semiconductor circuits. Referring to FIG. 2, in this embodiment, instead of the differential circuit 21 of FIG. 1, two sub-semiconductor circuits 1 and 6 which are integrated in a semiconductor integrated circuit and form sub-differential circuits respectively are shown in FIG. Each of which has a differential input terminal pair and a differential output terminal pair, and has a mirror-inverted relationship with each other as described later. Are arranged and wired as follows.
[0026]
The input capacitance of each input terminal 2, 3, 7, 8 of each sub semiconductor circuit 1, 6 is one of the first or second input terminals 22, 23 forming a differential input terminal pair of the differential circuit 21. Per input capacity. The driving capability (current driving capability) of each output terminal 4, 5, 9, 10 of each sub-semiconductor circuit 1, 6 is determined by the first or second output terminal 24 forming a differential output terminal pair of the differential circuit 21. , 25 is half of the driving capacity per one of the two.
[0027]
The first and second sub-semiconductor circuits 1 and 6 are laid out in a mirror-inverted relationship with each other. That is, the arrangement of the first and second sub-semiconductor circuits 1 and 6 is symmetric with respect to the broken line in FIG. The arrangement of the first differential input terminal 2 of the first sub-semiconductor circuit 1 and the first differential input terminal 7 of the second sub-semiconductor circuit 6 is symmetrical with respect to the broken line in FIG. The arrangement of the second differential input terminal 3 of the semiconductor circuit 1 and the second differential input terminal 8 of the second sub-semiconductor circuit 6 is symmetric with respect to the broken line in FIG. The arrangement of the first differential output terminal 4 of the first sub-semiconductor circuit 1 and the first differential output terminal 9 of the second sub-semiconductor circuit 6 is symmetric with respect to the broken line in FIG. The arrangement of the second differential output terminal 5 of the semiconductor circuit 1 and the second differential output terminal 10 of the second sub-semiconductor circuit 6 is symmetric with respect to the broken line in FIG. Further, the arrangement of the differential input terminal pairs 11 and 12 and the arrangement of the differential output terminal pairs 13 and 14 provided commonly to the first and second sub-semiconductor circuits 1 and 6 are shown in FIG. It is symmetric with respect to the broken line.
[0028]
By connecting the first differential input terminal 2 of the first sub-semiconductor circuit 1 and the second differential input terminal 8 of the second sub-semiconductor circuit 6, the first and second sub-semiconductor circuits 1 and 6, a first differential input terminal 11 provided in common.
[0029]
Similarly, by connecting the second differential input terminal 3 of the first sub-semiconductor circuit 1 and the first differential input terminal 7 of the second sub-semiconductor circuit 6, the first and second sub-semiconductors are connected. The second differential input terminal 12 is provided commonly to the circuits 1 and 6.
[0030]
The wiring length from the first differential input terminal 2 to the first differential input terminal 11 of the first sub-semiconductor circuit 1 and the wiring length from the second differential input terminal 8 of the second sub-semiconductor circuit 6 to the first Is the sum of the wiring length from the second differential input terminal 3 to the second differential input terminal 12 of the first sub-semiconductor circuit 1 and the second sub-semiconductor. It is equal to the sum of the wiring length from the first differential input terminal 7 to the second differential input terminal 12 of the circuit 6.
[0031]
By connecting the first differential output terminal 4 of the first sub-semiconductor circuit 1 and the second differential output terminal 10 of the second sub-semiconductor circuit 6, the first and second sub-semiconductor circuits 1 and 6, a first differential output terminal 13 provided in common.
[0032]
By connecting the second differential output terminal 5 of the first sub semiconductor circuit 1 and the first differential output terminal 9 of the second sub semiconductor circuit 6, the first and second sub semiconductor circuits 1 and 6, a second differential output terminal 14 provided in common.
[0033]
The wiring length from the first differential output terminal 4 to the first differential output terminal 13 of the first sub-semiconductor circuit 1 and the wiring length from the second differential output terminal 10 of the second sub-semiconductor circuit 6 to the first Of the wiring length from the second differential output terminal 5 to the second differential output terminal 14 of the first sub-semiconductor circuit 1 and the second sub-semiconductor It is equal to the sum of the wiring length from the first differential output terminal 9 of the circuit 6 to the second differential output terminal 14.
[0034]
By arranging and wiring as described above, the differential circuit in FIG. 2 has the same input capacitance and driving capability as the differential circuit 21 in FIG. 1, and can cancel the imbalance in the characteristics between the differential terminal pairs.
[0035]
For example, the input capacitance of the first differential input terminal 11 in FIG. 2 is the sum of the input capacitances of the first differential input terminal 2 of the sub semiconductor circuit 1 and the second differential input terminal 8 of the sub semiconductor circuit 6. , The input capacitance of the second differential input terminal 12 is the sum of the input capacitances of the second differential input terminal 3 of the sub semiconductor circuit 1 and the first differential input terminal 7 of the sub semiconductor circuit 6. Therefore, in the differential circuit 21 of FIG. 1, for example, even if the input capacitance of the first differential input terminal 22 is larger than the input capacitance of the second differential input terminal 23, The input capacitance of the differential input terminal 11 and the input capacitance of the second differential input terminal 12 are equal. That is, the variation in input capacitance between the differential input terminal pairs of the original circuit is balanced in the configuration of the differential input terminal pairs 11 and 12 in FIG. The equal sum of the lengths of the wires cross-connected from the differential input terminal pairs of each sub-semiconductor circuit to the common differential input terminal pairs 11 and 12 also contributes to the balance of the characteristics of the differential input terminal pairs 11 and 12. are doing.
[0036]
The driving capability of the first differential output terminal 11 of FIG. 2 is the sum of the driving capabilities of the first differential output terminal 4 of the sub semiconductor circuit 1 and the second differential input terminal 10 of the sub semiconductor circuit 6, and The driving capability of the second differential output terminal 14 is the sum of the driving capabilities of the second differential output terminal 5 of the sub-semiconductor circuit 1 and the first differential output terminal 9 of the sub-semiconductor circuit 6. Therefore, even if the first differential output terminal and the second differential output terminals 24 and 25 have different driving capabilities in the differential circuit 21 of FIG. The driving capabilities of the second differential output terminals 14 become equal. That is, the driving capabilities of the differential output terminal pairs 13 and 14 in FIG. 2 are balanced. The equal sum of the lengths of the wirings cross-connected from the differential output terminal pairs of each sub-semiconductor circuit to the common differential output terminal pairs 13 and 14 also contributes to the balance of the characteristics of the differential input terminal pairs 13 and 14. are doing.
[0037]
For example, when the sub-semiconductor circuit 1 (6) includes a differential input stage (not shown) including a MOS transistor, the gate capacitance (for example, the gate capacitance connected to the differential input terminal pair 2, 3 (7, 8), respectively) (Gate width) is set to half the gate capacitance of the MOS differential input stage connected to the differential input terminal pair 22, 23 of the differential circuit 21. In the sub-semiconductor circuit 1 (6) in which the driving capability of the output terminal is half that of the differential circuit 21, a MOS transistor in an output stage (not shown) connected to each of the output terminals 4, 5 (9, 10). Gain coefficient β (β = (με / t OX ) (W / L), where μ is the carrier mobility, ε is the dielectric constant of the gate insulating film, t OX Is the film thickness of the gate insulating film, W is the channel width, and L is the channel length) is the gain coefficient β of the MOS transistor in the output stage connected to each of the differential output terminal pairs 24 and 25 of the differential circuit 21. It may be half.
[0038]
In an information processing apparatus such as a computer that inputs circuit information of the differential circuit 21 of FIG. 1 from a communication medium such as a magnetic disk, a semiconductor memory, or a network, the information shown in FIG. The two sub differential circuits 1 and 6 are generated, the circuit information of the two sub differential circuits 1 and 6 is stored in a memory, and displayed on a display device by graphics or the like as necessary, and the two sub differential circuits 1 and 6 are further displayed. The differential circuits 1 and 6 are arranged so as to be mirror-inverted to each other, and the differential input terminal pairs 2, 3 and 7, 8 of the two sub differential circuits 1 and 6 have a common differential input terminal pair 11 and The wiring connection to 12 and the wiring connection to the common differential output terminal pairs 13 and 14 of the differential output terminal pairs 4, 5, 9 and 10 of the two sub differential circuits 1 and 6 are performed by a computer. Is also good.
[0039]
FIG. 3 shows the configuration of the second embodiment of the present invention. Referring to FIG. 3, in this embodiment, the configuration is the same as that of the differential circuit 21 of FIG. 1, and the 2N child semiconductor circuits 31, 36,... The layout is arranged. The input capacity of one input terminal of the differential input terminal pair and the drive capability of one output terminal of the differential output terminal pair of the child semiconductor circuits 31, 36,. One input terminal of the differential input terminal pair and 1 / N (N is a positive integer) one output terminal of the differential output terminal pair of the differential circuit 21 of FIG. Positive integer).
[0040]
The configuration shown in FIG. 3 is configured by replacing the first sub-semiconductor circuit 1 in FIG. 2 with N first-group sub-semiconductor circuits 31,... 41 having the same circuit configuration as the first sub-semiconductor circuit. Then, the second sub-semiconductor circuit 6 in FIG. 2 is replaced with N second-group sub-semiconductor circuits 36,... 46 having the same circuit configuration as the second sub-semiconductor circuit.
[0041]
The N first-group sub-semiconductor circuits have an input capacitance of 1 / N of the first or second differential input terminal (2 or 3) of the first sub-semiconductor circuit, and form a pair of the first and second differential input terminals. 1 and second differential input terminals (32, 33) (42, 43) and 1 / N of the first or second differential output terminal (4 or 5) of the first sub-semiconductor circuit 1 , And a pair of first and second differential output terminals (34, 35)... (44, 45).
[0042]
The N second group of sub-semiconductor circuits 36,..., 46 have 1 / N input capacitance of the first or second differential input terminal 7 or 8 of the second sub-semiconductor circuit 6, and , (47, 48), and the first or second differential output terminal of the second sub-semiconductor circuit. It has a driving capability of 1 / N of 9 or 10, and has a pair of first and second differential output terminals (39, 40) ... (49, 50). The 2N child semiconductor circuits are laid out in a mirror-inverted relationship.
[0043]
For each of the first and second sub-semiconductor circuits having a mirror-inverted relationship with each other and forming a pair, for example, the first differential input terminal 32 of the first sub-semiconductor circuit 31 and the second sub-semiconductor The second differential input terminal 38 of the circuit 36 is connected to the common first differential input terminal 51, and the second differential input terminal 32 of the first child semiconductor circuit 31 is connected to the second differential input terminal 32. The first differential input terminal 37 of the first sub-semiconductor circuit 31 is connected to the first differential input terminal 37 of the first sub-semiconductor circuit 31 to be connected to the common second differential input terminal 52. And the second differential output terminal 40 of the second sub-semiconductor circuit 36, and connected to the common first differential output terminal 53, and the second differential output terminal of the first sub-semiconductor circuit 31. The output terminal 35 is connected to the first differential output terminal 39 of the second sub-semiconductor circuit 36 to form a common first differential output terminal. It is connected to the 54. The same applies to the other pairs of the first and second sub-semiconductor circuits that have a mirror-inverted relationship.
[0044]
In order to cancel the imbalance of the characteristics between the differential terminal pairs of the sub-semiconductor circuits, the differential terminal pairs of the respective sub-semiconductor circuit pairs forming a mirror-reversal relationship and forming a pair are cross-connected to each other, and Have been. That is, as described above, the first group of first sub-semiconductor circuits 31 and the second group of second sub-semiconductor circuits 36 to the first group of N-th sub-semiconductor circuits 41 are paired in a mirror-inverted relationship. , The first differential input terminal 32 of the child semiconductor circuit 31 and the second differential input terminal 38 of the child semiconductor circuit 36 are cross-connected in the Nth child semiconductor circuit 46 of the second group. The first differential input terminal 41 and the second differential input terminal 48 of the child semiconductor circuit 46 are cross-connected to form a common differential input terminal 51, and the second differential input terminal 51 of the child semiconductor circuit 31 The dynamic input terminal 33 and the first differential input terminal 37 of the child semiconductor circuit 36 are cross-connected,..., The second differential input terminal 43 of the child semiconductor circuit 41 and the first differential input of the child semiconductor circuit 46. The terminals 47 are cross-connected to form a common differential input terminal 53. Output terminals of the first group of first sub-semiconductor circuits 31 and the second group of second sub-semiconductor circuits 36 to the first group of N-th sub-semiconductor circuits 41 and the second group of N-th sub-semiconductor circuits 46 The same applies to the output terminal pairs 53 and 54 that are common to the pair.
[0045]
FIG. 4 is a diagram showing a configuration of a differential circuit 69 having a multi-differential input terminal pair and a multi-differential output terminal pair (A differential input terminal pair and B differential output terminal pair). For example, a first differential input terminal pair is a first differential input terminal 61 and a second differential input terminal 62, and an A-th (A is a natural number) differential input terminal pair is a first differential input terminal pair. It comprises an input terminal 63 and a second differential input terminal 64. The first differential output terminal pair includes a first differential output terminal 65 and a second differential output terminal 66, and the B-th (B is a natural number) differential output terminal pair includes a first differential output terminal. 67 and a second differential input terminal 68.
[0046]
FIG. 5 is a diagram showing the configuration of the third embodiment of the present invention. Referring to FIG. 5, this embodiment has the same circuit configuration as the differential circuit 69 shown in FIG. 4, and the input capacitance of the differential input terminal pair and the capacitance of the differential output terminal pair are the same as those of the differential circuit 69. .. 89, 1 / N (where N is a predetermined positive integer) of each of the differential input terminal and the differential output terminal, and N second semiconductor circuits 71,. 98 is obtained by replacing the differential circuit 69 shown in FIG. Each of the N first group of sub-semiconductor circuits 71,... 89 and the N second group of sub-semiconductor circuits 80,. At this time, a pair of child semiconductor circuits (for example, the first child semiconductor circuit 71 of the first group and the first child semiconductor circuit 80 of the second group, or the Nth In order to cancel the imbalance in the characteristics between the differential terminal pairs of the sub-semiconductor circuit 89 and the N-th sub-semiconductor circuit 98 of the second group, the terminals of the sub-semiconductor circuits having a mirror-inverted relationship are alternated. Connect to make a differential terminal.
[0047]
For example, the first differential input terminal 72 of the first differential input terminal pair of the first sub-semiconductor circuit 71 of the first group and the first differential input terminal 72 of the first sub-semiconductor circuit 80 of the second group. The second differential input terminal 82 of the input terminal pair is cross-connected to the first differential input terminal 90 of the first differential input terminal pair of the first group of Nth sub-semiconductor circuits 89. , The first differential input terminal pair of the Nth sub-semiconductor circuit 98 of the second group are cross-connected to the second differential input terminal 100 to form a first differential input terminal pair of the first differential terminal pair. The input terminal 107 is used. Also, the second differential input terminal 73 of the first differential input terminal pair of the first group of first child semiconductor circuits 71 and the first differential input of the second group of first sub-semiconductor circuits 80 Cross-connect the first differential input terminal 81 of the terminal pair,..., The second differential input terminal 91 of the first differential input terminal pair of the first group of Nth sub-semiconductor circuits 89; The first differential input terminal pair of the first differential input terminal pair of the Nth sub-semiconductor circuit 98 of the second group is cross-connected to the second differential input terminal of the first differential terminal pair. The terminal 108 is used.
[0048]
A specific example of the differential circuit will be described. Referring to FIG. 6, in this differential circuit, the source is commonly connected to the drain of a current source transistor 205 whose source is grounded, and the gates are connected to differential input terminals 206 and 207 to form a differential pair. This is a resistive load type CML (current mode logic) inverter circuit including N-channel MOS transistors 203 and 204 and resistive loads 201 and 202 connected between the drains of the N-channel MOS transistors 203 and 204 and the power supply VDD. The drains of the MOS transistors 203 and 204 are connected to differential output terminals 208 and 209.
[0049]
FIG. 7 shows a fourth embodiment of the present invention. The differential pair transistors 203 and 204 and the gate width (W) of the current source transistor 205 of the resistive load type CML inverter circuit shown in FIG. The size is halved, the resistance value of the load resistor is halved, the circuit is divided into two sub-CML inverter circuits, and their terminals are connected alternately. Referring to FIG. 7, the source of the current source transistor 309 whose source is grounded, the source is commonly connected, and the gates are connected to the differential input terminals 311 and 312, respectively, to form a differential pair of N-channel MOS transistors 305 and 305. 306, a first sub-CML inverter circuit having resistive loads 301 and 302 connected between the drains of the N-channel MOS transistors 305 and 306 and the power supply VDD, and a drain of the current source transistor 310 whose source is grounded. Sources are commonly connected, and gates are connected to differential input terminals 313 and 314, respectively, to form differential pairs of N-channel MOS transistors 307 and 308, and connected between the drains of the N-channel MOS transistors 307 and 308 and the power supply VDD. Second with resistive loads 303 and 304 And a first differential input terminal 319 of the common differential input terminal pair, the first differential input terminal 311 of the first sub CML inverter circuit and the second sub CML inverter circuit. The second differential input terminal 320 of the first sub-CML inverter circuit is connected to the second differential input terminal 314 of the first sub-CML inverter circuit. And a first differential input terminal 313 of the second sub-CML inverter circuit. Also, the first differential output terminal 321 of the common differential output terminal pair is connected to the first differential output terminal 315 of the first sub-CML inverter circuit and the second differential output terminal 315 of the second sub-CML inverter circuit. The second differential output terminal 322 of the common differential output terminal pair is connected to the output terminal 318, and the second differential output terminal 316 and the second sub CML inverter of the first sub CML inverter circuit. It is connected to the first differential output terminal 317 of the circuit.
[0050]
In the circuit shown in FIG. The bias terminals 323 and 324 of the current source transistors 309 and 310 are connected to supply a common bias voltage to drive the differential pairs of the first and second sub-CML circuits, respectively. With such a configuration, it has the same input capacity and driving ability as the resistive load type CML inverter circuit of FIG. 6, and can cancel the imbalance in the characteristics between the differential terminals.
[0051]
FIG. 8 is a diagram showing an example of a layout of the circuit shown in FIG. A first sub-CML circuit including load resistors 401 and 402, input transistor pairs 407 and 408 forming a differential pair, and a current source transistor 405; load resistors 403 and 404; an input transistor pair forming a differential pair A second sub-CML inverter circuit including transistors 409 and 410 and a current source transistor 406 is arranged so as to have a mirror-inverted relationship. As described above, regarding the differential input terminal pairs of the two sub-CML inverter circuits, the first differential input terminal of the first sub-CML inverter circuit and the second differential input terminal of the second sub-CML inverter circuit Are cross-connected, the second differential input terminal of the first sub-CML inverter circuit and the first differential input terminal of the second sub-CML inverter circuit are cross-connected, and the difference between the two sub-CML inverter circuits is The dynamic output terminal pairs are similarly cross-connected.
[0052]
Although the present invention has been described with reference to the above embodiments, the present invention is not limited only to the configuration of the above embodiments, and a person skilled in the art within the scope of the claims set forth in the claims. Needless to say, various changes and modifications that could be made are included.
[0053]
【The invention's effect】
As described above, according to the present invention, it is possible to cancel the unbalance of the characteristics between the differential terminal pairs while maintaining the characteristics such as the input capacitance and the driving capability, and to easily improve the differential characteristics. It has the effect of being able to do it.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating an example of a configuration of a differential circuit.
FIG. 2 is a diagram illustrating an example of a circuit configuration according to the first embodiment of the present invention.
FIG. 3 is a diagram illustrating an example of a circuit configuration according to a second embodiment of the present invention.
FIG. 4 is a diagram illustrating an example of a differential circuit having a multi-differential input terminal pair and a multi-differential output terminal pair.
FIG. 5 is a diagram illustrating an example of a circuit configuration according to a third embodiment of the present invention.
FIG. 6 is a diagram illustrating an example of a resistive load type CML inverter circuit.
FIG. 7 is a diagram illustrating an example of a circuit configuration according to a fourth embodiment of the present invention.
FIG. 8 is a diagram showing an example of a layout showing a fourth embodiment of the present invention.
[Explanation of symbols]
21 Differential circuit
22 First differential input terminal
23 Second differential input terminal
24 1st differential output terminal
25 Second differential output terminal
1 First sub-semiconductor circuit
2 First differential input terminal
3 Second differential input terminal
4. First differential output terminal
5 Second differential output terminal
6. Second sub-semiconductor circuit
7 First differential input terminal
8 Second differential input terminal
9 First differential output terminal
10 Second differential output terminal
11 1st differential input terminal
12 Second differential input terminal
13 First differential output terminal
14 Second differential output terminal
31 First Sub-Semiconductor Circuit of First Group
32 first differential input terminal
33. 2nd differential input terminal
34 first differential output terminal
35 Second differential output terminal
36 Second group of second sub-semiconductor circuits
37 First differential input terminal
38 Second differential input terminal
39 first differential output terminal
40 Second differential output terminal
41 First Group Nth Sub-Semiconductor Circuit
42 first differential input terminal
43 Second differential input terminal
44 First differential output terminal
45 Second differential output terminal
46 Second Group Nth Sub-Semiconductor Circuit
47 first differential input terminal
48 second differential input terminal
49 first differential output terminal
50 Second differential output terminal
51 first differential input terminal
52 Second differential input terminal
53 first differential output terminal
54 Second differential output terminal
61 first differential input terminal
62 second differential input terminal
63 first differential input terminal
64 second differential input terminal
65 First differential output terminal
66 Second differential output terminal
67 First differential output terminal
68 second differential output terminal
69 differential circuit
71 First group of first sub-semiconductor circuits
72 First differential input terminal of first differential input terminal pair
73 Second differential input terminal of first differential input terminal pair
74 First differential input terminal of A-th differential input terminal pair
75 Second differential input terminal of A-th differential input terminal pair
76 First differential output terminal of first differential output terminal pair
77 Second differential output terminal of first differential output terminal pair
78 First differential output terminal of B-th differential output terminal pair
79 Second differential output terminal of B-th differential output terminal pair
80 Second group of first sub-semiconductor circuits
81 First differential input terminal of first differential input terminal pair
82 Second differential input terminal of first differential input terminal pair
83 First differential input terminal of A-th differential input terminal pair
84 Second differential input terminal of A-th differential input terminal pair
85 First differential output terminal of first differential output terminal pair
86 a second differential output terminal of the first differential output terminal pair
87 First differential output terminal of B-th differential output terminal pair
88 Second differential output terminal of B-th differential output terminal pair
89 First Group Nth Sub-Semiconductor Circuit
90 first differential input terminal of first differential input terminal pair
91 second differential input terminal of first differential input terminal pair
92 First differential input terminal of A-th differential input terminal pair
93 Second differential input terminal of A-th differential input terminal pair
94 first differential output terminal of first differential output terminal pair
95 Second differential output terminal of first differential output terminal pair
96 First differential output terminal of B-th differential output terminal pair
97 Second differential output terminal of B-th differential output terminal pair
98 Second Group Nth Sub-Semiconductor Circuit
99 first differential input terminal of first differential input terminal pair
100 second differential input terminal of first differential input terminal pair
101 first differential input terminal of A-th differential input terminal pair
102 Second differential input terminal of A-th differential input terminal pair
103 First differential output terminal of first differential output terminal pair
104 second differential output terminal of first differential output terminal pair
105 first differential output terminal of B-th differential output terminal pair
106 second differential output terminal of B-th differential output terminal pair
107 First differential input terminal of first differential input terminal pair
108 second differential input terminal of first differential input terminal pair
109 first differential output terminal of first differential output terminal pair
110 second differential output terminal of first differential output terminal pair
201 First resistance
202 Second resistance
203 First input transistor
204 second input transistor
205 Transistor for current source
206 first differential input terminal
207 second differential input terminal
208 first differential output terminal
209 second differential output terminal
210 Bias terminal of transistor for current source
301 First resistance of first sub-circuit
302 Second resistance of first sub-circuit
303 First resistance of second sub-circuit
304 second resistance of second sub-circuit
305 First input transistor of first sub-circuit
306 second input transistor of first sub-circuit
307 First input transistor of second sub-circuit
308 second input transistor of second sub-circuit
309 Current source transistor of first sub-circuit
310 Current source transistor of second sub-circuit
311 First differential input terminal of first sub-circuit
312 Second differential input terminal of first sub-circuit
313 first differential input terminal of second sub-circuit
314 second differential input terminal of second sub-circuit
315 first differential output terminal of first sub-circuit
316 second differential output terminal of first sub-circuit
317 First differential output terminal of second sub-circuit
318 second differential output terminal of second sub-circuit
319 first differential input terminal
320 second differential input terminal
321 first differential output terminal
322 second differential output terminal
323 Bias terminal of current source transistor of first sub-circuit
324 Bias terminal of current source transistor of second sub-circuit
401 first resistance of first sub-circuit
402 Second resistor of first sub-circuit
403 First resistance of second sub-circuit
404 Second resistance of second sub-circuit
405 Transistor for current source of first sub-circuit
406 Transistor for current source of second sub-circuit
407 First input transistor of first sub-circuit
408 Second input transistor of first sub-circuit
409 First input transistor of second sub-circuit
410 second input transistor of second sub-circuit

Claims (14)

１つの差動入力端子対をなす２つの入力端子と、１つの差動出力端子対をなす２つの出力端子とを少なくとも含み、前記差動入力端子対から入力信号を差動入力し、出力信号を前記差動出力端子対から差動出力する回路（「元の回路」という）が、同一のチップ上に集積化される回路群の少なくとも１つとなる半導体集積回路であって、
前記元の回路の代わりに、前記元の回路と同一又は等価な機能の回路構成の２つのサブ回路を備えており、
前記２つのサブ回路をなす第１及び第２のサブ回路のそれぞれが、
前記元の回路の前記差動入力端子対をなす入力端子１つあたりの半分の入力容量を有し、各サブ回路の差動入力端子対をなす第１及び第２の入力端子と、
前記元の回路の前記差動出力端子対をなす出力端子１つあたりの半分の駆動能力を有し、各サブ回路の差動出力端子対をなす第１及び第２の出力端子と、
を有し、
前記第１及び第２のサブ回路に対して、共通に設けられている、１つの差動入力端子対と１つの差動出力端子対とを有し、
前記第１のサブ回路の第１の入力端子と前記第２のサブ回路の第２の入力端子とが、前記第１及び第２のサブ回路に共通の前記差動入力端子対の１つの入力端子に接続され、
前記第１のサブ回路の第２の入力端子と前記第２のサブ回路の第１の入力端子とが、前記第１及び第２のサブ回路に共通の前記差動入力端子対の他の入力端子に接続され、
前記第１のサブ回路の第１の出力端子と前記第２のサブ回路の第２の出力端子とが、前記第１及び第２のサブ回路に共通の前記差動出力端子対の１つの出力端子に接続され、
前記第１のサブ回路の第２の出力端子と前記第２のサブ回路の第１の出力端子とが、前記第１及び第２のサブ回路に共通の前記差動出力端子対の他の出力端子に接続されてなる、ことを特徴とする半導体集積回路。An input signal that includes at least two input terminals that form one differential input terminal pair and two output terminals that form one differential output terminal pair; A circuit (hereinafter referred to as an “original circuit”) that differentially outputs from the differential output terminal pair is at least one of a group of circuits integrated on the same chip,
In place of the original circuit, there are provided two sub-circuits having the same or equivalent circuit configuration as the original circuit,
Each of the first and second sub-circuits forming the two sub-circuits is
First and second input terminals having a half input capacitance per input terminal forming the differential input terminal pair of the original circuit, and forming a differential input terminal pair of each sub-circuit;
A first and a second output terminal having a half driving capability per output terminal forming the differential output terminal pair of the original circuit, and forming a differential output terminal pair of each sub-circuit;
Has,
It has one differential input terminal pair and one differential output terminal pair provided in common for the first and second sub-circuits,
A first input terminal of the first sub-circuit and a second input terminal of the second sub-circuit are connected to one input of the differential input terminal pair common to the first and second sub-circuits. Connected to the terminal,
A second input terminal of the first sub-circuit and a first input terminal of the second sub-circuit are connected to another input of the differential input terminal pair common to the first and second sub-circuits. Connected to the terminal,
A first output terminal of the first sub-circuit and a second output terminal of the second sub-circuit are connected to one output of the differential output terminal pair common to the first and second sub-circuits. Connected to the terminal,
A second output terminal of the first sub-circuit and a first output terminal of the second sub-circuit are connected to another output of the differential output terminal pair common to the first and second sub-circuits. A semiconductor integrated circuit connected to a terminal. 前記第１のサブ回路の配置と前記第２のサブ回路の配置、及び、前記第１のサブ回路と前記第２のサブ回路との間の配線が、互いに鏡面反転の関係になるように、配置及び配線されている、ことを特徴とする請求項１記載の半導体集積回路。The arrangement of the first sub-circuit and the arrangement of the second sub-circuit, and the wiring between the first sub-circuit and the second sub-circuit are mirror-inverted with each other. 2. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is arranged and wired. １つの差動入力端子対をなす２つの入力端子と、１つの差動出力端子対をなす２つの出力端子とを少なくとも有し、前記差動入力端子対からの信号を差動入力し、出力信号を前記差動出力端子対から差動出力する回路（「元の回路」という）が、同一のチップ上に集積化される回路群の少なくとも１つとなる半導体集積回路であって、
前記元の回路は、前記元の回路と同一又は等価な回路構成の２つのサブ回路に置き換えられ、
前記２つのサブ回路をなす第１及び第２のサブ回路のそれぞれは、
前記元の回路の前記差動入力端子対をなす入力端子１つあたりの半分の入力容量を有し、各サブ回路の差動入力端子対をなす第１及び第２の入力端子と、
前記元の回路の前記差動出力端子対をなす出力端子１つあたりの半分の駆動能力を有し、各サブ回路の差動出力端子対をなす第１及び第２の出力端子を有し、さらに、前記第１のサブ回路は、前記第１のサブ回路と同一又は等価な機能の回路構成のＮ個（Ｎは２以上の整数）の第１群の子の回路で置き換えられて構成され、
前記第２のサブ回路は、前記第２のサブ回路と同一又は等価な機能の回路構成のＮ個の第２群の子の回路で置き換えられて構成されており、
前記Ｎ個の第１群の子の回路と前記Ｎ個の第２群の子の回路に対して、共通に設けられている、１つの差動入力端子対と１つの差動出力端子対とを有し、
前記Ｎ個の第１群の子の回路のそれぞれは、
前記第１のサブ回路の前記差動入力端子対をなす入力端子１つあたりのＮ分の１の入力容量を有し、各子の回路の差動入力端子対をなす第１及び第２の入力端子と、
前記第１のサブ回路の前記差動出力端子対をなす出力端子１つあたりのＮ分の１の駆動能力を有し、各子の回路の差動出力端対をなす第１及び第２の出力端子と、
を有し、
前記Ｎ個の第２群の子の回路のそれぞれは、
前記第２のサブ回路の前記差動入力端子対をなす入力端子１つあたりのＮ分の１の入力容量を有し、各子の回路の差動入力端子対をなす第１及び第２の入力端子と第２の入力端子と、
前記第２のサブ回路の前記差動出力端子対をなす出力端子１つあたりのＮ分の１の駆動能力を有し、各子の回路の差動出力端子対をなす第１及び第２の出力端子と、
を有し、
Ｎ個の前記第１群の子の回路とＮ個の前記第２群の子の回路とのそれぞれについて、
前記第１群の子の回路と、前記第１群の子の回路に対応する前記第２群の子の回路とは、互いに鏡面反転の関係になるように、レイアウトされており、
互いに鏡面反転の関係にあり対をなす第１の子の回路と第２の子の回路について、
前記第１の子の回路の第１の入力端子と前記第２の子の回路の第２の入力端子とが、共通に設けられた前記差動入力端子対の１つの入力端子に接続され、
前記第１の子の回路の第２の入力端子と前記第２の子の回路の第１の入力端子とが、共通に設けられた前記差動入力端子対の他の入力端子に接続され、
前記第１の子の回路の第１の出力端子と前記第２の子の回路の第２の出力端子とが、前記共通に設けられた前記差動出力端子対の１つの出力端子に接続され、
前記第１の子の回路の第２の出力端子と前記第２の子の回路の第１の出力端子とが、共通に設けられた前記差動出力端子対の他の出力端子に接続されている、ことを特徴とする半導体集積回路。It has at least two input terminals forming one differential input terminal pair and two output terminals forming one differential output terminal pair, differentially inputs a signal from the differential input terminal pair, and outputs A semiconductor integrated circuit in which a circuit that outputs signals differentially from the differential output terminal pair (referred to as an “original circuit”) is at least one of a group of circuits integrated on the same chip,
The original circuit is replaced with two sub-circuits having the same or equivalent circuit configuration as the original circuit,
Each of the first and second sub-circuits forming the two sub-circuits includes:
First and second input terminals having a half input capacitance per input terminal forming the differential input terminal pair of the original circuit, and forming a differential input terminal pair of each sub-circuit;
The first circuit has half the driving capability per output terminal forming the differential output terminal pair of the original circuit, and has first and second output terminals forming a differential output terminal pair of each sub-circuit; Further, the first sub-circuit is configured to be replaced by N (N is an integer of 2 or more) first-group child circuits having a circuit configuration having the same or equivalent function as the first sub-circuit. ,
The second sub-circuit is configured to be replaced with N second-group child circuits having a circuit configuration having the same or equivalent function as the second sub-circuit,
One differential input terminal pair and one differential output terminal pair provided in common for the N first group child circuits and the N second group child circuits. Has,
Each of the N first group child circuits comprises:
The first and second sub-circuits each have an input capacitance of 1 / N of one input terminal forming the differential input terminal pair, and include first and second input capacitances forming a differential input terminal pair of each child circuit. An input terminal,
The first and second sub-circuits have a driving capability of 1 / N per one output terminal forming the differential output terminal pair, and the first and second sub-circuits constitute a differential output terminal pair of each child circuit. An output terminal,
Has,
Each of the N second group child circuits comprises:
The first and second sub-circuits each have a 1 / N input capacitance per input terminal forming the differential input terminal pair, and constitute a differential input terminal pair of each child circuit. An input terminal, a second input terminal,
The first and second sub-circuits each have a driving capability of 1 / N of one output terminal forming the differential output terminal pair, and form a differential output terminal pair of each child circuit. An output terminal,
Has,
For each of the N child circuits of the first group and the N child circuits of the second group,
The first group of child circuits and the second group of child circuits corresponding to the first group of child circuits are laid out in a mirror-inverted relationship to each other,
Regarding a first child circuit and a second child circuit that are mirror-inverted to each other and form a pair,
A first input terminal of the first child circuit and a second input terminal of the second child circuit are connected to one input terminal of the differential input terminal pair provided in common;
A second input terminal of the first child circuit and a first input terminal of the second child circuit are connected to another input terminal of the differential input terminal pair provided in common;
A first output terminal of the first child circuit and a second output terminal of the second child circuit are connected to one output terminal of the differential output terminal pair provided in common. ,
A second output terminal of the first child circuit and a first output terminal of the second child circuit are connected to another output terminal of the differential output terminal pair provided in common. A semiconductor integrated circuit. 第１及び第２の入力端子からなる差動入力端子対をＡ組（ただし、Ａは所定の正整数）備え、第１及び第２の出力端子からなる差動出力端子対をＢ組（ただし、Ｂは所定の正整数）備え、
それぞれの組の差動入力端子対から信号を差動入力し、出力信号を対応する差動出力対より差動出力する回路（「元の回路」という）が、同一のチップ上に集積化される回路群の少なくとも１つとなる半導体集積回路であって、
前記元の回路は、前記元の回路と同一又は等価な機能の回路構成の、２つのサブ回路で置き換えられ、
前記２つのサブ回路をなす第１及び第２のサブ回路のそれぞれは、
前記元の回路の前記差動入力端子対をなす入力端子１つあたりの半分の入力容量を有する第１及び第２の入力端子よりなる差動入力端子対をＡ組備え、
前記元の回路の前記差動出力端子対をなす入力端子１つあたりの半分の駆動能力を有する第１及び第２の出力端子よりなる差動出力端子対をＢ組有し、
前記第１のサブ回路は、前記第１のサブ回路と同一又は等価な機能の回路構成のＮ（ただし、Ｎは２以上の所定の整数）個の第１群の子の回路で置き換えられて構成されており、
前記第２のサブ回路は、前記第２のサブ回路と同一又は等価な機能の回路構成のＮ個の第２群の子の回路で置き換えられて構成されており、
前記Ｎ個の第１群の子の回路のそれぞれは、
前記第１のサブ回路の前記差動出力端子対の入力端子１つあたりのＮ分の１の入力容量を有する第１及び第２の入力端子よりなる差動入力端子対をＡ組有し、
前記第１のサブ回路の前記差動出力端子対をなす入力端子１つあたりのＮ分の１の駆動能力を有する第１及び第２の出力端子よりなる差動出力端子対をＢ組有し、
前記Ｎ個の第２群の子の回路のそれぞれは、
前記第２のサブ回路の前記差動出力端子対をなす入力端子１つあたりのＮ分の１の入力容量を有する第１及び第２の入力端子よりなる差動入力端子対をＡ組有し、
前記第２のサブ回路の前記差動出力端子対をなす差動入力端子１つあたりのＮ分の１の駆動能力を有する第１及び第２の出力端子よりなる差動出力端子対をＢ組有し、
Ｎ個の前記第１群の子の回路とＮ個の前記第２群の子の回路とのそれぞれについて、
前記第１群の子の回路と前記第１群の子の回路に対応する前記第２群の子の回路とは、互いに鏡面反転の関係になるように、レイアウトされており、
互いに鏡面反転の関係にあり対をなす第１の子の回路と第２の子の回路のＡ組の差動入力端子対のそれぞれについて、
前記第１の子の回路の第ｉ（ただし、ｉは１以上Ａ以下の整数）組の差動入力端子対の第１の入力端子と、前記第２の子の回路の第ｉ組の差動入力端子対の第２の入力端子とが、前記元の回路に対応して、共通に設けられた第ｉ組の差動入力端子対の１つの入力端子に接続され、
前記第１の子の回路の第ｉ組の差動入力端子対の第２の入力端子と前記第２の子の回路の第ｉ組の差動入力端子対の第１の入力端子とが、前記元の回路に対応して、共通に設けられた第ｉ組の差動入力端子対の前記差動入力端子対の他の入力端子に接続され、
互いに鏡面反転の関係にあり対をなす前記第１の子の回路と前記第２の子の回路のＢ組の差動出力端子対のそれぞれについて、
前記第１の子の回路の第ｊ（ただし、ｊは１以上Ｂ以下の整数）組の差動出力端子対の第１の出力端子と、前記第２の子の回路の第ｊ組の差動出力端子対の第２の出力端子とが、前記元の回路に対応して、共通に設けられた第ｊ組の差動出力端子対の１つの出力端子に接続され、
前記第１の子の回路の第ｊ組の差動出力端子対の第２の出力端子と、前記第２の子の回路の第ｊ組の差動出力端子対の第１の出力端子とが、前記元の回路に対応して共通に設けられた、第ｊ組の差動出力端子対の前記差動出力端子対の他の出力端子に接続されてなる、ことを特徴とする半導体集積回路。A set of differential input terminal pairs comprising first and second input terminals (where A is a predetermined positive integer) is provided, and B pairs of differential output terminal pairs comprising first and second output terminals are provided (where , B are predetermined positive integers),
Circuits that input signals differentially from each pair of differential input terminals and output differential output signals from the corresponding differential output pairs (referred to as “original circuits”) are integrated on the same chip. A semiconductor integrated circuit that is at least one of a group of circuits,
The original circuit is replaced by two sub-circuits having the same or equivalent circuit configuration as the original circuit,
Each of the first and second sub-circuits forming the two sub-circuits includes:
A pair of differential input terminal comprising first and second input terminals each having a half input capacitance per input terminal forming the differential input terminal pair of the original circuit,
B sets of differential output terminal pairs comprising first and second output terminals having half the driving capability per input terminal forming the differential output terminal pair of the original circuit,
The first sub-circuit is replaced by N (here, N is a predetermined integer of 2 or more) first group child circuits having a circuit configuration having the same or equivalent function as the first sub-circuit. Is composed of
The second sub-circuit is configured to be replaced with N second-group child circuits having a circuit configuration having the same or equivalent function as the second sub-circuit,
Each of the N first group child circuits comprises:
A set of a differential input terminal pair including first and second input terminals having an input capacitance of 1 / N per input terminal of the differential output terminal pair of the first sub-circuit;
The first sub-circuit has B sets of differential output terminal pairs comprising first and second output terminals each having a driving capability of 1 / N per one input terminal forming the differential output terminal pair. ,
Each of the N second group child circuits comprises:
A set of differential input terminal pairs comprising first and second input terminals having 1 / N input capacitance per input terminal forming the differential output terminal pair of the second sub-circuit is provided. ,
The differential output terminal pair consisting of the first and second output terminals having a driving capability of 1 / N per one differential input terminal constituting the differential output terminal pair of the second sub-circuit is set to B. Have
For each of the N child circuits of the first group and the N child circuits of the second group,
The first group of child circuits and the second group of child circuits corresponding to the first group of child circuits are laid out so as to have a mirror-inverted relationship with each other,
For each of the A sets of differential input terminal pairs of the first child circuit and the second child circuit, which are mirror-inverted and form a pair,
The difference between the first input terminal of the i-th (where i is an integer of 1 or more and A or less) set of differential input terminal pairs of the first child circuit and the i-th set of the second child circuit A second input terminal of the dynamic input terminal pair is connected to one input terminal of a ith set of differential input terminal pairs provided in common with the original circuit;
A second input terminal of an i-th differential input terminal pair of the first child circuit and a first input terminal of an i-th differential input terminal pair of the second child circuit; Corresponding to the original circuit, connected to another input terminal of the differential input terminal pair of the i-th differential input terminal pair provided in common,
For each of the B sets of differential output terminal pairs of the first child circuit and the second child circuit, which are mirror-inverted with each other and form a pair,
A difference between a first output terminal of a j-th (where j is an integer of 1 or more and B or less) set of differential output terminal pairs of the first child circuit and a j-th set of the second child circuit. A second output terminal of the dynamic output terminal pair is connected to one output terminal of a j-th set of differential output terminal pairs provided in common corresponding to the original circuit;
A second output terminal of a j-th set of differential output terminals of the first child circuit and a first output terminal of a j-th set of differential output terminals of the second child circuit; A semiconductor integrated circuit connected to another output terminal of the differential output terminal pair of the j-th set of differential output terminals provided in common with the original circuit. . 半導体回路の回路情報を基に、半導体基板上への集積化のための、配置及び配線のレイアウト処理をコンピュータで行う半導体集積回路の設計方法であって、
１つの差動入力端子対をなす２つの入力端子と、１つの差動出力端子対をなす２つの出力端子とを少なくとも有し、前記差動入力端子対からの信号を差動入力し、出力信号を前記差動出力端子対から差動出力する回路（「元の回路」という）の回路情報を記憶手段から入力し、前記元の回路を、前記元の回路と同一又は等価な機能の回路構成の２つのサブ回路で置き換え、前記２つのサブ回路の回路情報を記憶手段に記憶するステップを有し、
前記２つのサブ回路をなす第１及び第２のサブ回路のそれぞれが、
前記元の回路の前記差動入力端子対をなす入力端子１つあたりの半分の入力容量を有し、各サブ回路の差動入力端子対をなす第１及び第２の入力端子と、
前記元の回路の前記差動出力端子対をなす出力端子の半分の駆動能力を有し、各サブ回路の差動出力端子対をなす第１及び第２の出力端子と、
を有するものであり、
前記第１及び第２のサブ回路に対して、共通に、１つの差動入力端子対と１つの差動出力端子対とを用意し、
前記記憶手段より、前記第１及び第２のサブ回路の回路情報を入力し、前記第１のサブ回路の第１の入力端子と前記第２のサブ回路の第２の入力端子とを接続して、前記第１及び第２のサブ回路に共通の前記差動入力端子対の１つの入力端子とするステップと、
前記第１のサブ回路の第２の入力端子と前記第２のサブ回路の第１の入力端子とを接続して、前記第１及び第２のサブ回路に共通の前記差動入力端子対の他の入力端子とするステップと、
前記第１のサブ回路の第１の出力端子と前記第２のサブ回路の第２の出力端子とを接続して、前記第１及び第２のサブ回路に共通の前記差動出力端子対の１つの出力端子とするステップと、
前記第１のサブ回路の第２の出力端子と第２のサブ回路の第１の出力端子を接続して、前記第１及び第２のサブ回路に共通の前記差動出力端子対の他の出力端子とするステップと、
を含む、ことを特徴とする半導体集積回路の設計方法。A method for designing a semiconductor integrated circuit, in which a computer performs layout processing of arrangement and wiring on a semiconductor substrate based on circuit information of the semiconductor circuit,
It has at least two input terminals forming one differential input terminal pair and two output terminals forming one differential output terminal pair, differentially inputs a signal from the differential input terminal pair, and outputs Circuit information of a circuit (referred to as an "original circuit") for differentially outputting a signal from the differential output terminal pair is input from storage means, and the original circuit is replaced with a circuit having the same or equivalent function as the original circuit. Replacing with two sub-circuits having a configuration, and storing circuit information of the two sub-circuits in a storage means,
Each of the first and second sub-circuits forming the two sub-circuits is
First and second input terminals having a half input capacitance per input terminal forming the differential input terminal pair of the original circuit, and forming a differential input terminal pair of each sub-circuit;
A first output terminal and a second output terminal each having half the driving ability of the output terminal forming the differential output terminal pair of the original circuit and forming a differential output terminal pair of each sub-circuit;
Which has
One differential input terminal pair and one differential output terminal pair are prepared in common for the first and second sub-circuits,
The circuit information of the first and second sub-circuits is input from the storage unit, and a first input terminal of the first sub-circuit is connected to a second input terminal of the second sub-circuit. Setting one input terminal of the differential input terminal pair common to the first and second sub-circuits;
A second input terminal of the first sub-circuit and a first input terminal of the second sub-circuit are connected to each other to connect the differential input terminal pair common to the first and second sub-circuits. Setting another input terminal;
A first output terminal of the first sub-circuit is connected to a second output terminal of the second sub-circuit, and a differential output terminal pair common to the first and second sub-circuits is connected. Making one output terminal;
A second output terminal of the first sub-circuit is connected to a first output terminal of the second sub-circuit, and the other of the differential output terminal pair common to the first and second sub-circuits is connected. An output terminal;
A method for designing a semiconductor integrated circuit, comprising: 前記第１のサブ回路の配置と前記第２のサブ回路の配置、及び、前記第１のサブ回路と前記第２のサブ回路間の配線が、互いに鏡面反転の関係になるようにレイアウトされる、ことを特徴とする請求項５記載の半導体集積回路の設計方法。The layout of the first sub-circuit and the layout of the second sub-circuit, and the wiring between the first sub-circuit and the second sub-circuit are laid out such that they have a mirror-inverted relationship with each other. 6. The method for designing a semiconductor integrated circuit according to claim 5, wherein 半導体回路の回路情報を基に、半導体基板上への集積化のための、配置及び配線のレイアウト処理をコンピュータで行う半導体集積回路の設計方法であって、
１つの差動入力端子対をなす２つの入力端子と、１つの差動出力端子対をなす２つの出力端子とを少なくとも有し、前記差動入力端子対からの信号を差動入力し、出力信号を前記差動出力端子対から差動出力する回路（「元の回路」という）の回路情報を記憶手段より入力し、前記元の回路を、前記元の回路と同一又は等価な回路構成の２つのサブ回路で置き換え、前記２つのサブ回路の回路情報を記憶手段に記憶するステップを有し、
前記２つのサブ回路をなす第１及び第２のサブ回路のそれぞれは、
前記元の回路の前記差動入力端子対をなす入力端子１つあたりの半分の入力容量を有し、各サブ回路の差動入力端子対をなす第１及び第２の入力端子と、
前記元の回路の前記差動出力端子対をなす出力端子の半分の駆動能力を有し、各サブ回路の差動出力端子対をなす第１及び第２の出力端子を有し、
前記Ｎ個の第１群の子の回路と前記Ｎ個の第２群の子の回路に対して、共通に設けられている、１つの差動入力端子対と１つの差動出力端子対とを有し、
前記記憶手段から前記第１のサブ回路の回路情報を入力し、前記第１のサブ回路を、前記第１のサブ回路と同一又は等価な機能の回路構成のＮ個（Ｎは２以上の整数）の第１群の子の回路で置き換え、前記Ｎ個の第１群の子の回路の回路情報を記憶手段に記憶するステップと、
前記記憶手段から前記第２のサブ回路の回路情報を入力し、前記第２のサブ回路を、前記第２のサブ回路と同一又は等価な機能の回路構成のＮ個（Ｎは２以上の整数）の第２群の子の回路で置き換え、前記Ｎ個の第２群の子の回路の回路情報を記憶手段に記憶するステップと、
を有し、
前記Ｎ個の第１群の子の回路のそれぞれは、
前記第１のサブ回路の前記差動入力端子対をなす入力端子１つあたりのＮ分の１の入力容量を有し、各子の回路の差動入力端子対をなす第１及び第２の入力端子と、
前記第１のサブ回路の前記差動出力端子対をなす出力端子１つあたりのＮ分の１の駆動能力を有し、各子の回路の差動出力端対をなす第１及び第２の出力端子と、
を有するものであり、
前記Ｎ個の第２群の子の回路のそれぞれは、
前記第２のサブ回路の前記差動入力端子対をなす入力端子のＮ分の１の入力容量を有し、各子の回路の差動入力端子対をなす第１及び第２の入力端子と第２の入力端子と、
前記第２のサブ回路の前記差動出力端子対をなす出力端子１つあたりのＮ分の１の駆動能力を有し、各子の回路の差動出力端子対をなす第１及び第２の出力端子と、
を有するものであり、
Ｎ個の前記第１群の子の回路とＮ個の前記第２群の子の回路とのそれぞれについて、
前記第１群の子の回路と、前記第１群の子の回路に対応する前記第２群の子の回路とが、互いに鏡面反転の関係になるように、レイアウトするステップを有し、
その際、互いに鏡面反転の関係にあり対をなす第１の子の回路と第２の子の回路について、
前記第１の子の回路の第１の入力端子と前記第２の子の回路の第２の入力端子とを接続し、共通に設けられた前記差動入力端子対の１つの入力端子とするステップと、
前記第１の子の回路の第２の入力端子と前記第２の子の回路の第１の入力端子とを接続し、共通に設けられた前記差動入力端子対の他の入力端子とするステップと、
前記第１の子の回路の第１の出力端子と前記第２の子の回路の第２の出力端子とを接続し、共通に設けられた前記差動出力端子対の１つの出力端子とするステップと、
前記第１の子の回路の第２の出力端子と前記第２の子の回路の第１の出力端子とを接続し、共通に設けられた前記差動出力端子対の他の出力端子とするステップと、
を含む、ことを特徴とする半導体集積回路の設計方法。A method for designing a semiconductor integrated circuit, in which a computer performs layout processing of arrangement and wiring on a semiconductor substrate based on circuit information of the semiconductor circuit,
It has at least two input terminals forming one differential input terminal pair and two output terminals forming one differential output terminal pair, differentially inputs a signal from the differential input terminal pair, and outputs Circuit information of a circuit (referred to as “original circuit”) that differentially outputs signals from the differential output terminal pair is input from a storage unit, and the original circuit is replaced with a circuit having the same or equivalent circuit configuration as the original circuit. Replacing with two sub-circuits and storing circuit information of the two sub-circuits in a storage means;
Each of the first and second sub-circuits forming the two sub-circuits includes:
First and second input terminals having a half input capacitance per input terminal forming the differential input terminal pair of the original circuit, and forming a differential input terminal pair of each sub-circuit;
The first circuit has half the driving capability of the output terminal forming the differential output terminal pair of the original circuit, and has first and second output terminals forming the differential output terminal pair of each sub-circuit,
One differential input terminal pair and one differential output terminal pair provided in common for the N first group child circuits and the N second group child circuits. Has,
The circuit information of the first sub-circuit is input from the storage means, and the first sub-circuit is divided into N (N is an integer of 2 or more) circuits having the same or equivalent function as the first sub-circuit. ) Replacing the first group of child circuits and storing the circuit information of the N first group child circuits in storage means;
The circuit information of the second sub-circuit is input from the storage means, and the second sub-circuit is divided into N (N is an integer of 2 or more) circuits having the same or equivalent function as the second sub-circuit. ) Replacing the second group of child circuits and storing the circuit information of the N second group of child circuits in storage means;
Has,
Each of the N first group child circuits comprises:
The first and second sub-circuits each have an input capacitance of 1 / N of one input terminal forming the differential input terminal pair, and include first and second input capacitances forming a differential input terminal pair of each child circuit. An input terminal,
The first and second sub-circuits have a driving capability of 1 / N per one output terminal forming the differential output terminal pair, and the first and second sub-circuits constitute a differential output terminal pair of each child circuit. An output terminal,
Which has
Each of the N second group child circuits comprises:
A first and a second input terminal forming a differential input terminal pair of each child circuit having an input capacitance of 1 / N of an input terminal forming the differential input terminal pair of the second sub-circuit; A second input terminal;
The first and second sub-circuits each have a driving capability of 1 / N of one output terminal forming the differential output terminal pair, and form a differential output terminal pair of each child circuit. An output terminal,
Which has
For each of the N child circuits of the first group and the N child circuits of the second group,
Laying out the first group of child circuits and the second group of child circuits corresponding to the first group of child circuits so that they have a mirror-inverted relationship with each other;
At this time, the first child circuit and the second child circuit that are mirror-inverted with each other and form a pair are:
A first input terminal of the first child circuit and a second input terminal of the second child circuit are connected to form one input terminal of the differential input terminal pair provided in common. Steps and
A second input terminal of the first child circuit is connected to a first input terminal of the second child circuit to serve as another input terminal of the differential input terminal pair provided in common. Steps and
A first output terminal of the first child circuit and a second output terminal of the second child circuit are connected to form one output terminal of the differential output terminal pair provided in common. Steps and
A second output terminal of the first child circuit and a first output terminal of the second child circuit are connected to each other to provide another output terminal of the differential output terminal pair provided in common. Steps and
A method for designing a semiconductor integrated circuit, comprising: 半導体回路の回路情報を基に、半導体基板上への集積化のための、配置及び配線のレイアウト処理をコンピュータで行う半導体集積回路の設計方法であって、
第１及び第２の入力端子からなる差動入力端子対をＡ組（ただし、Ａは所定の正整数）備え、第１及び第２の出力端子からなる差動出力端子対をＢ組（ただし、Ｂは所定の正整数）備え、それぞれの組の差動入力端子対から信号を差動入力し、出力信号を対応する差動出力対より差動出力する回路（「元の回路」という）の回路情報を記憶手段より入力し、前記元の回路を、前記元の回路と同一又は等価な機能の回路構成の２つのサブ回路で置き換え、前記２つのサブ回路の回路情報を記憶手段に記憶するステップを有し、
前記２つのサブ回路をなす第１及び第２のサブ回路のそれぞれは、
前記元の回路の前記差動入力端子対をなす入力端子１つあたりの半分の入力容量を有する第１及び第２の入力端子よりなる差動入力端子対をＡ組備え、
前記元の回路の前記差動出力端子対をなす入力端子１つあたりの半分の駆動能力を有する第１及び第２の出力端子よりなる差動出力端子対をＢ組有し、
前記第１のサブ回路の回路情報を前記記憶手段より入力し、前記第１のサブ回路を、前記第１のサブ回路と同一又は等価な機能の回路構成のＮ個（ただし、Ｎは２以上の所定の整数）の第１群の子の回路で置き換え、前記Ｎ個の第１群の子の回路の回路情報を記憶手段に記憶するステップと、
前記第２のサブ回路の回路情報を前記記憶手段より入力し、前記第２のサブ回路を、前記第２のサブ回路と同一又は等価な機能の回路構成のＮ個の第２群の子の回路で置き換え、前記Ｎ個の第２群の子の回路の回路情報を記憶手段に記憶するステップと、
を有し、
前記Ｎ個の第１群の子の回路のそれぞれは、
前記第１のサブ回路の差動出力端子対の入力端子１つあたりのＮ分の１の入力容量を有する第１及び第２の入力端子よりなる差動入力端子対をＡ組有し、
前記第１のサブ回路の差動出力端子対をなす入力端子１つあたりのＮ分の１の駆動能力を有する第１及び第２の出力端子よりなる差動出力端子対をＢ組有し、
前記Ｎ個の第２群の子の回路のそれぞれは、
前記第２のサブ回路の差動出力端子対をなす入力端子１つあたりのＮ分の１の入力容量を有する第１及び第２の入力端子よりなる差動入力端子対をＡ組有し、
前記第２のサブ回路の差動出力端子対をなす出力端子１つあたりのＮ分の１の駆動能力を有する第１及び第２の出力端子よりなる差動出力端子対をＢ組有し、
Ｎ個の前記第１群の子の回路とＮ個の前記第２群の子の回路とのそれぞれについて、
前記第１群の子の回路と、前記第１群の子の回路に対応する前記第２群の子の回路とが、互いに鏡面反転の関係になるように、レイアウトするステップを有し、
その際、互いに鏡面反転の関係にあり対をなす第１の子の回路と第２の子の回路のＡ組の差動入力端子対のそれぞれについて、
前記第１の子の回路の第ｉ（ただし、ｉは１以上Ａ以下の整数）組の差動入力端子対の第１の入力端子と、前記第２の子の回路の第ｉ組の差動入力端子対の第２の入力端子とを接続して、元の回路に対応して、共通に設けられた第ｉ組の差動入力端子対の１つの入力端子とするステップと、
前記第１の子の回路の第ｉ組の差動入力端子対の第２の入力端子と前記第２の子の回路の第ｉ組の差動入力端子対の第１の入力端子とを接続して、前記元の回路に対応して、共通に設けられた第ｉ組の差動入力端子対の前記差動入力端子対の他の入力端子とするステップと、
互いに鏡面反転の関係にあり対をなす前記第１の子の回路と前記第２の子の回路のＢ組の差動出力端子対のそれぞれについて、
前記第１の子の回路の第ｊ（ただし、ｊは１以上Ｂ以下の整数）組の差動出力端子対の第１の出力端子と、前記第２の子の回路の第ｊ組の差動出力端子対の第２の出力端子とを接続して、前記元の回路に対応して、共通に設けられた第ｊ組の差動出力端子対の１つの出力端子とするステップと、
前記第１の子の回路の第ｊ組の差動出力端子対の第２の出力端子と、前記第２の子の回路の第ｊ組の差動出力端子対の第１の出力端子とを接続して、前記元の回路に対応して共通に設けられた、第ｊ組の差動出力端子対の前記差動出力端子対の他の出力端子とするステップと、
を含む、ことを特徴とする半導体集積回路の設計方法。A method for designing a semiconductor integrated circuit, in which a computer performs layout processing of arrangement and wiring on a semiconductor substrate based on circuit information of the semiconductor circuit,
A set of differential input terminal pairs comprising first and second input terminals (where A is a predetermined positive integer) is provided, and B pairs of differential output terminal pairs comprising first and second output terminals are provided (where , B are predetermined positive integers), and a circuit for differentially inputting a signal from each set of differential input terminal pairs and differentially outputting an output signal from a corresponding differential output pair (referred to as an “original circuit”) From the storage means, the original circuit is replaced with two sub-circuits having the same or equivalent circuit configuration as the original circuit, and the circuit information of the two sub-circuits is stored in the storage means. Having a step of
Each of the first and second sub-circuits forming the two sub-circuits includes:
A pair of differential input terminal comprising first and second input terminals each having a half input capacitance per input terminal forming the differential input terminal pair of the original circuit,
B sets of differential output terminal pairs comprising first and second output terminals having half the driving capability per input terminal forming the differential output terminal pair of the original circuit,
The circuit information of the first sub-circuit is input from the storage means, and the first sub-circuit is divided into N circuits having the same or equivalent function as the first sub-circuit (where N is 2 or more). A predetermined integer) of the first group of child circuits and storing the circuit information of the N first group of child circuits in storage means;
The circuit information of the second sub-circuit is input from the storage means, and the second sub-circuit is replaced with N second group children having a circuit configuration having the same or equivalent function as the second sub-circuit. Replacing with N circuits and storing circuit information of the N second group child circuits in storage means;
Has,
Each of the N first group child circuits comprises:
A set of differential input terminal pairs including first and second input terminals having an input capacitance of 1 / N per one input terminal of the differential output terminal pair of the first sub-circuit;
B sets of differential output terminal pairs comprising first and second output terminals having a driving capability of 1 / N per one input terminal forming a differential output terminal pair of the first sub-circuit;
Each of the N second group child circuits comprises:
A set of differential input terminal pairs comprising first and second input terminals having an input capacitance of 1 / N per one input terminal forming a differential output terminal pair of the second sub-circuit;
B sets of differential output terminal pairs comprising first and second output terminals having a driving capability of 1 / N per one output terminal forming a differential output terminal pair of the second sub-circuit;
For each of the N child circuits of the first group and the N child circuits of the second group,
Laying out the first group of child circuits and the second group of child circuits corresponding to the first group of child circuits so that they have a mirror-inverted relationship with each other;
At this time, for each of the A sets of differential input terminal pairs of the first child circuit and the second child circuit, which are mirror-inverted with each other and form a pair,
The difference between the first input terminal of the i-th (where i is an integer of 1 or more and A or less) set of differential input terminal pairs of the first child circuit and the i-th set of the second child circuit Connecting the second input terminal of the dynamic input terminal pair to one input terminal of an i-th differential input terminal pair provided in common with the original circuit;
A second input terminal of an i-th differential input terminal pair of the first child circuit is connected to a first input terminal of an i-th differential input terminal pair of the second child circuit. Corresponding to the original circuit, and as another input terminal of the differential input terminal pair of the i-th differential input terminal pair provided in common,
For each of the B sets of differential output terminal pairs of the first child circuit and the second child circuit, which are mirror-inverted with each other and form a pair,
A difference between a first output terminal of a j-th (where j is an integer of 1 or more and B or less) set of differential output terminal pairs of the first child circuit and a j-th set of the second child circuit. Connecting the second output terminal of the dynamic output terminal pair to one output terminal of a j-th set of differential output terminal pairs provided in common with the original circuit;
A second output terminal of a j-th set of differential output terminals of the first child circuit and a first output terminal of a j-th set of differential output terminals of the second child circuit; Connecting to another output terminal of the differential output terminal pair of the j-th set of differential output terminals provided in common corresponding to the original circuit;
A method for designing a semiconductor integrated circuit, comprising: 半導体回路の回路情報を基に、半導体基板上への集積化のための配置及び配線のレイアウト処理をコンピュータで行う設計自動化装置であって、
１つの差動入力端子対をなす２つの入力端子と、１つの差動出力端子対をなす２つの出力端子とを少なくとも有し、前記差動入力端子対からの信号を差動入力し、出力信号を前記差動出力端子対から差動出力する回路（「元の回路」という）の回路情報を記憶手段から入力し、前記元の回路を、前記元の回路と同一又は等価な機能の回路構成の２つのサブ回路で置き換える手段を有し、
前記２つのサブ回路をなす第１及び第２のサブ回路のそれぞれが、
前記元の回路の前記差動入力端子対をなす入力端子１つあたりの半分の入力容量を有し、各サブ回路の差動入力端子対をなす第１及び第２の入力端子と、
前記元の回路の前記差動出力端子対をなす出力端子１つあたりの半分の駆動能力を有し、各サブ回路の差動出力端子対をなす第１及び第２の出力端子と、
を有し、
前記第１及び第２のサブ回路に対して、共通に設けられた、１つの差動入力端子対と１つの差動出力端子対とを有し、
前記第１のサブ回路の第１の入力端子と前記第２のサブ回路の第２の入力端子とを接続して、前記第１及び第２のサブ回路に共通の前記差動入力端子対の１つの入力端子とする手段と、
前記第１のサブ回路の第２の入力端子と前記第２のサブ回路の第１の入力端子とを接続して、前記第１及び第２のサブ回路に共通の前記差動入力端子対の他の入力端子とする手段と、
前記第１のサブ回路の第１の出力端子と前記第２のサブ回路の第２の出力端子とを接続して、前記第１及び第２のサブ回路に共通の前記差動出力端子対の１つの出力端子とする手段と、
前記第１のサブ回路の第２の出力端子と前記第２のサブ回路の第１の出力端子を接続して、前記第１及び第２のサブ回路に共通の前記差動出力端子対の他の出力端子とする手段と、
を備えている、ことを特徴とする設計自動化装置。Based on the circuit information of the semiconductor circuit, a design automation apparatus that performs a layout process of arrangement and wiring for integration on a semiconductor substrate by a computer,
It has at least two input terminals forming one differential input terminal pair and two output terminals forming one differential output terminal pair, differentially inputs a signal from the differential input terminal pair, and outputs Circuit information of a circuit (referred to as an "original circuit") for differentially outputting a signal from the differential output terminal pair is input from storage means, and the original circuit is replaced with a circuit having the same or equivalent function as the original circuit. Means for replacing with two sub-circuits of configuration
Each of the first and second sub-circuits forming the two sub-circuits is
First and second input terminals having a half input capacitance per input terminal forming the differential input terminal pair of the original circuit, and forming a differential input terminal pair of each sub-circuit;
A first and a second output terminal having a half driving capability per output terminal forming the differential output terminal pair of the original circuit, and forming a differential output terminal pair of each sub-circuit;
Has,
The first and second sub-circuits have one differential input terminal pair and one differential output terminal pair provided in common,
A first input terminal of the first sub-circuit and a second input terminal of the second sub-circuit are connected to each other to connect the differential input terminal pair common to the first and second sub-circuits; Means for one input terminal;
A second input terminal of the first sub-circuit and a first input terminal of the second sub-circuit are connected to each other to connect the differential input terminal pair common to the first and second sub-circuits. Means for other input terminals;
A first output terminal of the first sub-circuit is connected to a second output terminal of the second sub-circuit, and a differential output terminal pair common to the first and second sub-circuits is connected. Means for providing one output terminal;
A second output terminal of the first sub-circuit is connected to a first output terminal of the second sub-circuit, and the other of the differential output terminal pair common to the first and second sub-circuits is connected. Means for the output terminal of
A design automation device comprising: 前記第１のサブ回路の配置と前記第２のサブ回路の配置、及び、前記第１のサブ回路と前記第２のサブ回路間の配線が、互いに鏡面反転の関係になるようにレイアウトする手段を備えている、ことを特徴とする請求項９記載の設計自動化装置。Means for laying out such that the arrangement of the first sub-circuit and the arrangement of the second sub-circuit and the wiring between the first sub-circuit and the second sub-circuit have a mirror-inverted relationship with each other. The design automation apparatus according to claim 9, further comprising: 半導体回路の回路情報を基に、半導体基板上への集積化のための配置及び配線のレイアウト処理をコンピュータで行う設計自動化装置であって、
１つの差動入力端子対をなす２つの入力端子と、１つの差動出力端子対をなす２つの出力端子とを少なくとも有し、前記差動入力端子対からの信号を差動入力し、出力信号を前記差動出力端子対から差動出力する回路（「元の回路」という）の回路情報を記憶手段より入力し、前記元の回路を、前記元の回路と同一又は等価な回路構成の２つのサブ回路で置き換える手段を有し、
前記２つのサブ回路をなす第１及び第２のサブ回路のそれぞれは、
前記元の回路の前記差動入力端子対をなす入力端子１つあたりの半分の入力容量を有し、各サブ回路の差動入力端子対をなす第１及び第２の入力端子と、
前記元の回路の前記差動出力端子対をなす出力端子１つあたりの半分の駆動能力を有し、各サブ回路の差動出力端子対をなす第１及び第２の出力端子と、
を有し、
前記元の回路の１つの差動入力端子対と１つの差動出力端子対に対応して、前記第１及び第２のサブ回路に対して、共通に、１つの差動入力端子対と１つの差動出力端子対とを設ける手段を有し、
さらに前記第１のサブ回路を、前記第１のサブ回路の回路情報に基づき、前記第１のサブ回路と同一又は等価な機能の回路構成のＮ個（Ｎは２以上の整数）の第１群の子の回路で置き換える手段と、
前記第２のサブ回路を、前記第２のサブ回路の回路情報に基づき、前記第２のサブ回路と同一又は等価な機能の回路構成のＮ個の第２群の子の回路で置き換える手段と、
を備え、
前記Ｎ個の第１群の子の回路と前記Ｎ個の第２群の子回路に対して、共通に設けられている、１つの差動入力端子対と１つの差動出力端子対とを有し、
前記Ｎ個の第１群の子の回路のそれぞれは、
前記第１のサブ回路の前記差動入力端子対をなす入力端子１つあたりのＮ分の１の入力容量を有し、各子の回路の差動入力端子対をなす第１及び第２の入力端子と、
前記第１のサブ回路の前記差動出力端子対をなす出力端子１つあたりのＮ分の１の駆動能力を有し、各子の回路の差動出力端対をなす第１及び第２の出力端子と、
を有し、
前記Ｎ個の第２群の子の回路のそれぞれは、
前記第２のサブ回路の前記差動入力端子対をなす入力端子１つあたりのＮ分の１の入力容量を有し、各子の回路の差動入力端子対をなす第１及び第２の入力端子と第２の入力端子と、
前記第２のサブ回路の前記差動出力端子対をなす出力端子１つあたりのＮ分の１の駆動能力を有し、各子の回路の差動出力端子対をなす第１及び第２の出力端子と、
を有し、
Ｎ個の前記第１群の子の回路とＮ個の前記第２群の子の回路とのそれぞれについて、前記第１群の子の回路と、前記第１群の子の回路に対応する前記第２群の子の回路とは、互いに鏡面反転の関係になるように、レイアウトする手段を備え、
前記レイアウトする手段は、
互いに鏡面反転の関係にあり対をなす第１の子の回路と第２の子の回路について、
前記第１の子の回路の第１の入力端子と前記第２の子の回路の第２の入力端子とを接続して、共通に設けられた前記差動入力端子対の１つの入力端子とする手段と、
前記第１の子の回路の第２の入力端子と前記第２の子の回路の第１の入力端子とを接続し、共通に設けられた前記差動入力端子対の他の入力端子とする手段と、
前記第１の子の回路の第１の出力端子と前記第２の子の回路の第２の出力端子とを接続し、共通に設けられた前記差動出力端子対の１つの出力端子とする手段と、
前記第１の子の回路の第２の出力端子と前記第２の子の回路の第１の出力端子とを接続し、共通に設けられた前記差動出力端子対の他の出力端子とする手段と、
を備えている、ことを特徴とする設計自動化装置。Based on the circuit information of the semiconductor circuit, a design automation apparatus that performs a layout process of arrangement and wiring for integration on a semiconductor substrate by a computer,
It has at least two input terminals forming one differential input terminal pair and two output terminals forming one differential output terminal pair, differentially inputs a signal from the differential input terminal pair, and outputs Circuit information of a circuit (referred to as “original circuit”) that differentially outputs signals from the differential output terminal pair is input from a storage unit, and the original circuit is replaced with a circuit having the same or equivalent circuit configuration as the original circuit. Has means to replace with two sub-circuits,
Each of the first and second sub-circuits forming the two sub-circuits includes:
First and second input terminals having a half input capacitance per input terminal forming the differential input terminal pair of the original circuit, and forming a differential input terminal pair of each sub-circuit;
A first and a second output terminal having a half driving capability per output terminal forming the differential output terminal pair of the original circuit, and forming a differential output terminal pair of each sub-circuit;
Has,
Corresponding to one differential input terminal pair and one differential output terminal pair of the original circuit, one differential input terminal pair and one common to the first and second sub-circuits. Means for providing two differential output terminal pairs,
Further, based on circuit information of the first sub-circuit, the first sub-circuit is divided into N (N is an integer of 2 or more) first circuit circuits having the same or equivalent function as the first sub-circuit. Means for replacing with a child circuit of the group;
Means for replacing the second sub-circuit with N second group child circuits having a circuit configuration having the same or equivalent function as the second sub-circuit based on the circuit information of the second sub-circuit; ,
With
One differential input terminal pair and one differential output terminal pair, which are provided in common for the N first group child circuits and the N second group child circuits, Have
Each of the N first group child circuits comprises:
The first and second sub-circuits each have an input capacitance of 1 / N of one input terminal forming the differential input terminal pair, and include first and second input capacitances forming a differential input terminal pair of each child circuit. An input terminal,
The first and second sub-circuits have a driving capability of 1 / N per one output terminal forming the differential output terminal pair, and the first and second sub-circuits constitute a differential output terminal pair of each child circuit. An output terminal,
Has,
Each of the N second group child circuits comprises:
The first and second sub-circuits each have a 1 / N input capacitance per input terminal forming the differential input terminal pair, and constitute a differential input terminal pair of each child circuit. An input terminal, a second input terminal,
The first and second sub-circuits each have a driving capability of 1 / N of one output terminal forming the differential output terminal pair, and form a differential output terminal pair of each child circuit. An output terminal,
Has,
The N child circuits of the first group and the N child circuits of the second group respectively correspond to the child circuits of the first group and the child circuits of the first group. The second group of child circuits is provided with a means for laying out so as to have a mirror-inverted relationship with each other,
The means for laying out includes:
Regarding a first child circuit and a second child circuit that are mirror-inverted to each other and form a pair,
A first input terminal of the first child circuit is connected to a second input terminal of the second child circuit, and one input terminal of the differential input terminal pair provided in common is Means to
A second input terminal of the first child circuit is connected to a first input terminal of the second child circuit to serve as another input terminal of the differential input terminal pair provided in common. Means,
A first output terminal of the first child circuit and a second output terminal of the second child circuit are connected to form one output terminal of the differential output terminal pair provided in common. Means,
A second output terminal of the first child circuit and a first output terminal of the second child circuit are connected to each other to provide another output terminal of the differential output terminal pair provided in common. Means,
A design automation device comprising: 半導体回路の回路情報を基に、半導体基板上への集積化のための配置及び配線のレイアウト処理をコンピュータで行う設計自動化装置であって、
第１及び第２の入力端子からなる差動入力端子対をＡ組（ただし、Ａは所定の正整数）備え、第１及び第２の出力端子からなる差動出力端子対をＢ組（ただし、Ｂは所定の正整数）備え、それぞれの組の差動入力端子対から信号を差動入力し、出力信号を対応する差動出力対より差動出力する回路（「元の回路」という）の回路情報を記憶手段より入力し、前記元の回路を、前記元の回路と同一又は等価な機能の回路構成の２つのサブ回路で置き換える手段を有し、
前記２つのサブ回路をなす第１及び第２のサブ回路のそれぞれは、
前記元の回路の前記差動入力端子対をなす入力端子１つあたりの半分の入力容量を有する第１及び第２の入力端子よりなる差動入力端子対をＡ組備え、
前記元の回路の差動出力端子対をなす入力端子１つあたりの半分の駆動能力を有する第１及び第２の出力端子よりなる差動出力端子対をＢ組有し、
前記第１のサブ回路を、前記第１のサブ回路と同一又は等価な機能の回路構成のＮ個（ただし、Ｎは２以上の所定の整数）の第１群の子の回路で置き換える手段と、
前記第２のサブ回路を、前記第２のサブ回路と同一又は等価な機能の回路構成のＮ個の第２群の子の回路で置き換える手段と、
を有し、
前記Ｎ個の第１群の子の回路のそれぞれは、
前記第１のサブ回路の前記差動出力端子対の入力端子１つあたりのＮ分の１の入力容量を有する第１及び第２の入力端子よりなる差動入力端子対をＡ組有し、
前記第１のサブ回路の差動出力端子対をなす入力端子１つあたりのＮ分の１の駆動能力を有する第１及び第２の出力端子よりなる差動出力端子対をＢ組有し、
前記Ｎ個の第２群の子の回路のそれぞれは、
前記第２のサブ回路の差動出力端子対をなす入力端子１つあたりのＮ分の１の入力容量を有する第１及び第２の入力端子よりなる差動入力端子対をＡ組有し、
前記第２のサブ回路の差動出力端子対をなす差動入力端子１つあたりのＮ分の１の駆動能力を有する第１及び第２の出力端子よりなる差動出力端子対をＢ組有し、
Ｎ個の前記第１群の子の回路とＮ個の前記第２群の子の回路とのそれぞれについて、前記第１群の子の回路と、前記第１群の子の回路に対応する前記第２群の子の回路とは、互いに鏡面反転の関係になるようにレイアウトする手段を有し、
前記レイアウトする手段は、
互いに鏡面反転の関係にあり対をなす第１の子の回路と第２の子の回路のＡ組の差動入力端子対のそれぞれについて、
前記第１の子の回路の第ｉ（ただし、ｉは１以上Ａ以下の整数）組の差動入力端子対の第１の入力端子と、前記第２の子の回路の第ｉ組の差動入力端子対の第２の入力端子とを接続して、元の回路に対応して、共通に設けられた第ｉ組の差動入力端子対の１つの入力端子とする手段と、
前記第１の子の回路の第ｉ組の差動入力端子対の第２の入力端子と前記第２の子の回路の第ｉ組の差動入力端子対の第１の入力端子とを接続して、前記元の回路に対応して、共通に設けられた第ｉ組の差動入力端子対の前記差動入力端子対の他の入力端子とする手段と、
を有し、
互いに鏡面反転の関係にあり対をなす前記第１の子の回路と前記第２の子の回路のＢ組の差動出力端子対のそれぞれについて、
前記第１の子の回路の第ｊ（ただし、ｊは１以上Ｂ以下の整数）組の差動出力端子対の第１の出力端子と、前記第２の子の回路の第ｊ組の差動出力端子対の第２の出力端子とを接続して、前記元の回路に対応して、共通に設けられた第ｊ組の差動出力端子対の１つの出力端子とする手段と、
前記第１の子の回路の第ｊ組の差動出力端子対の第２の出力端子と、前記第２の子の回路の第ｊ組の差動出力端子対の第１の出力端子とを接続して、前記元の回路に対応して共通に設けられた、第ｊ組の差動出力端子対の前記差動出力端子対の他の出力端子とする手段と、
を備えている、ことを特徴とする設計自動化装置。Based on the circuit information of the semiconductor circuit, a design automation apparatus that performs a layout process of arrangement and wiring for integration on a semiconductor substrate by a computer,
A set of differential input terminal pairs comprising first and second input terminals (where A is a predetermined positive integer) is provided, and B pairs of differential output terminal pairs comprising first and second output terminals are provided (where , B are predetermined positive integers), and a circuit for differentially inputting a signal from each set of differential input terminal pairs and differentially outputting an output signal from a corresponding differential output pair (referred to as an “original circuit”) Means for inputting the circuit information from the storage means, and replacing the original circuit with two sub-circuits having a circuit configuration having the same or equivalent function as the original circuit,
Each of the first and second sub-circuits forming the two sub-circuits includes:
A pair of differential input terminal comprising first and second input terminals each having a half input capacitance per input terminal forming the differential input terminal pair of the original circuit,
B sets of differential output terminal pairs comprising first and second output terminals having half the driving capability per input terminal forming a differential output terminal pair of the original circuit;
Means for replacing the first sub-circuit with N (where N is a predetermined integer of 2 or more) first-group child circuits having a circuit configuration having the same or equivalent function as the first sub-circuit; ,
Means for replacing the second sub-circuit with N second-group child circuits having a circuit configuration having the same or equivalent function as the second sub-circuit;
Has,
Each of the N first group child circuits comprises:
A set of a differential input terminal pair including first and second input terminals having an input capacitance of 1 / N per input terminal of the differential output terminal pair of the first sub-circuit;
B sets of differential output terminal pairs comprising first and second output terminals having a driving capability of 1 / N per one input terminal forming a differential output terminal pair of the first sub-circuit;
Each of the N second group child circuits comprises:
A set of differential input terminal pairs comprising first and second input terminals having an input capacitance of 1 / N per one input terminal forming a differential output terminal pair of the second sub-circuit;
B sets of differential output terminal pairs comprising first and second output terminals having 1 / N drive capability per differential input terminal forming a differential output terminal pair of the second sub-circuit. And
The N child circuits of the first group and the N child circuits of the second group respectively correspond to the child circuits of the first group and the child circuits of the first group. The second group of child circuits have means for laying them out such that they have a mirror-inverted relationship with each other,
The means for laying out includes:
For each of the A sets of differential input terminal pairs of the first child circuit and the second child circuit, which are mirror-inverted and form a pair,
The difference between the first input terminal of the i-th (where i is an integer of 1 or more and A or less) set of differential input terminal pairs of the first child circuit and the i-th set of the second child circuit Means for connecting the second input terminal of the dynamic input terminal pair to one input terminal of the ith set of differential input terminal pairs provided in common corresponding to the original circuit;
A second input terminal of an i-th differential input terminal pair of the first child circuit is connected to a first input terminal of an i-th differential input terminal pair of the second child circuit. Means for corresponding to the original circuit, as another input terminal of the differential input terminal pair of the i-th differential input terminal pair provided in common,
Has,
For each of the B sets of differential output terminal pairs of the first child circuit and the second child circuit, which are mirror-inverted with each other and form a pair,
A difference between a first output terminal of a j-th (where j is an integer of 1 or more and B or less) set of differential output terminal pairs of the first child circuit and a j-th set of the second child circuit. Means for connecting the second output terminal of the dynamic output terminal pair to one output terminal of a j-th set of differential output terminal pairs provided in common corresponding to the original circuit;
A second output terminal of a j-th set of differential output terminals of the first child circuit and a first output terminal of a j-th set of differential output terminals of the second child circuit; Means for connecting to another output terminal of the differential output terminal pair of the j-th set of differential output terminals provided in common corresponding to the original circuit;
A design automation device comprising: 半導体回路の回路情報を基に、半導体基板上への集積化のための配置及び配線のレイアウト処理を行う設計自動化装置を構成するコンピュータで実行されるプログラムであって、
１つの差動入力端子対をなす２つの入力端子と、１つの差動出力端子対をなす２つの出力端子とを少なくとも有し、前記差動入力端子対からの信号を差動入力し、出力信号を前記差動出力端子対から差動出力する回路（「元の回路」という）の回路情報を記憶手段から入力し、前記元の回路を、前記元の回路と同一又は等価な機能の回路構成の２つのサブ回路に分割し、前記２つのサブ回路の回路情報を記憶手段に記憶する第１の処理を有し、
前記２つのサブ回路をなす第１及び第２のサブ回路のそれぞれが、
前記元の回路の前記差動入力端子対をなす入力端子１つあたりの半分の入力容量を有し、各サブ回路の差動入力端子対をなす第１及び第２の入力端子と、
前記元の回路の前記差動出力端子対をなす出力端子の半分の駆動能力を有し、各サブ回路の差動出力端子対をなす第１及び第２の出力端子と、
を有するものであり、
前記第１及び第２のサブ回路に対して、共通に、１つの差動入力端子対と１つの差動出力端子対とを用意し、
前記記憶手段より、前記第１及び第２のサブ回路の回路情報を入力し、前記第１のサブ回路の第１の入力端子と前記第２のサブ回路の第２の入力端子とを、前記第１及び第２のサブ回路に共通の前記差動入力端子対の１つの入力端子に接続し、前記第１のサブ回路の第２の入力端子と前記第２のサブ回路の第１の入力端子とを、前記第１及び第２のサブ回路に共通の前記差動入力端子対の他の入力端子に接続する第２の処理と、
前記第１のサブ回路の第１の出力端子と前記第２のサブ回路の第２の出力端子とを、前記第１及び第２のサブ回路に共通の前記差動出力端子対の１つの出力端子に接続し、前記第１のサブ回路の第２の出力端子と第２のサブ回路の第１の出力端子とを、前記第１及び第２のサブ回路に共通の前記差動出力端子対の他の出力端子に接続する第３の処理と、
を含み、
前記第１乃至第３の処理を前記コンピュータに実行させるプログラム。Based on circuit information of a semiconductor circuit, a program executed by a computer constituting a design automation device that performs layout processing of arrangement and wiring for integration on a semiconductor substrate,
It has at least two input terminals forming one differential input terminal pair and two output terminals forming one differential output terminal pair, differentially inputs a signal from the differential input terminal pair, and outputs Circuit information of a circuit (referred to as an "original circuit") for differentially outputting a signal from the differential output terminal pair is input from storage means, and the original circuit is replaced with a circuit having the same or equivalent function as the original circuit. A first process of dividing the configuration into two sub-circuits and storing circuit information of the two sub-circuits in storage means;
Each of the first and second sub-circuits forming the two sub-circuits is
First and second input terminals having a half input capacitance per input terminal forming the differential input terminal pair of the original circuit, and forming a differential input terminal pair of each sub-circuit;
A first output terminal and a second output terminal each having half the driving ability of the output terminal forming the differential output terminal pair of the original circuit and forming a differential output terminal pair of each sub-circuit;
Which has
One differential input terminal pair and one differential output terminal pair are prepared in common for the first and second sub-circuits,
Circuit information of the first and second sub-circuits is input from the storage means, and a first input terminal of the first sub-circuit and a second input terminal of the second sub-circuit are A second input terminal of the first sub-circuit and a first input of the second sub-circuit connected to one input terminal of the differential input terminal pair common to the first and second sub-circuits; A second process of connecting a terminal to another input terminal of the differential input terminal pair common to the first and second sub-circuits;
A first output terminal of the first sub-circuit and a second output terminal of the second sub-circuit are connected to one output of the differential output terminal pair common to the first and second sub-circuits. A second output terminal of the first sub-circuit and a first output terminal of the second sub-circuit, the differential output terminal pair being common to the first and second sub-circuits. A third process of connecting to another output terminal of
Including
A program for causing the computer to execute the first to third processes. 請求項１３記載のプログラムにおいて、
前記第１のサブ回路の配置と前記第２のサブ回路の配置、及び、前記第１のサブ回路と前記第２のサブ回路との間の配線が、互いに鏡面反転の関係になるように、配置及び配線する処理を前記コンピュータに実行させるプログラム。The program according to claim 13,
The arrangement of the first sub-circuit and the arrangement of the second sub-circuit, and the wiring between the first sub-circuit and the second sub-circuit are mirror-inverted with each other. A program for causing the computer to execute a process of arranging and wiring.
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US7304506B2 (en) 2005-02-28 2007-12-04 Ricoh Company, Ltd. Differential output circuit and semiconductor device having the same
JP2009531989A (en) * 2006-03-28 2009-09-03 ハネウェル・インターナショナル・インコーポレーテッド Radiation-resistant differential output buffer
JP2010154337A (en) * 2008-12-25 2010-07-08 Samsung Electro-Mechanics Co Ltd High frequency module
US7911369B2 (en) 2007-09-14 2011-03-22 Panasonic Corporation Pipelined AD converter
JP2012504337A (en) * 2008-11-25 2012-02-16 ザイリンクス インコーポレイテッド Common center of gravity electrostatic discharge protection for integrated circuit devices

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Cited By (5)

* Cited by examiner, † Cited by third party
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US7304506B2 (en) 2005-02-28 2007-12-04 Ricoh Company, Ltd. Differential output circuit and semiconductor device having the same
JP2009531989A (en) * 2006-03-28 2009-09-03 ハネウェル・インターナショナル・インコーポレーテッド Radiation-resistant differential output buffer
US7911369B2 (en) 2007-09-14 2011-03-22 Panasonic Corporation Pipelined AD converter
JP2012504337A (en) * 2008-11-25 2012-02-16 ザイリンクス インコーポレイテッド Common center of gravity electrostatic discharge protection for integrated circuit devices
JP2010154337A (en) * 2008-12-25 2010-07-08 Samsung Electro-Mechanics Co Ltd High frequency module

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