JP2004022982A - Stacked-layer type semiconductor device - Google Patents

Stacked-layer type semiconductor device Download PDF

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JP2004022982A
JP2004022982A JP2002178821A JP2002178821A JP2004022982A JP 2004022982 A JP2004022982 A JP 2004022982A JP 2002178821 A JP2002178821 A JP 2002178821A JP 2002178821 A JP2002178821 A JP 2002178821A JP 2004022982 A JP2004022982 A JP 2004022982A
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fuse
chip
semiconductor device
stacked
semiconductor chip
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Osamu Ara
荒　修
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
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    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a stacked-layer type semiconductor device which is improved in the reliability of package by improving a humidity-proof characteristic at the fuse aperture of a lower side chip. <P>SOLUTION: The stacked-type semiconductor device comprises a first semiconductor chip which is formed by stacking a plurality of semiconductor chips and has at least one fuse aperture, at least a bonding film stuck to the first semiconductor chip so as to seal the fuse aperture, and a second semiconductor chip arranged at the upper part of the first semiconductor chip via the bonding film. Moreover, a plurality of fuse apertures are sealed with a plurality of bonding films. The plurality of fuse apertures are formed adjacent to the center area of the first semiconductor chip, and these are sealed with a single bonding film. <P>COPYRIGHT: (C)2004,JPO

Description

【０００１】
【発明の属する技術分野】
本発明は、複数の半導体チップを積層して１つのパッケージ内に収納した積層型半導体装置に関する。
【０００２】
【従来の技術】
近年の携帯電話などの情報通信機器が軽量小型化および高性能化するのに伴い、組み込まれる半導体装置に対するいっそうの小型化および高機能化が強く求められている。これに応えるために、異なるシステムを有する複数の半導体チップを組み合わせて、１つのパッケージ内に収納するパッケージ方式（ＭＣＰ：Ｍｕｌｔｉ　Ｃｈｉｐ　Ｐａｃｋａｇｅ）による半導体装置が広く用いられている。このＭＣＰ方式の中でも、リードフレームの表面および裏面に半導体チップを搭載する表裏搭載方式、および大面積の半導体チップ上に別の小面積の半導体チップを直接的に積層するチップ積層方式がある。さらに、チップ積層方式の積層型半導体装置にも、リードフレームを有する積層型半導体装置（リードフレーム型）と、表面実装可能なバンプメタルを含む基板を有する積層型半導体装置（基板型）とがある。
【０００３】
ここで図８ないし図１０を参照しながら、一例として、従来式のチップ積層方式の積層型半導体装置（基板型）について説明する。この積層型半導体装置１０１は、概略、ガラスエポキシ樹脂などで構成された配線基板１１０、この配線基板１１０上に下側ダイボンドフィルム１１２を介して接着された、より大きい面積を有する半導体チップ１２０（単に、「下側チップ」ともいう。）、および下側チップ１２０上に同様の材料からなる上側ダイボンドフィルム１２２を介して接着された、より小さい面積を有する半導体チップ１３０（単に、「上側チップ」ともいう。）を備えている。
【０００４】
下側チップ１２０および上側チップ１３０は、通常、異なるシステムを有し、例えば、ＳＲＡＭ、擬似ＳＲＡＭ、ＤＲＡＭ、またはフラッシュメモリチップなどであり、エンドユーザのニーズに合わせて、これらの半導体チップを任意に組み合わせて、パッケージ化された１つの積層型半導体装置１０１が設計される。
【０００５】
配線基板１１０、下側チップ１２０、および上側チップ１３０は、その上面において、ワイヤボンディング可能な複数の電極パッド１１４，１２４，１３４を有し、下側チップ１２０および上側チップ１３０は、金線ワイヤ１１５を介して配線基板１１０と接続されている。また、この積層型半導体装置１０１を周辺装置（図示せず）に表面実装することができるように、配線基板１１０の下面において、複数のバンプメタル１１６が設けられている。さらに、配線基板１１０の上方において、トランスファモールド樹脂が下側チップ１２０および上側チップ１３０全体を包囲して、これらチップ１２０，１３０を保護している。（図９では、分かりやすくするために、モールド樹脂１４０のハッチングを省略した。）
【０００６】
上述したＳＲＡＭ、擬似ＳＲＡＭ、ＤＲＡＭ、またはフラッシュメモリなどの半導体メモリチップは、一般に、形成されたメモリ回路の上方にパッシベーション層１２５，１３５を一面に有し、チップ周辺部の所定の領域においてパッシベーション層が取り除かれたヒューズ開口部１２６，１３６を有する。モールド樹脂１４０を省略した図８において、下側チップ１２０は、破線で示す領域においてヒューズ開口部１２６を有し、上側チップ１２０は、実線で示す領域においてヒューズ開口部１３６を有する。また、各ヒューズ開口部１２６，１３６の底面には、複数のヒューズライン（図示せず）が形成されている。そして、ヒューズ開口部１２６，１３６を通じて、所定のヒューズラインにレーザ光を照射して、切断することにより、製造時の欠陥などで正常に動作しないメモリ回路を冗長回路に置き換えたり、基準電圧に対する電位のばらつきを抑制するように電位のチューニングを行う。こうして、上側および下側チップ１２０，１３０の製造歩留まりを向上させる。
【０００７】
上述のように、モールド樹脂１４０が上側チップ１３０および下側チップ１２０の全体を包むように成型されているので、図１０の拡大図で示すように、上側チップ１３０のヒューズ開口部１３６ａには、モールド樹脂１４０が隙間なく入り込み、パッシベーション層１３５が形成されないヒューズラインおよびその近傍の回路素子を保護する。
【０００８】
【発明が解決しようとする課題】
しかしながら、上述のように、上側チップ１３０と下側チップ１２０の組み合わせは、最終的な所望する積層型半導体装置の仕様に応じて決定され、下側チップ１２０に対する上側チップ１３０の配置位置、および上側ダイボンドフィルム１２２に対する下側チップ１２０のヒューズ開口部１２６の配置位置などは、上側チップ１３０と下側チップ１２０の組み合わせに依存する。このとき、図９および図１０に示すように、上側ダイボンドフィルム１２２が下側チップ１２０のヒューズ開口部１２６の一部の領域だけをカバーするように配置された場合、モールド樹脂１４０が下側チップ１２０のヒューズ開口部１２６に完全に充填されず、密閉された間隙部１５０が生じることがある。こうした間隙部１５０に封入された空気、とりわけ水分は、ＨＡＳＴ試験を含む温度サイクル試験およびリフロー半田実装時において、膨張・収縮を繰り返し、パッシベーション層１３５が形成されないヒューズラインおよびその近傍の回路素子に多大なダメージを与え、耐湿性などのパッケージ信頼性が著しく損なわれる。
【０００９】
そこで本発明は、こうした問題を解消するためになされたもので、下側チップのヒューズ開口部内に水分が入り込まないように、下側チップのヒューズ開口部の上方には必ずダイボンドフィルムを配置することにより、下側チップのヒューズ開口部における耐湿性を向上させ、パッケージ信頼性の改善された積層型半導体装置を提供することを目的とする。
【００１０】
【課題を解決するための手段】
この目的を達成するために、請求項１に記載の本発明は、複数の半導体チップを積層して形成された積層型半導体装置であって、少なくとも１つのヒューズ開口部を有する第１の半導体チップと、ヒューズ開口部を封止するように第１の半導体チップ上に貼付された少なくとも１つの接着フィルムと、接着フィルムを介して第１の半導体チップの上方に配置された第２の半導体チップとを備える。これにより、第１の半導体チップのヒューズ開口部は、接着フィルムにより確実に封止され、モールド樹脂がヒューズ開口部内に侵入することを防止し、モールド成型時、ヒューズ開口部内への湿気の侵入を阻止し、ヒューズ開口部の耐湿性を実質的に改善することができる。
【００１１】
請求項２に記載の本発明によれば、複数のヒューズ開口部が、複数の接着フィルムにより封止される。これにより、一般にチップ周辺部に配置されたヒューズ開口部の配置位置に合わせて、複数の接着フィルムを用いて複数のヒューズ開口部を封止することができる。
【００１２】
請求項３に記載の本発明によれば、複数のヒューズ開口部が、第１の半導体チップの中央部において互いに隣接して配置され、１つの接着フィルムにより封止される。こうして、１つの接着フィルムを用いて、複数のヒューズ開口部を確実に、かつ容易に封止することができる。また、複数のヒューズ開口部を封止するために、より面積の小さい１つの接着フィルムを用いることができ、接着フィルムのコストを低減できる。
【００１３】
請求項４に記載の本発明によれば、接着フィルムは、第２の半導体チップの面積と同一もしくは小さい面積を有し、第１の半導体チップ上のヒューズ開口部すべてを覆う。したがって、上述した先行技術のように、ヒューズ開口部の一部領域だけがカバーされて、密閉された間隙部が生じることを防ぐことができる。
【００１４】
【発明の実施の形態】
以下、添付図面を参照して本発明に係る積層型半導体装置の実施の形態を説明する。各実施の形態の説明において、理解を容易にするために方向を表す用語（例えば、「上側」、「下側」、「右側」、「左側」、「ｘ方向」、および「ｙ方向」など）を適宜用いるが、これは説明のためのものであって、これらの用語は本発明を限定するものでない。
【００１５】
実施の形態１．
図１および図２を参照しながら、本発明の第１の実施の形態によるチップ積層方式の積層型半導体装置（基板型）について説明する。この積層型半導体装置１は、概略、ガラスエポキシ樹脂などで構成された配線基板１０、この配線基板１０上に下側ダイボンドフィルム１２を介して接着された、より大きい面積を有する半導体チップ２０（単に、「下側チップ」ともいう。）、および下側チップ２０上に同様の材料からなる２本の上側ダイボンドフィルム２２ａ，２２ｂを介して接着された、より小さい面積を有する半導体チップ３０（単に、「上側チップ」ともいう。）を備えている。
【００１６】
下側チップ２０および上側チップ３０は、例えば、ＳＲＡＭ、擬似ＳＲＡＭ、ＤＲＡＭ、またはフラッシュメモリチップなどであり、その組み合わせは、エンドユーザの所望する仕様・機能に依存する。こうして任意に組み合わされたメモリチップを積層し、パッケージ化して１つの積層型半導体装置１が構成される。
【００１７】
配線基板１０、下側チップ２０、および上側チップ３０は、その上面において、ワイヤボンディング可能な複数の電極パッド１４，２４，３４を有し、下側チップ２０および上側チップ３０は、金線ワイヤ１５を介して配線基板１０と接続されている（図１においては金線ワイヤ１５を省略している）。また、この積層型半導体装置１を周辺装置（図示せず）に表面実装することができるように、配線基板１０の下面において、複数のバンプメタル１６が設けられている。さらに、配線基板１０の上方において、トランスファモールド樹脂４０が下側チップ２０および上側チップ３０全体を包囲するように成型され、これらチップ２０，３０を保護している。（分かりやすくするために、図１においてはモールド樹脂４０を省略し、図２においてはそのハッチングを省略した。）なお、モールド樹脂４０が２本の上側ダイボンドフィルム２２ａ，２２ｂの間にも隙間なく充填されやすくするために、上側ダイボンドフィルム２２ａ，２２ｂの膜厚を、下側ダイボンドフィルム１２よりも厚くすることが好ましい。
【００１８】
この実施の形態１において、上側チップ２０および上側チップ３０は、形成されたメモリ回路（図示せず）の上方にパッシベーション層２５，３５を一面に有し、それぞれ図１の破線および実線で示すように、チップ周辺部の所定の領域においてパッシベーション層２５，３５をエッチングして形成されたヒューズ開口部２６，３６を有する。また、ヒューズ開口部２６，３６の底面には、複数のヒューズライン（図示せず）が形成されている。そして、ヒューズ開口部２６，３６を通じて、レーザトリミングすることにより、製造時の欠陥などで正常に動作しないメモリ回路を冗長回路に置き換えたり、基準電圧に対する電位のばらつきを抑制するように電位のチューニングを行う。こうして、上側および下側チップ２０，３０の製造歩留まりを向上させる。
【００１９】
この実施の形態１の積層型半導体装置１において、２本のダイボンドフィルム２２ａ，２２ｂのそれぞれは、下側チップ２０の２つのヒューズ開口部２６ａ，２６ｂを完全に封止するように、下側チップ２０上に貼付される。換言すると、下側チップ２０のヒューズ開口部２６ａ，２６ｂの上方には、これを蓋するように配置されたダイボンドフィルム２２ａ，２２ｂが必ず存在する。したがって、モールド樹脂４０が上側チップ３０および下側チップ２０の周囲全体にモールドされるとき、下側チップ２０のヒューズ開口部２６ａ，２６ｂ内へのモールド樹脂の侵入が防止され、モールド成型時、湿気がヒューズ開口部２６ａ，２６ｂ内に侵入することはない。このように、実施の形態１によれば、下側チップ２０のヒューズ開口部２６ａ，２６ｂを封止するように、複数のダイボンドフィルム２２ａ，２２ｂがヒューズ開口部２６ａ，２６ｂの配置位置に合わせて貼付されるので、ヒューズ開口部２６ａ，２６ｂにおける耐湿性を改善することができ、積層型半導体装置１の信頼性を向上させることができる。
【００２０】
実施の形態２．
図３ないし図７を参照しながら、本発明の第２の実施の形態によるチップ積層方式の積層型半導体装置について説明する。実施の形態２による積層型半導体装置１は、１本のダイボンドフィルムを用いる点、および下側チップの複数のヒューズ開口部を中央部において互いに隣接して配置する点を除いて、第１の実施の形態による積層型半導体装置１と同様の構成を有するので、重複する内容については説明を省略する。
【００２１】
実施の形態２による積層型半導体装置１において、図３から明らかなように、下側チップ２０のヒューズ開口部２７ａないし２７ｄ（破線で示す）は、ｘ方向およびｙ方向においてそれぞれ２つずつ互いに隣接するように設けられている。しかも、これらのヒューズ開口部２７ａないし２７ｄは、下側チップ２０の中央部（中央領域）に集中して配置されている。このように、複数のヒューズ開口部２７ａないし２７ｄが互いに隣接して中央部に配置されていると、１本のダイボンドフィルム２３を用いて、複数のヒューズ開口部２７ａないし２７ｄを確実に、かつ容易に封止することができる。すなわち、上述した先行技術のように、ヒューズ開口部の一部領域だけがカバーされて、密閉された間隙部が生じることを防ぐことができる。
【００２２】
換言すると、複数のヒューズ開口部２７ａないし２７ｄが互いに隣接して中央部に配置されている場合、面積のより小さい１本のダイボンドフィルムを用いて、複数のヒューズ開口部２７ａないし２７ｄを容易に封止することができる。複数のヒューズ開口部２７ａないし２７ｄが１本のダイボンドフィルムで封止されるとき、図５に示すヒューズ開口部２７ａのｘ方向における最左端２８Ｌから、その右側に隣接して配置された別のヒューズ開口部２７ｃのｘ方向における最右端２８Ｒまでの距離（ｄｘ）は、ｘ方向におけるダイボンドフィルム２３自体の長さ（Ｌｘ）よりも短い。同様に、１本のダイボンドフィルム２３を用いて、複数のヒューズ開口部２７ａないし２７ｄを封止するためには、ｙ方向において、隣接するヒューズ開口部２７ａおよび２７ｂの互いに最も離れた端部の間の距離（ｄｙ）が、接着フィルムのｙ方向の長さ（Ｌｙ）より短いことが必要である。すなわち、この実施の形態２による積層型半導体装置１によれば、複数のヒューズ開口部２７ａないし２７ｄが互いに隣接して中央部に配置され、ｘ方向およびｙ方向などの任意の方向において、隣接するヒューズ開口部の互いに最も離れた端部の間の距離が、接着フィルム２３の長さより短い（ｄｘ＜Ｌｘ，ｄｙ＜Ｌｙ）。
【００２３】
さらに好適には、上述の端部間距離ｄｘ，ｄｙが、ダイボンドフィルム２３の半分の長さＬｘ，Ｌｙよりも小さくなるように（すなわち、ｄｘ＜１／２×Ｌｘ，ｄｙ＜１／２×Ｌｙ）、ヒューズ開口部を中央部に集中配置する（互いに隣接させて構成する）。
【００２４】
図３ないし図５に示す積層型半導体装置１は、そのヒューズ開口部２６ａないし２６ｄがｘ方向に長辺、ｙ方向に短辺を有する一方、図６および図７に示す積層型半導体装置１は、そのヒューズ開口部２６ａないし２６ｄがｘ方向に短辺、ｙ方向に長辺を有する以外は同様の積層型半導体装置である。図６に示す積層型半導体装置１においても同様に、任意の方向において、下側チップ２０の隣接するヒューズ開口部２６の互いに最も離れた端部の間の距離が、ダイボンドフィルム２３の長さより短い。
【００２５】
こうして、各ヒューズ開口部２６ａないし２６ｄは、下側ダイボンドフィルム２３により確実に封止され、ヒューズ開口部２６ａないし２６ｄにおける耐湿性を改善し、積層型半導体装置１のパッケージ信頼性を向上させることができる。
【００２６】
なお、本発明について、表面実装可能なバンプメタルを含む基板を有する積層型半導体装置（基板型）を参照しながら、これまで説明してきたが、当業者ならば容易に理解されるように、本発明は、リードフレームを有する積層型半導体装置（リードフレーム型）などにも同様に適用することができる。
【００２７】
【発明の効果】
【課題を解決するための手段】
請求項１に記載の本発明によれば、第１の半導体チップのヒューズ開口部は、接着フィルムにより確実に封止され、モールド樹脂がヒューズ開口部内に侵入することを防止し、モールド成型時、ヒューズ開口部内への湿気の侵入を阻止し、ヒューズ開口部の耐湿性を実質的に改善することができる。
【００２８】
請求項２に記載の本発明によれば、一般にチップ周辺部に配置されたヒューズ開口部の配置位置に合わせて、複数の接着フィルムを用いて複数のヒューズ開口部を封止して、ヒューズ開口部の耐湿性を実質的に改善することができる。
【００２９】
請求項３に記載の本発明によれば、１つの接着フィルムを用いて、複数のヒューズ開口部を確実に、かつ容易に封止して、ヒューズ開口部の耐湿性を実質的に改善することができる。また、複数のヒューズ開口部を封止するために、より面積の小さい１つの接着フィルムを用いることができ、接着フィルムのコストを低減できる。
【００３０】
請求項４に記載の本発明によれば、上述した先行技術のように、ヒューズ開口部の一部領域だけがカバーされて、密閉された間隙部が生じることを防ぐことができる。
【図面の簡単な説明】
【図１】図１は、本発明の実施の形態１による集積型半導体装置の平面図であって、モールド樹脂を省略している。
【図２】図２は、図１のＩＩ−ＩＩ線からみた集積型半導体装置の断面図である。
【図３】図３は、本発明の実施の形態２による集積型半導体装置の平面図であって、モールド樹脂を省略している。
【図４】図４は、図３のＩＶ−ＩＶ線からみた集積型半導体装置の断面図である。
【図５】図５は、図３に示す下側チップとボンディングフィルムの配置関係を示す平面図である。
【図６】図６は、図３の集積型半導体装置の変形例を示す平面図であって、モールド樹脂を省略している。
【図７】図７は、図６のＶＩＩ−ＶＩＩ線からみた集積型半導体装置の断面図である。
【図８】図８は、従来式の集積型半導体装置の平面図であって、モールド樹脂を省略している。
【図９】図９は、図８のＩＸ−ＩＸ線からみた集積型半導体装置の断面図である。
【図１０】図１０は、従来式の集積型半導体装置の間隙部を示す拡大図である。
【符号の説明】
１…積層型半導体装置、１０…配線基板、１２…下側ダイボンドフィルム、１４，２４，３４…電極パッド、１５…金線ワイヤ、１６…バンプメタル、２０…下側チップ、２２ａ，２２ｂ，２３…上側ダイボンドフィルム、３０…上側チップ、４０…モールド樹脂、２５，３５…パッシベーション層、２６，２７，３６…ヒューズ開口部。[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a stacked semiconductor device in which a plurality of semiconductor chips are stacked and housed in one package.
[0002]
[Prior art]
2. Description of the Related Art As information communication devices such as mobile phones have become lighter and smaller and have higher performance in recent years, there is a strong demand for further miniaturization and higher functionality of semiconductor devices to be incorporated. In order to respond to the demand, a semiconductor device of a package system (MCP: Multi Chip Package) in which a plurality of semiconductor chips having different systems are combined and housed in one package is widely used. Among the MCP methods, there are a front-back mounting method in which semiconductor chips are mounted on the front and back surfaces of a lead frame, and a chip stacking method in which another small-area semiconductor chip is directly stacked on a large-area semiconductor chip. Further, chip-stacked stacked semiconductor devices include a stacked semiconductor device having a lead frame (lead frame type) and a stacked semiconductor device having a substrate including a surface mountable bump metal (substrate type). .
[0003]
Here, with reference to FIGS. 8 to 10, a description will be given of a conventional stacked semiconductor device (substrate type) of a conventional chip stacking system as an example. The stacked semiconductor device 101 includes a wiring board 110 made of glass epoxy resin or the like, and a semiconductor chip 120 having a larger area (simply attached to the wiring board 110 via a lower die bond film 112). , And “lower chip”), and a semiconductor chip 130 having a smaller area adhered to the lower chip 120 via an upper die bond film 122 made of a similar material (also simply referred to as “upper chip”). ).
[0004]
The lower chip 120 and the upper chip 130 typically have different systems, for example, SRAM, pseudo SRAM, DRAM, or flash memory chips, and any of these semiconductor chips can be arbitrarily adapted to the needs of the end user. In combination, one packaged stacked semiconductor device 101 is designed.
[0005]
The wiring board 110, the lower chip 120, and the upper chip 130 have a plurality of electrode pads 114, 124, 134 that can be wire-bonded on the upper surface, and the lower chip 120 and the upper chip 130 include gold wire 115. Is connected to the wiring board 110 via the. A plurality of bump metals 116 are provided on the lower surface of the wiring board 110 so that the stacked semiconductor device 101 can be surface-mounted on a peripheral device (not shown). Further, above the wiring board 110, the transfer mold resin surrounds the entire lower chip 120 and the upper chip 130 to protect the chips 120 and 130. (In FIG. 9, hatching of the mold resin 140 is omitted for easy understanding.)
[0006]
A semiconductor memory chip such as the above-described SRAM, pseudo SRAM, DRAM, or flash memory generally has passivation layers 125 and 135 all over the formed memory circuit, and has a passivation layer in a predetermined region around the chip. Have fuse openings 126 and 136 removed. In FIG. 8 where the mold resin 140 is omitted, the lower chip 120 has a fuse opening 126 in a region shown by a broken line, and the upper chip 120 has a fuse opening 136 in a region shown by a solid line. Further, a plurality of fuse lines (not shown) are formed on the bottom surfaces of the fuse openings 126 and 136. Then, a predetermined fuse line is irradiated with laser light through the fuse openings 126 and 136 and cut, so that a memory circuit that does not operate normally due to a defect at the time of manufacture or the like can be replaced with a redundant circuit, or a potential with respect to a reference voltage can be replaced. Tuning is performed so as to suppress variations in the potential. Thus, the manufacturing yield of the upper and lower chips 120 and 130 is improved.
[0007]
As described above, since the molding resin 140 is molded so as to cover the entire upper chip 130 and the lower chip 120, as shown in the enlarged view of FIG. The resin 140 penetrates without gaps and protects the fuse line where the passivation layer 135 is not formed and the circuit elements in the vicinity thereof.
[0008]
[Problems to be solved by the invention]
However, as described above, the combination of the upper chip 130 and the lower chip 120 is determined according to the final desired specification of the stacked semiconductor device, and the arrangement position of the upper chip 130 with respect to the lower chip 120 and The position of the fuse opening 126 of the lower chip 120 with respect to the die bond film 122 depends on the combination of the upper chip 130 and the lower chip 120. At this time, as shown in FIGS. 9 and 10, when the upper die bond film 122 is disposed so as to cover only a part of the fuse opening 126 of the lower chip 120, the molding resin 140 is The fuse openings 126 of the 120 may not be completely filled, resulting in a sealed gap 150. The air, especially moisture, sealed in the gap 150 repeatedly expands and contracts during the temperature cycle test including the HAST test and the reflow solder mounting, and is greatly applied to the fuse line where the passivation layer 135 is not formed and the circuit elements in the vicinity thereof. Package reliability, such as moisture resistance, is significantly impaired.
[0009]
Therefore, the present invention has been made to solve such a problem, and a die bond film must be disposed above the fuse opening of the lower chip so that moisture does not enter the fuse opening of the lower chip. Accordingly, an object of the present invention is to provide a stacked semiconductor device in which the moisture resistance in the fuse opening of the lower chip is improved and the package reliability is improved.
[0010]
[Means for Solving the Problems]
In order to achieve this object, the present invention according to claim 1 is a stacked semiconductor device formed by stacking a plurality of semiconductor chips, the first semiconductor chip having at least one fuse opening. And at least one adhesive film attached on the first semiconductor chip so as to seal the fuse opening, and a second semiconductor chip disposed above the first semiconductor chip via the adhesive film. Is provided. As a result, the fuse opening of the first semiconductor chip is securely sealed by the adhesive film, preventing the mold resin from entering the fuse opening, and preventing moisture from entering the fuse opening during molding. This can substantially improve the moisture resistance of the fuse opening.
[0011]
According to the second aspect of the present invention, the plurality of fuse openings are sealed with the plurality of adhesive films. Thus, a plurality of fuse openings can be sealed with a plurality of adhesive films in accordance with the arrangement position of the fuse openings generally arranged in the periphery of the chip.
[0012]
According to the third aspect of the present invention, the plurality of fuse openings are arranged adjacent to each other at the center of the first semiconductor chip and are sealed with one adhesive film. Thus, a plurality of fuse openings can be reliably and easily sealed using one adhesive film. Moreover, in order to seal the plurality of fuse openings, one adhesive film having a smaller area can be used, and the cost of the adhesive film can be reduced.
[0013]
According to the present invention, the adhesive film has an area equal to or smaller than the area of the second semiconductor chip, and covers all the fuse openings on the first semiconductor chip. Therefore, it is possible to prevent the formation of a sealed gap by covering only a part of the fuse opening as in the prior art described above.
[0014]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of a stacked semiconductor device according to the present invention will be described with reference to the accompanying drawings. In the description of each embodiment, terms indicating directions (for example, “upper”, “lower”, “right”, “left”, “x direction”, and “y direction” for easy understanding) ) Is used as appropriate, but this is only for explanation, and these terms do not limit the present invention.
[0015]
Embodiment 1 FIG.
A stacked semiconductor device (substrate type) of a chip stacking type according to a first embodiment of the present invention will be described with reference to FIGS. The stacked semiconductor device 1 includes a wiring board 10 made of glass epoxy resin or the like, and a semiconductor chip 20 having a larger area (simply attached to the wiring board 10 via a lower die bond film 12). , "Lower chip"), and a semiconductor chip 30 having a smaller area (simply referred to as a "lower chip"), which is bonded on the lower chip 20 via two upper die bond films 22a and 22b made of the same material. Also referred to as an "upper chip."
[0016]
The lower chip 20 and the upper chip 30 are, for example, an SRAM, a pseudo SRAM, a DRAM, a flash memory chip, or the like, and a combination thereof depends on specifications and functions desired by an end user. The memory chips arbitrarily combined in this manner are stacked and packaged to form one stacked semiconductor device 1.
[0017]
The wiring board 10, the lower chip 20, and the upper chip 30 have a plurality of electrode pads 14, 24, 34 that can be wire-bonded on the upper surface. (The gold wire 15 is omitted in FIG. 1). Further, a plurality of bump metals 16 are provided on the lower surface of the wiring board 10 so that the stacked semiconductor device 1 can be surface-mounted on a peripheral device (not shown). Further, a transfer mold resin 40 is molded above the wiring board 10 so as to surround the lower chip 20 and the upper chip 30 as a whole, thereby protecting the chips 20 and 30. (For the sake of simplicity, the mold resin 40 is omitted in FIG. 1 and the hatching is omitted in FIG. 2.) The mold resin 40 has no gap between the two upper die bond films 22a and 22b. It is preferable that the upper die-bonding films 22a and 22b have a greater thickness than the lower die-bonding film 12 in order to facilitate the filling.
[0018]
In the first embodiment, the upper chip 20 and the upper chip 30 have passivation layers 25 and 35 all over the formed memory circuit (not shown), as shown by broken lines and solid lines in FIG. 1, respectively. And fuse openings 26 and 36 formed by etching the passivation layers 25 and 35 in a predetermined region around the chip. A plurality of fuse lines (not shown) are formed on the bottom surfaces of the fuse openings 26 and 36. Then, by performing laser trimming through the fuse openings 26 and 36, a memory circuit that does not operate normally due to a defect at the time of manufacturing or the like is replaced with a redundant circuit, or the potential is tuned so as to suppress variation in potential with respect to a reference voltage. Do. Thus, the production yield of the upper and lower chips 20, 30 is improved.
[0019]
In the stacked semiconductor device 1 according to the first embodiment, the two die bonding films 22a and 22b are respectively connected to the lower chip so that the two fuse openings 26a and 26b of the lower chip 20 are completely sealed. 20. In other words, above the fuse openings 26a, 26b of the lower chip 20, there are always the die bond films 22a, 22b arranged to cover the fuse openings 26a, 26b. Therefore, when the molding resin 40 is molded over the entire periphery of the upper chip 30 and the lower chip 20, the intrusion of the molding resin into the fuse openings 26a, 26b of the lower chip 20 is prevented. Does not enter the fuse openings 26a and 26b. As described above, according to the first embodiment, the plurality of die bond films 22a and 22b are aligned with the positions of the fuse openings 26a and 26b so as to seal the fuse openings 26a and 26b of the lower chip 20. Since it is attached, the moisture resistance in the fuse openings 26a and 26b can be improved, and the reliability of the stacked semiconductor device 1 can be improved.
[0020]
Embodiment 2 FIG.
A stacked semiconductor device of a chip stacking type according to a second embodiment of the present invention will be described with reference to FIGS. The stacked semiconductor device 1 according to the second embodiment is similar to the first embodiment except that a single die bond film is used and a plurality of fuse openings of the lower chip are arranged adjacent to each other at the center. Since the configuration is the same as that of the stacked semiconductor device 1 according to the embodiment, the description of the same content will not be repeated.
[0021]
In the stacked semiconductor device 1 according to the second embodiment, as is apparent from FIG. 3, two fuse openings 27a to 27d (shown by broken lines) of the lower chip 20 are adjacent to each other in the x direction and the y direction. It is provided to be. In addition, these fuse openings 27a to 27d are arranged in a concentrated manner in the central portion (central region) of the lower chip 20. As described above, when the plurality of fuse openings 27a to 27d are arranged adjacent to each other at the center, the plurality of fuse openings 27a to 27d can be reliably and easily formed using one die bond film 23. Can be sealed. That is, as in the above-described prior art, only a partial area of the fuse opening is covered, so that a sealed gap can be prevented from being generated.
[0022]
In other words, when a plurality of fuse openings 27a to 27d are arranged adjacent to each other in the center, the plurality of fuse openings 27a to 27d can be easily sealed using one die bond film having a smaller area. Can be stopped. When the plurality of fuse openings 27a to 27d are sealed with one die bond film, another fuse disposed adjacent to the right side from the leftmost end 28L in the x direction of the fuse opening 27a shown in FIG. The distance (dx) to the rightmost end 28R in the x direction of the opening 27c is shorter than the length (Lx) of the die bond film 23 itself in the x direction. Similarly, in order to seal the plurality of fuse openings 27a to 27d using one die-bonding film 23, the distance between the ends of the adjacent fuse openings 27a and 27b which are farthest from each other in the y-direction. Is required to be shorter than the length (Ly) of the adhesive film in the y direction. That is, in the stacked semiconductor device 1 according to the second embodiment, the plurality of fuse openings 27a to 27d are arranged at the center adjacent to each other, and are adjacent to each other in an arbitrary direction such as the x direction and the y direction. The distance between the farthest ends of the fuse openings is shorter than the length of the adhesive film 23 (dx <Lx, dy <Ly).
[0023]
More preferably, the distances dx and dy between the ends are smaller than half the lengths Lx and Ly of the die bond film 23 (that is, dx <1/2 × Lx and dy <1/2 ×). Ly), the fuse openings are centrally arranged (configured adjacent to each other).
[0024]
In the stacked semiconductor device 1 shown in FIGS. 3 to 5, the fuse openings 26a to 26d have long sides in the x direction and short sides in the y direction, while the stacked semiconductor devices 1 shown in FIGS. , Except that the fuse openings 26a to 26d have short sides in the x direction and long sides in the y direction. Similarly, in the stacked semiconductor device 1 illustrated in FIG. 6, the distance between the ends of the adjacent fuse openings 26 of the lower chip 20 that are farthest from each other in any direction is shorter than the length of the die bond film 23. .
[0025]
Thus, each of the fuse openings 26a to 26d is securely sealed by the lower die bond film 23, the moisture resistance in the fuse openings 26a to 26d is improved, and the package reliability of the stacked semiconductor device 1 is improved. it can.
[0026]
Although the present invention has been described above with reference to a stacked semiconductor device (substrate type) having a substrate including a bump metal that can be surface-mounted, as will be easily understood by those skilled in the art, The invention can be similarly applied to a stacked semiconductor device (lead frame type) having a lead frame.
[0027]
【The invention's effect】
[Means for Solving the Problems]
According to the first aspect of the present invention, the fuse opening of the first semiconductor chip is securely sealed by the adhesive film to prevent the mold resin from entering the fuse opening. Moisture can be prevented from entering the fuse opening, and the moisture resistance of the fuse opening can be substantially improved.
[0028]
According to the present invention as set forth in claim 2, the plurality of fuse openings are generally sealed with a plurality of adhesive films in accordance with the arrangement positions of the fuse openings arranged around the chip. The moisture resistance of the part can be substantially improved.
[0029]
According to the third aspect of the present invention, the plurality of fuse openings are securely and easily sealed using one adhesive film, and the moisture resistance of the fuse openings is substantially improved. Can be. Moreover, in order to seal the plurality of fuse openings, one adhesive film having a smaller area can be used, and the cost of the adhesive film can be reduced.
[0030]
According to the present invention, only a partial area of the fuse opening is covered as in the above-described prior art, and it is possible to prevent a sealed gap from being generated.
[Brief description of the drawings]
FIG. 1 is a plan view of an integrated semiconductor device according to a first embodiment of the present invention, in which a mold resin is omitted.
FIG. 2 is a sectional view of the integrated semiconductor device taken along line II-II of FIG. 1;
FIG. 3 is a plan view of an integrated semiconductor device according to a second embodiment of the present invention, in which a mold resin is omitted.
FIG. 4 is a sectional view of the integrated semiconductor device taken along line IV-IV in FIG. 3;
FIG. 5 is a plan view showing an arrangement relationship between a lower chip and a bonding film shown in FIG. 3;
FIG. 6 is a plan view showing a modified example of the integrated semiconductor device of FIG. 3, in which a mold resin is omitted.
FIG. 7 is a sectional view of the integrated semiconductor device taken along line VII-VII in FIG. 6;
FIG. 8 is a plan view of a conventional integrated semiconductor device, omitting a mold resin.
FIG. 9 is a sectional view of the integrated semiconductor device taken along line IX-IX in FIG. 8;
FIG. 10 is an enlarged view showing a gap portion of a conventional integrated semiconductor device.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Laminated semiconductor device, 10 ... Wiring board, 12 ... Lower die bond film, 14, 24, 34 ... Electrode pad, 15 ... Gold wire, 16 ... Bump metal, 20 ... Lower chip, 22a, 22b, 23 ... upper die bonding film, 30 ... upper chip, 40 ... mold resin, 25, 35 ... passivation layer, 26, 27, 36 ... fuse opening.

Claims (4)

複数の半導体チップを積層して形成された積層型半導体装置であって、
少なくとも１つのヒューズ開口部を有する第１の半導体チップと、
ヒューズ開口部を封止するように第１の半導体チップ上に貼付された少なくとも１つの接着フィルムと、
接着フィルムを介して第１の半導体チップの上方に配置された第２の半導体チップとを備えることを特徴とする積層型半導体装置。A stacked semiconductor device formed by stacking a plurality of semiconductor chips,
A first semiconductor chip having at least one fuse opening;
At least one adhesive film affixed on the first semiconductor chip to seal the fuse opening;
A second semiconductor chip disposed above the first semiconductor chip with an adhesive film interposed therebetween. 請求項１に記載の積層型半導体装置であって、
複数のヒューズ開口部が、複数の接着フィルムにより封止されることを特徴とする積層型半導体装置。The stacked semiconductor device according to claim 1, wherein:
A stacked semiconductor device, wherein a plurality of fuse openings are sealed with a plurality of adhesive films. 請求項１に記載の積層型半導体装置であって、
複数のヒューズ開口部が、第１の半導体チップの中央部において互いに隣接して配置され、１つの接着フィルムにより封止されることを特徴とする積層型半導体装置。The stacked semiconductor device according to claim 1, wherein:
A stacked semiconductor device, wherein a plurality of fuse openings are arranged adjacent to each other at a central portion of a first semiconductor chip and are sealed with one adhesive film. 請求項３に記載の積層型半導体装置であって、
接着フィルムは、第２の半導体チップの面積と同一もしくは小さい面積を有し、第１の半導体チップ上のヒューズ開口部すべてを覆うことを特徴とする積層型半導体装置。The stacked semiconductor device according to claim 3, wherein:
A stacked semiconductor device, wherein the adhesive film has an area equal to or smaller than the area of the second semiconductor chip and covers all the fuse openings on the first semiconductor chip.
JP2002178821A 2002-06-19 2002-06-19 Stacked-layer type semiconductor device Pending JP2004022982A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140042589A1 (en) * 2012-08-10 2014-02-13 Elpida Memory, Inc. Semiconductor device
KR20190025097A (en) * 2017-08-28 2019-03-11 삼성전자주식회사 Semiconductor package and method of fabricating the same

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140042589A1 (en) * 2012-08-10 2014-02-13 Elpida Memory, Inc. Semiconductor device
US9117741B2 (en) * 2012-08-10 2015-08-25 Ps4 Luxco S.A.R.L. Semiconductor device
KR20190025097A (en) * 2017-08-28 2019-03-11 삼성전자주식회사 Semiconductor package and method of fabricating the same
KR102419154B1 (en) * 2017-08-28 2022-07-11 삼성전자주식회사 Semiconductor package and method of fabricating the same

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