JP2004022890A - Multilayer circuit board - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an inexpensive multilayer circuit board which is suited for the prevention of noise intrusion from outside, high-density wiring and increased pins in the multilayer circuit board on which a plurality of signal conductors having different characteristic impedances are formed. <P>SOLUTION: On the main surface of an insulating substrate 2, a lower grounding conductor layer 3, a first signal conductor layer 4, an inner layer grounding conductor layer 5, a second signal conductor layer 6 and an upper grounding conductor layer 7 are laminated in order, respectively, via an insulating layer 8. The first and second signal conductor layers 4 and 6 are composed of a plurality of signal conductors including signal conductors 4a to 4c and 6a to 6c having different characteristic impedances. The inner layer grounding conductor layer 5 has conductor non-forming parts 5b and 5c formed at sites immediately over or under the signal conductors 4a and 6c having characteristic impedances larger than 70Ω among the plurality of signal conductors 4a to 4c and 6a to 6c. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a multilayer wiring board including a signal line layer including a plurality of signal lines having different widths, and a ground conductor layer formed above and below the signal line layer.
[0002]
[Prior art]
FIG. 2 is a sectional view of a conventional multilayer wiring board. In FIG. 2, 11 is a multilayer wiring board, 12 is an insulating substrate, 13 is a lower ground conductor layer formed on one main surface of the insulating substrate 12 substrate, and 14 is a first ground conductor layer laminated on the lower ground conductor layer 13. 14a is a first signal line in the signal line layer 14, 14b is a second signal line in the signal line layer 14, 15 is an inner ground conductor layer laminated above the signal line layer 14, Reference numeral 16 denotes a second signal line layer laminated above the inner ground conductor layer 15, and 17 denotes an upper ground conductor layer laminated above the second signal line layer 16. Further, the lower ground conductor layer 13, the first signal line layer 14, the inner ground conductor layer 15, the second signal line layer 16, and the upper ground conductor layer 17 are stacked with an insulating layer 18 interposed therebetween. 18a is a first insulating layer, 18b is a second insulating layer, 18c is a third insulating layer, and 18d is a fourth insulating layer.
[0003]
In this case, the second signal line layer 16 includes one third signal line 16a.
[0004]
A semiconductor element such as an IC or an LSI is provided on the upper surface of the multilayer wiring board 11, and its input / output electrode pads are electrically connected to the first signal line 14a, the second signal line 14b, and the third signal line 16a. It is connected to and mounted.
[0005]
As shown in FIG. 2, a lower ground conductor layer 13, an inner ground conductor layer 15, and an upper ground conductor layer 17 are provided above and below the first and second signal line layers 14, 16 via an insulating layer 18. And has a stripline structure. In this case, in order to form a plurality of signal lines having different characteristic impedances in one signal line layer, it is necessary to make the width of the signal line having a large characteristic impedance smaller than that of the signal line having a small characteristic impedance. For example, when a signal line A having a characteristic impedance of 50Ω and a signal line B having a characteristic impedance of 60Ω are formed in one signal line layer, the width of the signal line A is 31 μm, whereas the width of the signal line A is 31 μm. Is 18 μm, which must be smaller than the width of the signal line A.
[0006]
FIG. 3 shows a multilayer wiring board having a structure in which a plurality of signal lines having different characteristic impedances are formed in one signal line layer (see JP-A-2001-284827). In FIG. 3, 21 is a multilayer wiring board, 22 is an insulating substrate, 23 is a lower ground conductor layer, 24 is a signal line layer, 24a is a first signal line, 24b is a second signal line, and 24c is a third signal line. The line, 27 is an upper ground conductor layer, 27a is a conductor non-formed portion, 28 is an insulating layer, 28a is a first insulating layer, and 28b is a second insulating layer.
[0007]
As shown in FIG. 3, as one signal line layer is provided with a plurality of signal lines having different characteristic impedances, a portion of the upper ground conductor layer 27 immediately above the first signal line 24a requiring a high characteristic impedance value is provided. It is proposed to provide a conductor non-formed portion 27a.
[0008]
[Problems to be solved by the invention]
However, in the above-described conventional wiring board 11 of FIG. 2, if a signal line having a larger characteristic impedance is to be formed, the width of the signal line becomes fine, and it becomes difficult to form the signal line in manufacturing. There was a problem. In addition, when the width of the signal line is reduced, it becomes difficult to control the characteristic impedance, so that the value of the characteristic impedance varies, and there is a problem that the transmission efficiency of the high-frequency signal is reduced.
[0009]
There is also a configuration in which signal lines having different characteristic impedance values are provided on separate signal line layers and the thickness of an insulating layer between the signal line layer and the ground conductor layer above and below the signal line layer is adjusted. There has been a problem that the number of line layers increases and the multilayer wiring board becomes thicker. In addition, since the thickness of the insulating layer is increased, there is a problem that the manufacturing cost is increased.
[0010]
Therefore, in order to solve the above-mentioned problem, a multilayer wiring board 21 having a configuration as shown in FIG. 3 has been proposed. In this configuration, it is possible to form signal lines 24a to 24c having different characteristic impedances on one signal line layer 24. The presence of the non-formed portion 27a makes it impossible to protect the first signal line 24a from external noise. As a result, there is a problem that the noise affects the semiconductor elements connected to the first to third signal lines 24a to 24c, and it is not possible to cope with an increase in the operating speed of the semiconductor elements.
[0011]
Also, since there is only one signal line layer 24, a jumper layer for cross wiring cannot be provided, that is, when a plurality of signal line layers are provided and the upper signal line and the lower signal line intersect, etc. Since the upper signal line and the lower signal line cannot be connected via the through conductor, there is a problem that it is difficult to cope with an increase in the number of pins of the semiconductor element and a high-speed operation processing.
[0012]
Therefore, the present invention has been completed in view of the above-mentioned conventional problems, and an object of the present invention is to provide a multilayer wiring board having a plurality of signal lines having different characteristic impedances, preventing intrusion of noise from the outside and high-density wiring. An object of the present invention is to provide a low-cost multi-layer wiring board which can realize a higher number of pins and more pins.
[0013]
[Means for Solving the Problems]
In the multilayer wiring board of the present invention, the lower ground conductor layer, the first signal line layer, the inner layer ground conductor layer, the second signal line layer, and the upper ground conductor layer are respectively provided on the main surface of the insulating substrate via the insulating layer. Are sequentially laminated, the first and second signal line layers are each composed of a plurality of signal lines including those having different characteristic impedances, and the inner ground conductor layer has a characteristic impedance of the plurality of signal lines. A conductor-free portion is provided immediately above or immediately below the signal line, which is larger than 70Ω.
[0014]
In the multilayer wiring board of the present invention, since a plurality of signal lines having different characteristic impedances are formed in one signal line layer, high-density wiring of the signal lines becomes possible. In addition, it becomes possible to provide a jumper wire of cross wiring, that is, when a plurality of signal line layers are provided and the upper signal line and the lower signal line intersect, the upper signal line and the lower signal line are connected to each other. Can be connected via a through conductor, and the number of pins of the semiconductor element can be increased.
[0015]
In addition, since the conductor non-forming portion is provided immediately above or directly below the signal line having a characteristic impedance of more than 70Ω among the plurality of signal lines, the upper ground conductor layer above or below the conductor non-forming portion or The signal line has a stripline structure due to the lower ground conductor layer and the signal line having a characteristic impedance of more than 70Ω. As a result, the distance between the signal line having a characteristic impedance of greater than 70Ω and the upper ground conductor layer or the lower ground conductor layer increases, and the electrical capacitance decreases, thereby increasing the characteristic impedance value. In this case, the width of the signal line becomes larger when trying to obtain the same characteristic impedance value than when there is no conductor non-formed portion. Therefore, the width of the signal line having a large characteristic impedance can be increased as compared with the related art. As a result, control of the characteristic impedance is facilitated, and a signal line with small variation in the characteristic impedance can be formed.
[0016]
Further, since the upper ground conductor layer and the lower ground conductor layer are laminated above and below the first signal line layer, the inner ground conductor layer, and the second signal line layer, the influence of external noise is reduced. A signal line that is not affected by the signal can be formed. Therefore, it is possible to cope with an increase in the operating speed of the semiconductor element connected to the signal line.
[0017]
In the multilayer wiring board of the present invention, preferably, the inner-layer grounded conductor layer has a characteristic impedance of a portion of the plurality of signal lines immediately above or immediately below the signal line having a characteristic impedance of 40Ω or less and having a small interval with the signal line. It is characterized by having.
[0018]
In the multilayer wiring board of the present invention, since the inner ground conductor layer has a portion where the distance from the signal line is reduced immediately above or immediately below the signal line having a characteristic impedance of 40Ω or less among the plurality of signal lines, At the portion, the electrical capacitance with the signal line having the characteristic impedance of 40Ω or less increases, and the characteristic impedance value decreases. In this case, the width of the signal line becomes smaller when trying to obtain the same characteristic impedance value as compared with a case where there is no portion with a small interval. Therefore, the width of a signal line having a small characteristic impedance can be made smaller than that of a conventional signal line, and can be closer to the width of a signal line having a larger characteristic impedance. As a result, the width of a plurality of signal lines having different characteristic impedances is extremely close to or substantially equal to each other in combination with the operation and effect of providing the conductor non-formed portion as described above. Becomes possible.
[0019]
BEST MODE FOR CARRYING OUT THE INVENTION
The multilayer wiring board of the present invention will be described in detail below. FIG. 1 is a sectional view of an example of an embodiment of a multilayer wiring board of the present invention. In FIG. 1, 1 is a multilayer wiring board, 2 is an insulating substrate, 3 is a lower ground conductor layer, 4 is a first signal line layer, 4a is a first signal line, 4b is a second signal line, and 4c is a second signal line. Three signal lines, 5 is an inner ground conductor layer, 5a is an internal ground conductor, 5b is a first conductor non-formed portion, 5c is a second conductor non-formed portion, and 5d is a small interval portion of the internal ground conductor 5a. . Reference numeral 6 denotes a second signal line layer, 6a denotes a fourth signal line, 6b denotes a fifth signal line, 6c denotes a sixth signal line, 7 denotes an upper ground conductor layer, 8 denotes an insulating layer, and 8a denotes a One insulating layer, 8b is a second insulating layer, 8c is a third insulating layer, and 8d is a fourth insulating layer.
[0020]
A semiconductor element (not shown) such as an IC or an LSI is mounted on the upper part of the multilayer wiring board 1 of the present invention while its electrodes are electrically connected to the signal wirings 4a to 4c and 6a to 6c. The semiconductor element may not be mounted on the multilayer wiring board 1.
[0021]
The insulating substrate 2 is made of a ceramic substrate such as alumina (Al ₂ O ₃ ) ceramic, mullite (3Al ₂ O ₃ .2SiO ₂ ) ceramic, aluminum nitride (AlN) ceramic, glass ceramic, or the like, and a through conductor such as a through-hole conductor. It is preferable because it can be formed by simultaneous firing. Also, ethylene tetrafluoride resin (polytetrafluoroethylene; PTFE), ethylene tetrafluoride / ethylene copolymer resin (tetrafluoroethylene-ethylene copolymer resin; ETFE), ethylene tetrafluoride / perfluoroalkoxyethylene copolymer resin A substrate made of a fluororesin such as (tetrafluoroethylene-perfluoroalkylvinylether copolymer resin; PFA), a substrate made of a glass epoxy resin, a substrate made of a resin such as polyimide, or the like may be used.
[0022]
Conductive layers of lower ground conductor layer 3, first signal line layer 4, internal ground conductor 5a of inner ground conductor layer 5, second signal line layer 6, and upper ground conductor layer 7 formed on the upper surface of insulating substrate 2. Are formed by a thin film forming method, a metallizing method using a printing paste, a metal foil method, a plating method, or the like. Further, these forming methods may be combined.
[0023]
In the case of a thin film formation method, a conductor layer is formed by a sputtering method, an evaporation method, a CVD method, or the like. For example, a conductor layer having a four-layer structure of a Ti layer, a Ti-W alloy layer, a Cu layer, and a Cr layer is formed from the lower side. Thereafter, this conductor layer is formed into a predetermined pattern by patterning by photolithography and etching. In the case of the metallization method, a metal paste containing at least one of W, Mo, Mn and Cu is formed by printing and applying a desired pattern by a screen printing method and sintering. In the case of the metal foil method, a conductor layer is formed by patterning a metal foil of Cu or the like previously attached to the insulating substrate 2 by a photolithography method using a dry film or the like and an etching method. Alternatively, it is formed by transferring a metal foil patterned in advance onto the insulating substrate 2. In the case of the plating method, a Cu plating layer or the like is formed by an electroless plating method or an electrolytic plating method, and is formed by pattern processing.
[0024]
The thickness of the conductor layer is preferably 0.5 to 50 μm, and if it is less than 0.5 μm, the conduction resistance of the conductor layer tends to increase, and if it exceeds 50 μm, it becomes difficult to process into a fine signal line.
[0025]
The width of each of the signal lines 4a to 4c and 6a to 6c in the first signal line layer 4 and the second signal line layer 6 is preferably 10 to 50 μm. If it is smaller than 10 μm, disconnection of the signal lines 4a to 4c and 6a to 6c tends to occur, and if it is larger than 50 μm, high-density wiring of the signal lines 4a to 4c and 6a to 6c becomes difficult.
[0026]
In the present invention, the first and second signal line layers 4 and 6 are composed of a plurality of signal lines including signal lines 4a to 4c and 6a to 6c having different characteristic impedances, respectively. Of the signal lines 4a to 4c and 6a to 6c, the conductor non-forming portions 5b and 5c are provided immediately above or directly below the signal lines 4a and 6c whose characteristic impedance is greater than 70Ω. In the present invention, preferably, the inner ground conductor layer 5 has a portion immediately above (or immediately below) the signal line 4b having a characteristic impedance of 40Ω or less in a plurality of signal lines and having a small interval with the signal line 4b. ing.
[0027]
The widths of the first conductor non-formed portion 5b and the second conductor non-formed portion 5c of the present invention are substantially the same as the widths of the corresponding signal line layers 4a and 6c. It can be smaller or larger than the width of the layers 4a, 6c. Preferably, the width of the first conductor non-formed portion 5b and the second conductor non-formed portion 5c is slightly larger than the width of the corresponding signal line layers 4a and 6c. In this case, almost no capacitance component occurs between the ends of the signal line layers 4a and 6c and the ends of the first conductor non-formed portion 5b and the second conductor non-formed portion 5c. The characteristic impedance can be increased without reducing the width of 6c.
[0028]
Although the characteristic impedance of the first signal line 4a and the sixth signal line 6c is 70Ω or more, if it is more than 50Ω and less than 70Ω, the first and second conductor non-formed portions 5b and 5c are provided and directly above or below. When the thickness of the insulating layer is increased, the widths of the first signal line 4a and the sixth signal line 6c, which are originally large, are further increased, and high-density mounting becomes difficult. It is not necessary to provide the forming parts 5b and 5c.
[0029]
In addition, the characteristic impedance of the second signal line 4b is 40Ω or less. However, if the characteristic impedance of the second signal line 4b is less than 50Ω and exceeds 40Ω, the width of the second signal line 4b becomes unnecessarily large if the thickness of the insulating layer immediately above or below is reduced. Since it becomes small and it becomes difficult to control the characteristic impedance, there is no need to provide a portion (small interval portion 5d) immediately above the second signal line 4b of the inner ground conductor layer 5 and having a small interval with the signal line 4b.
[0030]
The interval between the small interval portions 5d is preferably 3 to 50 μm. If it is less than 3 μm, insulation failure is likely to occur. If it exceeds 50 μm, the contact resistance of the penetrating conductor that conducts between the conductor layers tends to increase, and the transmission speed of electric signals tends to decrease.
[0031]
The conductor non-formed portions 5b and 5c and the small interval portions 5d may be formed over the entire length of the signal line, or may be provided on a part of the signal line.
[0032]
The lower ground conductor layer 3 and the upper ground conductor layer 7 are formed so as to cover the entirety of the plurality of signal lines 4 a to 4 c and 6 a to 6 c of the first and second signal line layers 4 and 6. With this configuration, intrusion of noise from the outside can be prevented. The upper ground conductor layer 7 is formed so as to cover all the signal lines 4a to 4c and 6a to 6c. As a result, all of the signal lines 4a to 4c and 6a to 6c have a stripline structure by the upper ground conductor layer 7, the lower ground conductor layer 3, and the internal ground conductor 5a, and prevent external noise from entering. it can.
[0033]
Further, the lower grounding conductor layer 3 may be formed on substantially the entire upper surface of the insulating substrate 2. In this case, the signal lines 4 a to 4 c and 6 a to 6 c are restricted by the size of the lower grounding conductor layer 3. It can be formed without. The upper ground conductor layer 7 may be formed so as to cover substantially the entire upper surface of the fourth insulating layer 8d.
[0034]
The insulating layer 8 is made of polyimide, BCB (benzocyclobutene), an epoxy resin, a fluorine-based resin, or the like, and is formed by applying a spin coating method, a roll coating method, a die coating method, a printing method, or the like. Alternatively, it may be formed by applying a resin processed into a film. The thickness of each of the insulating layers 8a to 8d is preferably 3 to 50 μm. If it is less than 3 μm, insulation failure is likely to occur. On the other hand, if it exceeds 50 μm, the contact resistance of a through hole (not shown) for conduction between the conductor layers tends to increase, and the transmission speed of an electric signal tends to decrease.
[0035]
The insulating layer 8 is preferably formed in two or three layers in order to prevent insulation failure due to the generation of pinholes in the manufacturing process. As a processing method, a method of forming a pattern including through holes by imparting photosensitivity to the resin itself and exposing and developing the resin by photolithography is preferable. Alternatively, a resist layer may be applied on the insulating layer 8, patterned by photolithography, and a pattern including through holes may be formed by etching. Further, it may be formed by a printing method. Also, pattern processing may be performed by an excimer laser or the like. Further, the above processing methods may be combined. The same type of resin may be used for each of the insulating layers 8a to 8d, or different insulating layers may be used.
[0036]
【Example】
An embodiment of the multilayer wiring board 1 of the present invention will be described below.
[0037]
(Example 1)
The multilayer wiring board 1 was configured as follows. A substantially 3.3 μm-thick lower grounding conductor layer composed of a four-layered conductor layer of a Ti layer, a Ti—W alloy layer, a Cu layer, and a Cr layer over substantially the entire upper surface of the insulating substrate 2 made of alumina ceramics. 3 was formed by a sputtering method. A first insulating layer 8a made of polyimide and having a thickness of 20 μm is formed on the lower grounding conductor layer 3 by photolithography, and a Ti layer, a Ti—W alloy layer, and a Cu layer are formed on the first insulating layer 8a from below. A first signal line layer 4 having a thickness of 3.2 μm and made of a four-layered conductor layer composed of a Cr layer was formed by a sputtering method. Similarly, a second insulating layer 8b and an inner ground conductor layer 5, a third insulating layer 8c and a second signal line layer 6, a fourth insulating layer 8d, and an upper ground conductor layer 7 were formed. The upper ground conductor layer 7 was formed on substantially the entire upper surface of the fourth insulating layer 8d.
[0038]
Immediately above the first signal line 4a having a characteristic impedance of 70Ω and a width of 20 μm, a first conductor non-forming portion 5b having a width of 80 μm is formed over the entire length (about 10 mm). The width of the first signal line 4a was larger than the width of 10 μm of the first signal line 4a without the first conductor non-formed portion 5b. Similarly, immediately below the sixth signal line 6c having a characteristic impedance of 70Ω and a width of 20 μm, a second conductor non-forming portion 5c having a width of 80 μm is formed over the entire length (about 10 mm). Accordingly, the width of the sixth signal line 6c is larger than the width 10 μm of the sixth signal line 6c when the second conductor non-formed portion 5c is not provided.
[0039]
Accordingly, when the first conductor non-formed portion 5b and the second conductor non-formed portion 5c are not provided, the characteristic impedance becomes unstable because the widths of the first signal line 4a and the sixth signal line 6c are small. The transmission loss (transmission loss) when a 1 GHz high-frequency signal was transmitted was about -2 dB, but the transmission loss (transmission loss) was improved to about -1 dB by the above configuration of the present embodiment.
[0040]
(Example 2)
In addition to the configuration of the first embodiment, a small gap having the same width as the width of the second signal line 4b is provided on the inner ground conductor layer 5 immediately above the second signal line 4b having a characteristic impedance of 35Ω and a width of 30 μm. The portion 5d (interval 10 μm) was formed over the entire length (10 mm) of the second signal line 4b. Thereby, the width of the second signal line 4b is smaller than the width of 50 μm of the second signal line 4b without the small interval portion 5d.
[0041]
Therefore, the width of the first signal line 4a having the characteristic impedance of 70Ω is 20 μm, the width of the second signal line 4b having the characteristic impedance of 35Ω is 30 μm, and the width of the third signal line 4c having the characteristic impedance of 50Ω is 20 μm. , The difference between their widths became smaller. This is because the first signal line 4a has a width of 10 μm, the second signal line 4b has a width of 50 μm, and the first conductor non-formed portion 5b, the second conductor non-formed portion 5c, and the small interval portion 5d are not provided. Compared to the width of the three signal lines 4c of 20 μm, it became extremely uniform. Thus, by adopting the configuration of the second embodiment, in the case of the multilayer wiring board 1 having the configuration of FIG. 1, the size is reduced to 0.8 times. In other words, the integration was 1.25 times higher. In addition, the miniaturization has made it possible to manufacture at low cost.
[0042]
Note that the present invention is not limited to the above-described embodiment, and various changes may be made without departing from the scope of the present invention. For example, in the above embodiment, two signal line layers are provided, but three or more signal line layers may be provided.
[0043]
【The invention's effect】
In the multilayer wiring board of the present invention, the lower ground conductor layer, the first signal line layer, the inner layer ground conductor layer, the second signal line layer, and the upper ground conductor layer are respectively provided on the main surface of the insulating substrate via the insulating layer. The first and second signal line layers are sequentially laminated, and each of the first and second signal line layers includes a plurality of signal lines including those having different characteristic impedances. The provision of the conductor non-formation portion directly above or directly below the large signal line enables high-density wiring of the signal line and the provision of jumper wires for cross wiring, thereby enabling the semiconductor element to be provided. Can be adapted to increase the number of pins.
[0044]
Further, the distance between the signal line having a characteristic impedance of more than 70Ω and the upper grounding conductor layer or the lower grounding conductor layer increases, the electric capacity decreases, the characteristic impedance value increases, and there is no conductor non-forming portion. In order to obtain the same characteristic impedance value as compared with the case, the width of the signal line becomes large. Therefore, the width of the signal line having a large characteristic impedance can be made larger than that of a conventional signal line, and the control of the characteristic impedance can be easily performed. Thus, a signal line having a small variation in the characteristic impedance can be formed. Further, the first signal line layer and the second signal line layer are not affected by external noise, and can cope with an increase in the operating speed of the semiconductor element connected to the signal line.
[0045]
In the multilayer wiring board according to the present invention, preferably, the inner-layer ground conductor layer has a portion in which a characteristic impedance is reduced immediately above or immediately below a signal line having a characteristic impedance of 40Ω or less among a plurality of signal lines. As a result, the electrical capacitance between the inner ground conductor layer and the signal line having the characteristic impedance of 40Ω or less increases, the characteristic impedance value decreases, and it is attempted to obtain the same characteristic impedance value as compared to a case where there is no portion with a small gap. Then, the width of the signal line becomes smaller. Therefore, the width of a signal line having a small characteristic impedance can be made smaller than that of a conventional signal line, and can be closer to the width of a signal line having a larger characteristic impedance. As a result, the width of the signal lines having different characteristic impedances is extremely close to or substantially equal to each other in combination with the function and effect of the provision of the non-conductor portion, so that further high-density wiring is possible. .
[Brief description of the drawings]
FIG. 1 is a sectional view showing an example of an embodiment of a multilayer wiring board of the present invention.
FIG. 2 is a cross-sectional view of a conventional multilayer wiring board.
FIG. 3 is a sectional view showing another example of a conventional multilayer wiring board.
[Explanation of symbols]
1: Multilayer wiring board 2: Insulating substrate 3: Lower ground conductor layer 4: First signal line layers 4a to 4c: First to third signal lines 5: Inner layer ground conductor layers 5b, 5c: First and second Conductor non-formed portion 6: second signal line layers 6a to 6c: fourth to sixth signal lines 7: upper ground conductor layer 8: insulating layer

Claims (2)

A lower ground conductor layer, a first signal line layer, an inner layer ground conductor layer, a second signal line layer, and an upper ground conductor layer are sequentially laminated on the main surface of the insulating substrate via an insulating layer, respectively. The first and second signal line layers each include a plurality of signal lines including those having different characteristic impedances, and the inner ground conductor layer has a characteristic impedance of the signal line larger than 70Ω among the plurality of signal lines. A multilayer wiring board, wherein a conductor-free portion is provided immediately above or immediately below. The said inner ground conductor layer has a part which reduced the space | interval with the said signal line immediately above or immediately below the said signal line whose characteristic impedance is 40 ohms or less among the said several signal lines, The characterized by the above-mentioned. 2. The multilayer wiring board according to 1.

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