JP2004014918A - Manufacturing method of mis semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of an MIS semiconductor device in which an etching selection ratio between a high dielectric gate insulating film and a silicon layer of its base is taken greatly. <P>SOLUTION: The manufacturing method includes a step for forming a gate electrode by forming a gate insulating film composed of an oxide high dielectric material on the silicon layer, forming a gate electrode material film thereon, and selectively removing the exposed gate electrode material film by etching while using a prescribed etching mask; a step for installing the silicon layer having the etching mask within a plasma etching device, and selectively exposing a silicon layer surface by removing a gate insulating film portion exposed from the etching mask by alternately repeating an operation for exposing the gate insulating film exposed from the etching mask under a fluorocarbon gas atmosphere and operation for exposing it under a diluted gas ion radiation plasma atmosphere; and a step for forming a drain area by injecting impurities which imparts conductivity to the silicon layer. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for manufacturing a MIS type semiconductor device, and more particularly to a method for manufacturing a MIS type semiconductor device in which a dry etching step of an insulating film for forming source and drain contacts is improved.
[0002]
[Prior art]
Conventionally, a semiconductor device having a MOS (Metal-Oxide-Silicon) structure, for example, a semiconductor device having a bulk silicon substrate, has a silicon oxide film (SiO 2) as a gate insulating film. ₂ ) Is used. Such a semiconductor device is manufactured by the following method. That is, for example, a step of forming an element isolation region on the main surface of a p-type silicon wafer (p-type silicon substrate), a step of forming a gate insulating film on the main surface of the silicon substrate, and depositing a gate electrode material film on the entire surface A step of patterning the gate electrode material film to form a gate electrode, and ion-implanting an n-type impurity using the gate electrode as a mask. ⁺ Forming source and drain regions of the mold, and forming SiO 2 on the entire surface including the gate electrode. ₂ Depositing an interlayer insulating film consisting of: a step of opening a contact hole in the interlayer insulating film corresponding to the source and drain regions and a gate insulating film thereunder; and forming a wiring on the interlayer insulating film including the contact hole. After depositing a material film, patterning and forming a wiring connected to the source / drain region through the contact hole, thereby manufacturing a semiconductor device having a MOS structure.
[0003]
In the manufacture of a semiconductor device having such a MOS structure, RIE (Reactive Ion Etching) is usually used to form the contact hole. However, both the interlayer insulating film and the gate insulating film are made of SiO. ₂ Therefore, a high selectivity can be obtained with respect to the underlying silicon substrate, so that the contact hole can be formed without excessively etching the silicon substrate.
[0004]
In the conventional MOS device having the MOS structure as described above, when the MOS transistor is miniaturized for low power consumption and high operation speed, the SiO2 of the gate insulating film is formed at the same ratio according to the scaling law. ₂ Also need to be made thinner. For example, when the gate length is 0.1 μm, the thickness of SiO 2 ₂ Is required as a gate insulating film, and the film thickness approaches the physical thin film limit. Therefore, a gate insulating film (high-dielectric gate insulating film) made of an oxide-based high-dielectric material capable of increasing the physical film thickness is formed of SiO. ₂ Considerations are being made to apply it instead of.
[0005]
As the oxide-based high dielectric material used for the gate insulating film, transition metal oxides and rare earth oxides are considered to be effective. In the above-described semiconductor device manufacturing process, SiO 2 ₂ When a high dielectric gate insulating film is used in place of the gate insulating film, the gate insulating film is formed by thermal oxidation of the silicon substrate and the deposition of the high dielectric gate insulating film. It is necessary to ensure the selectivity with respect to the underlying silicon substrate when the high dielectric gate insulating film is selectively removed by etching.
[0006]
[Problems to be solved by the invention]
Transition metal oxides, particularly rare earth oxides, which are materials for the high-dielectric gate insulating film, have few compounds with high volatility, and have extremely low volatility of halides with halogens used in ordinary dry etching. Therefore, it is expected that there is no major problem in the etching step for patterning the gate electrode because the etching of the high dielectric gate insulating film is suppressed.
[0007]
On the other hand, when the high dielectric gate insulating film itself is selectively etched away, the etching rate of the silicon substrate is higher than the etching rate of the high dielectric gate insulating film, so that it is extremely difficult to ensure the selectivity to the underlying silicon substrate. There was a problem.
[0008]
The present invention makes it possible to increase the etching selectivity between the high dielectric gate insulating film and the underlying silicon layer, thereby forming impurity injection windows, contact holes, etc. without excessively etching the silicon layer. It is an object of the present invention to provide a method of manufacturing a MIS type semiconductor device that can perform the above-mentioned steps.
[0009]
[Means for Solving the Problems]
A method for manufacturing a MIS type semiconductor device according to the present invention includes the steps of: forming a gate insulating film made of an oxide-based high dielectric material on a silicon layer;
Forming a gate electrode material film on the gate insulating film, forming a predetermined etching mask on the gate electrode material film, and selectively etching away the gate electrode material film exposed from the etching mask. Forming a gate electrode;
An operation of exposing a silicon layer having the etching mask in a plasma etching apparatus and exposing the gate insulating film exposed from the etching mask to a fluorocarbon-based gas atmosphere and an operation of exposing to a rare gas ion-irradiated plasma atmosphere is alternately performed. Repeatedly removing the gate insulating film portion exposed from the etching mask to selectively expose the silicon layer surface; and
Forming source and drain regions electrically isolated from each other by implanting impurities imparting conductivity to the silicon layer through the exposed surface;
It is characterized by including.
[0010]
Another method for manufacturing a MIS type semiconductor device according to the present invention includes a step of forming a gate insulating film made of an oxide-based high dielectric material on a silicon layer;
A gate electrode material film is formed on the gate insulating film, a predetermined mask made of an insulating material is formed on the gate electrode material film, and the gate electrode material film exposed from the mask is selectively etched away. Forming a gate electrode by
Forming a low-concentration impurity region by ion-implanting an impurity imparting conductivity through the gate insulating film into the silicon layer excluding the mask;
After forming a film made of an insulating material having a selective etching property with respect to the gate insulating film on the entire surface including the mask, the film is subjected to reactive ion etching to form spacers on the side surfaces of the gate electrode and the mask. Process and
An operation in which a silicon layer having the mask and the spacer is provided in a plasma etching apparatus, and an operation of exposing the gate insulating film exposed from the mask and the spacer to a fluorocarbon-based gas atmosphere and an operation of exposing to a rare gas ion-irradiated plasma atmosphere Alternately removing the gate insulating film portion exposed from the mask and the spacer to selectively expose the silicon layer surface; and
Impurities that impart conductivity to the silicon layer are implanted through the exposed surface to form high-concentration impurity regions, thereby forming source and drain regions composed of low-concentration and high-concentration regions electrically separated from each other. Process and
It is characterized by including.
[0011]
Still another method for manufacturing a MIS semiconductor device according to the present invention includes a step of forming a gate insulating film made of an oxide-based high dielectric material on a silicon layer;
Forming a gate electrode on a part of the gate insulating film;
Forming a source and a drain region in the silicon layer by electrically separating each other;
After forming an interlayer insulating film on the gate insulating film including the gate electrode, forming a predetermined etching mask,
A silicon layer having the etching mask is provided in a plasma etching apparatus, and the interlayer insulating film exposed from the etching mask is selectively removed by etching until the underlying gate insulating film is exposed. Opening a contact hole by selectively etching the gate insulating film exposed from the etching hole of the interlayer insulating film by alternately repeating an operation of exposing to an atmosphere and an operation of exposing to a rare gas ion irradiation plasma atmosphere;
It is characterized by including.
[0012]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, the present invention will be described in detail.
[0013]
(1st Embodiment)
First, a gate insulating film made of an oxide-based high dielectric material is formed on a silicon layer.
[0014]
Examples of the silicon layer include a polycrystalline silicon layer formed on a transparent insulating substrate such as a silicon substrate containing impurities or a glass substrate.
[0015]
As the oxide-based high dielectric material, for example, HfO ₂ , ZrO ₂ , SiZrO ₄ Or a transition metal oxide such as Gd ₂ O ₃ And rare earth oxides.
[0016]
Next, a gate electrode material film such as, for example, polycrystalline silicon, Mo, or Ta is formed on the gate insulating film, and a predetermined etching mask is formed on the gate electrode material film. A gate electrode is formed by selectively etching away the gate electrode material film.
[0017]
Examples of the etching mask include a resist pattern formed by a photolithography method.
[0018]
Next, a silicon layer having the etching mask is provided in a plasma etching apparatus, and an operation of exposing the gate insulating film exposed from the etching mask to a fluorocarbon-based gas atmosphere and an operation of exposing to a rare gas ion irradiation atmosphere are performed. The gate insulating film portion exposed from the etching mask is alternately removed to selectively expose the surface of the silicon layer.
[0019]
The plasma etching apparatus may be any apparatus capable of irradiating rare gas ions having an energy of 50 eV or more in plasma, such as an RIE apparatus, an apparatus having a microwave plasma source and a bias substrate electrode, and an IPC plasma source and a bias substrate. A device having electrodes can be used.
[0020]
The operation of exposing to the fluorocarbon-based gas atmosphere is performed by simply supplying the fluorocarbon-based gas into the chamber of the etching apparatus without generating plasma in the chamber. As the fluorocarbon-based gas used here, for example, CF ₄ Gas, C ₂ F ₆ C like gas _x F _y Gas or CHF ₃ C like gas _x H _y F _z Gas and the like can be mentioned.
[0021]
The operation of exposing to the rare gas ion irradiation atmosphere includes supplying a rare gas into the chamber of the etching apparatus, generating plasma in the chamber to ionize the rare gas, accelerating the ions, and exposing the gate insulation. This is done by irradiating the film. Examples of the rare gas used here include Ar, He, Ne, Kr, and Xe. Among them, Ar is particularly preferable.
[0022]
The above two operations are alternately repeated a number of times corresponding to the film thickness to form a film.
[0023]
Next, source and drain regions electrically isolated from each other are formed by injecting impurities imparting conductivity to the silicon layer through the exposed surface. Subsequently, after an interlayer insulating film is formed on the entire surface including the gate electrode, a resist film is coated, exposed, and developed to form a resist pattern. Subsequently, a contact hole is opened by selectively etching away the interlayer insulating film using the resist pattern as a mask. Subsequently, a wiring material film such as Al or an Al alloy is formed on the interlayer insulating film including the contact hole, and is patterned to form a source / drain connected to the source / drain region through the contact hole. Wiring is formed to manufacture a MIS type semiconductor device.
[0024]
As described above, according to the first embodiment, when an exposed gate insulating film made of an oxide-based high dielectric material is etched using an etching mask for forming a gate electrode, the gate insulating film is exposed from the etching mask in a plasma etching apparatus. By alternately repeating the operation of exposing the gate insulating film to a fluorocarbon-based gas atmosphere and the operation of exposing to a rare gas ion irradiation atmosphere, the gate insulating film has a high etching selectivity with respect to the underlying silicon layer. The film portion can be removed by etching.
[0025]
It is thought that the following effects can exert a high etching selectivity with respect to the underlying silicon layer when the gate insulating film made of such an oxide-based high dielectric material is etched.
[0026]
That is, in an operation of exposing a gate insulating film made of an oxide-based high dielectric material to a fluorocarbon gas atmosphere, fluorocarbon fragments are adsorbed on the surface of the gate insulating film. Thereafter, in an operation of exposing to an atmosphere of irradiation of rare gas ions, the carbon fluoride fragments are oxidized and volatilized by oxygen generated from the oxide-based high dielectric material due to physical etching, so that the deposition is prevented. That is, the effect of preventing the etching by the fluorocarbon fragment disappears, and the etching effect by the impact of the rare gas ions becomes dominant, and the gate insulating film made of the oxide-based high dielectric material is etched.
[0027]
On the other hand, when the gate insulating film is etched and the underlying silicon layer is exposed and then exposed to a fluorocarbon gas atmosphere, fluorocarbon fragments are adsorbed on the surface of the silicon layer. After that, unlike the oxide-based high dielectric material, the silicon layer does not generate oxygen by physical etching in the operation of exposing to the rare gas ion irradiation atmosphere, so that the fluorocarbon fragment is not oxidized and the silicon layer is not oxidized. Stop at the layer surface. For this reason, the effect of preventing the silicon layer from being etched by the fluorocarbon fragments against the impact of rare gas ions works.
[0028]
The disappearance of the fluorocarbon fragments on the surface of the gate insulating film made of such an oxide-based high-dielectric material and the retention of the fluorocarbon fragments on the surface of the silicon layer greatly increase the distance between the gate insulating film and the silicon layer. It is estimated that this is expressed as an etching selectivity.
[0029]
Therefore, the silicon layer surface can be selectively exposed without excessively etching the silicon layer. As a result, impurities imparting conductivity to the silicon layer can be implanted through the exposed surface thereof, and the source and drain regions electrically isolated from each other can be formed in the silicon layer having almost no etching. It is possible to manufacture a highly reliable MIS semiconductor device.
[0030]
(2nd Embodiment)
First, a gate insulating film made of an oxide-based high dielectric material is formed on a silicon layer.
[0031]
Examples of the silicon layer include a silicon substrate containing impurities and a polycrystalline silicon layer, as described in the first embodiment.
[0032]
As the oxide-based high dielectric material, the same material as described in the first embodiment can be used.
[0033]
Next, a gate electrode material film such as polycrystalline silicon, Mo or Ta is formed on the gate insulating film, a predetermined mask is formed on the gate electrode material film, and then the gate electrode exposed from the mask is formed. A gate electrode is formed by selectively etching away the material film.
[0034]
As the mask, for example, a silicon oxide (SiO 2) patterned using a resist pattern formed by photolithography as a mask is used. ₂ ) Patterns, silicon nitride (SiN) patterns, and the like.
[0035]
Next, a low concentration impurity region is formed by ion-implanting an impurity imparting conductivity into the silicon layer excluding the mask through the gate insulating film.
[0036]
As the impurity imparting conductivity, an n-type impurity such as arsenic and a p-type impurity such as boron can be used.
[0037]
Then, after forming a film made of an insulating material having a selective etching property with respect to the gate insulating film over the entire surface including the mask, the film is subjected to reactive ion etching to form spacers on the side surfaces of the gate electrode and the mask. To form
[0038]
It is preferable that the insulating material also has a selective etching property with respect to the mask. As such an insulating material, for example, the mask is made of silicon oxide (SiO 2). ₂ ) In the case of a pattern, silicon nitride can be used.
[0039]
Next, a silicon layer having the mask and the spacer is provided in a plasma etching apparatus, and the gate insulating film exposed from the mask and the spacer is exposed to a fluorocarbon-based gas atmosphere and exposed to a rare gas ion-irradiated plasma atmosphere. The operation is alternately repeated to remove the gate insulating film portion exposed from the mask and the spacer to selectively expose the silicon layer surface.
[0040]
As the plasma etching apparatus, similar to the first embodiment, any apparatus capable of irradiating rare gas ions having an energy of 50 eV or more in plasma may be used.
[0041]
The operation of exposing to the fluorocarbon-based gas atmosphere is performed by simply supplying the fluorocarbon-based gas into the chamber of the etching apparatus without generating plasma in the chamber. As the fluorocarbon-based gas used here, for example, CF ₄ Gas, C ₂ F ₆ C like gas _x F _y Gas or CHF ₃ C like gas _x H _y F _z Gas and the like can be mentioned.
[0042]
The operation of exposing to the rare gas ion irradiation atmosphere includes supplying a rare gas into the chamber of the etching apparatus, generating plasma in the chamber to ionize the rare gas, accelerating the ions, and exposing the gate insulation. This is done by irradiating the film. Examples of the rare gas used here include Ar, He, Ne, Kr, and Xe. Among them, Ar is particularly preferable.
[0043]
The above two operations are alternately repeated a number of times corresponding to the film thickness to form a film.
[0044]
Impurities (for example, n-type impurities such as arsenic, or p-type impurities such as boron) that impart conductivity to the silicon layer are implanted through the exposed surface to form high-concentration impurity regions, thereby electrically isolating the silicon layers from each other. A source / drain region having a so-called LDD (Lightly Doped Drain) structure formed of the low-concentration and high-concentration regions is formed. Subsequently, after an interlayer insulating film is formed on the entire surface including the gate electrode, a resist film is coated, exposed, and developed to form a resist pattern. Subsequently, a contact hole is opened by selectively etching away the interlayer insulating film using the resist pattern as a mask. A wiring material film such as Al or Al alloy is formed on the interlayer insulating film including the contact hole, and is patterned to form a source / drain wiring connected to the source / drain region through the contact hole. Then, an MIS type semiconductor device is manufactured.
[0045]
As described above, according to the second embodiment, when a gate insulating film made of an oxide-based high dielectric material is exposed using a mask and a spacer for forming a gate electrode, the mask and the spacer are etched in a plasma etching apparatus. By alternately repeating the operation of exposing the gate insulating film exposed from the substrate to a fluorocarbon-based gas atmosphere and the operation of exposing to a rare gas ion irradiation atmosphere, the underlying silicon layer can be removed similarly to the first embodiment. Thus, the gate insulating film portion exposed with a high etching selectivity can be removed by etching.
[0046]
Therefore, the silicon layer surface can be selectively exposed without excessively etching the silicon layer. As a result, the second conductivity-imparting impurity can be implanted into the silicon layer through the exposed surface, and the source and drain regions having the LDD structure electrically isolated from each other are formed in the silicon layer having almost no etching. Therefore, a highly reliable MIS type semiconductor device can be manufactured.
[0047]
(Third embodiment)
First, a gate insulating film made of an oxide-based high dielectric material is formed on a silicon layer.
[0048]
Examples of the silicon layer include a silicon substrate containing impurities and a polycrystalline silicon layer, as described in the first embodiment.
[0049]
As the oxide-based high dielectric material, the same material as described in the first embodiment can be used.
[0050]
Next, a gate electrode material film such as, for example, polycrystalline silicon, Mo, or Ta is formed on the gate insulating film, and a predetermined etching mask is formed on the gate electrode material film. A gate electrode is formed by selectively etching away the gate electrode material film. Subsequently, using the gate electrode as a mask, impurities are ion-implanted into the silicon layer through the gate insulating film to form source and drain regions electrically separated from each other in the silicon layer.
[0051]
Next, after forming an interlayer insulating film on the gate insulating film including the gate electrode, the resist film is coated, exposed and developed to form a resist pattern as a predetermined etching mask. Subsequently, a silicon layer having the etching mask is set in a plasma etching apparatus, the interlayer insulating film is removed by etching using the resist pattern as a mask, and then exposed to a fluorocarbon-based gas atmosphere and irradiated with rare gas ions. An operation of exposing to an atmosphere is alternately repeated to selectively remove the gate insulating film exposed by etching the interlayer insulating film, thereby opening a contact hole.
[0052]
As the plasma etching apparatus, similar to the first embodiment, any apparatus capable of irradiating rare gas ions having an energy of 50 eV or more in plasma may be used.
[0053]
The operation of exposing to the fluorocarbon-based gas atmosphere is performed by simply supplying the fluorocarbon-based gas into the chamber of the etching apparatus without generating plasma in the chamber. As the fluorocarbon-based gas used here, for example, CF ₄ Gas, C ₂ F ₆ C like gas _x F _y Gas or CHF ₃ C like gas _x H _y F _z Gas and the like can be mentioned.
[0054]
The operation of exposing to the rare gas ion irradiation atmosphere includes supplying a rare gas into the chamber of the etching apparatus, generating plasma in the chamber to ionize the rare gas, accelerating the ions, and exposing the gate insulation. This is done by irradiating the film. Examples of the rare gas used here include Ar, He, Ne, Kr, and Xe. Among them, Ar is particularly preferable.
[0055]
The above two operations are alternately repeated a number of times corresponding to the film thickness to form a film.
[0056]
Next, a wiring material film such as Al or an Al alloy is formed on the interlayer insulating film including the contact hole, and is patterned to form a source / drain wiring connected to the source / drain region through the contact hole. Is formed to manufacture a MIS type semiconductor device.
[0057]
As described above, according to the third embodiment, when the interlayer insulating film is selectively removed by using a mask such as a resist pattern, and the underlying gate insulating film made of an oxide-based high dielectric material is etched, As in the first embodiment described above, the operation of exposing the gate insulating film exposed from the mask in a plasma etching apparatus to a fluorocarbon-based gas atmosphere and the operation of exposing the gate insulating film to a rare gas ion irradiation atmosphere are alternately repeated. In addition, the gate insulating film portion exposed with a high etching selectivity to the underlying silicon layer can be removed by etching.
[0058]
Therefore, since a contact hole can be opened over the interlayer insulating film and the gate insulating film without excessively etching the silicon layer, a highly reliable MIS semiconductor device can be manufactured.
[0059]
【Example】
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0060]
FIG. 1 is a schematic sectional view showing an RIE apparatus used in the embodiment of the present invention.
[0061]
In a grounded chamber 1, a substrate support member 2 also serving as an electrode is disposed. The support member 2 has a hollow portion 5 communicating with the supply hole 3 and the discharge hole 4 of the cooling water. The high frequency power supply 6 is connected to the support member 2 through a matching device 7.
[0062]
The exhaust pipe 8 is formed on the lower right side of the chamber 1, and a vacuum pump (not shown) is connected to the other end of the exhaust pipe 8. The gate valve 9 is interposed in the exhaust pipe 8.
[0063]
The first and second gas supply pipes 10 and 11 are connected to a pipe 12 at their ends, and the pipe 12 is connected to an upper left portion of the chamber 1. The first and second flow controllers 13 and 14 are provided with an argon gas supply pipe 10 and a CF. ₄ The gas supply pipes 11 are respectively provided. The valve 15 is interposed in the pipe 12.
[0064]
(Example 1)
A method for manufacturing an n-channel MIS semiconductor device will be described with reference to FIGS.
[0065]
First, an oxide-based high dielectric material such as Gd is deposited on the main surface of the p-type silicon substrate 21 by electron beam evaporation. ₂ O ₃ Was formed at a temperature of 400 ° C. after forming a gate insulating film 22 having a thickness of 5 nm. Subsequently, a polycrystalline silicon film was deposited on the gate insulating film 22 by a CVD method. After a resist pattern 23 is formed on the polycrystalline silicon film by photolithography, the polycrystalline silicon film is selectively etched away using the resist pattern 23 as a mask, as shown in FIG. A gate electrode 24 having a width of 5 μm was formed on the gate insulating film 22.
[0066]
Next, the silicon substrate 21 having the resist pattern 23 was set on the support member 2 in the chamber 1 shown in FIG. Subsequently, the silicon substrate on the support member 2 was cooled by flowing the hollow portion 5 of the support member 2 through the cooling water supply hole 3 and discharging the hollow water through the discharge hole 4. Subsequently, the opening degree of the gate valve 9 of the exhaust pipe 8 was adjusted, and a vacuum pump (not shown) was operated to exhaust the gas in the chamber 1 to a predetermined degree of vacuum. After the degree of vacuum in the chamber 1 was stabilized, the first operation and the second operation under the following conditions were alternately repeated 10 times.
[0067]
<First operation>
CF ₄ The gas is supplied to the second supply pipe 11, the flow rate is adjusted by the second flow controller 14, and the CF is supplied through the open pipe 12. ₄ Gas was supplied into the chamber 1 at a flow rate of 100 sccm for 30 seconds to a pressure of 20 Pa. In this operation, no high-frequency power was applied from the high-frequency power supply 6 and no plasma was generated in the chamber.
[0068]
<Second operation>
CF ₄ The supply of gas is stopped, argon gas is supplied to the first supply pipe 10, the flow rate is adjusted by the first flow controller 13, and argon gas is supplied into the chamber 1 at a flow rate of 100 sccm through the open pipe 12 for 30 seconds. Then, at a pressure of 20 Pa, at the same time, a high frequency power of 13.56 MHz and 300 W is applied from the high frequency power source 6 to the support member 2 through the matching unit 7 to generate a plasma 16 between the support member 2 and the chamber 1 to generate argon ions. Was applied to the gate insulating film exposed from the resist pattern on the substrate.
[0069]
At this time, Gd for the silicon substrate 21 ₂ O ₃ The etching selectivity of the gate insulating film 22 made of is approximately 1.6, and almost no etching of the surface of the silicon substrate 21 occurs. ₂ O ₃ The portion of the gate insulating film 22 made of was removed by etching, and the surface of the silicon substrate 21 was exposed. Subsequently, by implanting arsenic into the silicon substrate 21 through the exposed surface, n + type source and drain regions 25 and 26 which are electrically separated from each other were formed as shown in FIG. 2B.
[0070]
For comparison, CF ₄ The gas is supplied to the second supply pipe 11, the flow rate is adjusted by the second flow controller 14, the argon gas is supplied to the first supply pipe 10, the flow rate is adjusted by the first flow controller 13, and the gas is supplied through the open pipe 12. CF ₄ A gas is supplied at a flow rate of 75 sccm and an argon gas is supplied at a flow rate of 25 sccm into the chamber 1 for 5 minutes to make the gas pressure 4 Pa. At the same time, a high frequency power of 13.56 MHz and 200 W is supplied from the high frequency power supply 6 through the matching unit 7 to the supporting member. 2 and a mixed plasma was generated between the support member 2 and the chamber 1 to etch the gate insulating film exposed from the resist pattern on the silicon substrate. At this time, Gd with respect to the silicon substrate ₂ O ₃ The etching selectivity of the gate insulating film made of was about 0.03, and it was confirmed that the silicon substrate surface was also etched when the gate insulating film was removed by etching.
[0071]
Next, the resist pattern 23 is peeled off and the entire surface including the gate electrode 24 is covered with SiO 2. ₂ After the interlayer insulating film 27 is formed, the interlayer insulating film 27 is selectively etched away using a resist pattern (not shown) as a mask, thereby forming the source and drain regions 25 and 26 as shown in FIG. Contact holes 28 and 29 were opened in the portion of the interlayer insulating film 27 corresponding to. Subsequently, a wiring material film made of an Al alloy is deposited on the interlayer insulating film 27 including the contact holes 28 and 29 by vacuum deposition and patterned, thereby forming the contact holes as shown in FIG. Source and drain wirings 30 and 31 connected to the source region 25 and the drain region 26 through 28 and 29 were formed to manufacture an MIS type semiconductor device.
[0072]
The obtained MIS type semiconductor device had a small gate length of 5 μm, and had high reliability because the surfaces of the source and drain regions 25 and 26 were not etched.
[0073]
(Example 2)
A method for manufacturing an n-channel MIS semiconductor device will be described with reference to FIGS.
[0074]
First, an oxide-based high dielectric material such as Gd is deposited on the main surface of the p-type silicon substrate 41 by electron beam evaporation. ₂ O ₃ After forming a gate insulating film 42 having a thickness of 5 nm, the film was annealed at 400 ° C. Subsequently, a polycrystalline silicon film and a silicon oxide film were sequentially deposited on the gate insulating film 42 by a CVD method. After a resist pattern (not shown) is formed on the silicon oxide film by photolithography, the silicon oxide film is selectively etched and removed using the resist pattern as a mask to form a 5 μm-wide width on the polycrystalline silicon film. The silicon oxide pattern 43 was formed. Subsequently, the resist pattern was peeled off and the polycrystalline silicon film was selectively etched using the silicon oxide pattern 43 as a mask to form a gate electrode 44 having a width of 5 μm on the gate insulating film 42. Thereafter, arsenic, which is an n-type impurity, is ion-implanted into the p-type silicon substrate 41 through the gate insulating film 42 using the silicon oxide pattern 43 as a mask, thereby electrically connecting each other as shown in FIG. Low concentration n-type region 45 to be isolated ₁ , 45 ₂ Was formed.
[0075]
Next, as shown in FIG. 3B, a silicon nitride film 46 was deposited on the entire surface including the silicon oxide pattern 43. Subsequently, the silicon nitride film 46 was subjected to reactive ion etching. At this time, as shown in FIG. 3C, spacers 47 made of silicon nitride were formed on the side surfaces of the stacked body of the gate electrode 44 and the silicon oxide pattern 43.
[0076]
Next, the silicon substrate 41 on which the spacer 47 was formed was set on the support member 2 in the chamber 1 shown in FIG. Subsequently, the silicon substrate on the support member 2 was cooled by flowing the hollow portion 5 of the support member 2 through the cooling water supply hole 3 and discharging the hollow water through the discharge hole 4. Subsequently, the opening degree of the gate valve 9 of the exhaust pipe 8 was adjusted, and a vacuum pump (not shown) was operated to exhaust the gas in the chamber 1 to a predetermined degree of vacuum. After the degree of vacuum in the chamber 1 is stabilized, the first operation (CF ₄ The operation of exposing to a gas atmosphere) and the second operation (operation of irradiating with argon ions) were alternately repeated 10 times. At this time, Gd for the silicon substrate 41 ₂ O ₃ The etching selectivity of the gate insulating film 42 made of is approximately 1.6, and the etching of the surface of the silicon substrate 41 hardly occurs, and the Gd exposed from the silicon oxide pattern 43 and the spacer 47 is formed. ₂ O ₃ The portion of the gate insulating film 42 made of was removed by etching, and the surface of the silicon substrate 41 was exposed. Subsequently, arsenic is implanted into the silicon substrate 41 through the exposed surface to thereby provide a high-concentration n. ⁺ Mold area 48 ₁ , 48 ₂ Is formed, the n-type regions 45 electrically isolated from each other as shown in FIG. ₁ , 45 ₂ And n + type region 48 ₁ , 48 ₂ , A source 49 and a drain region 50 having a so-called LDD (Lightly doped drain) structure were formed. Thereafter, although not shown, an MIS type semiconductor is formed by forming an interlayer insulating film, opening contact holes, and forming source and drain wirings connected to the source and drain regions through these contact holes, as in the first embodiment. The device was manufactured.
[0077]
The obtained MIS type semiconductor device had high reliability with a fine gate length of 5 μm and no etching of the surfaces of the source and drain regions 49 and 50 having the LDD structure.
[0078]
(Example 3)
A method for manufacturing an n-channel MIS semiconductor device will be described with reference to FIGS.
[0079]
First, an oxide-based high dielectric material such as Gd is deposited on the main surface of the p-type silicon substrate 51 by electron beam evaporation. ₂ O ₃ After forming a gate insulating film 52 having a thickness of 5 nm made of, annealed at 400 ° C. Subsequently, a polycrystalline silicon film was deposited on the gate insulating film 52 by a CVD method. After a resist pattern (not shown) is formed on the polycrystalline silicon film by photolithography, the polycrystalline silicon film is selectively etched away using the resist pattern as a mask to form a width on the gate insulating film 52. Formed a gate electrode 53 of 5 μm. Subsequently, by using the resist pattern as a mask, arsenic is ion-implanted into the silicon substrate 51 through the gate insulating film 52, so that the n + type source regions 54 electrically separated from each other as shown in FIG. , A drain region 55 was formed.
[0080]
Next, the resist pattern is peeled and removed, and SiO 2 is formed on the gate insulating film 52 including the gate electrode 53. ₂ After the formation of the interlayer insulating film 56 made of, a resist pattern was formed as shown in FIG. 4B by applying a resist film, exposing, and developing. Subsequently, the silicon substrate 51 having the resist pattern 57 was set on the support member 2 in the chamber 1 shown in FIG. Subsequently, the silicon substrate on the support member 2 was cooled by flowing the hollow portion 5 of the support member 2 through the cooling water supply hole 3 and discharging the hollow water through the discharge hole 4. Subsequently, the opening degree of the gate valve 9 of the exhaust pipe 8 was adjusted, and a vacuum pump (not shown) was operated to exhaust the gas in the chamber 1 to a predetermined degree of vacuum. After the degree of vacuum in the chamber 1 is stabilized, CF ₄ The gas is supplied to the second supply pipe 11, the flow rate is adjusted by the second flow controller 14, the argon gas is supplied to the first supply pipe 10, the flow rate is adjusted by the first flow controller 13, and the gas is supplied through the open pipe 12. CF ₄ A gas and an argon gas are supplied into the chamber 1 for 5 minutes, and at the same time, a high frequency power of 13.56 MHz is applied from the high frequency power source 6 to the support member 2 through the matching unit 7, and the mixed plasma is supplied between the support member 2 and the chamber 1. Is generated, the SiO 2 exposed from the resist pattern 57 is formed. ₂ Was selectively removed by etching until the underlying gate insulating film 52 was exposed. Thereafter, the first operation (CF ₄ The operation of exposing to a gas atmosphere) and the second operation (operation of irradiating with argon ions) were alternately repeated 10 times. At this time, Gd for the silicon substrate 51 ₂ O ₃ The etching selectivity of the gate insulating film 52 made of is approximately 1.6, and almost no etching occurs on the surface of the silicon substrate 51, and Gd exposed from the hole of the interlayer insulating film 56 already etched. ₂ O ₃ The portion of the gate insulating film 52 made of was removed by etching, and contact holes 58 and 59 were opened as shown in FIG.
[0081]
Then, a wiring material film made of an Al alloy is deposited on the interlayer insulating film 56 including the contact holes 58 and 59 by vacuum deposition and patterned, thereby forming the contact holes 58 and 59 as shown in FIG. Source and drain wirings 60 and 61 connected to the source region 54 and the drain region 55 through 59 were formed to manufacture a MIS type semiconductor device.
[0082]
The obtained MIS type semiconductor device had high reliability with a fine gate length of 5 μm and no etching of the surface of the silicon substrate 51 under the contact holes 58 and 59.
[0083]
(Example 4)
A method for manufacturing an n-channel thin film transistor (TFT) of a liquid crystal display device will be described with reference to FIGS.
[0084]
First, after forming a polycrystalline silicon layer on a glass substrate 71, the polycrystalline silicon layer was patterned to form an island-shaped active layer 72. Subsequently, on the glass substrate 71 including the active layer 72, an oxide-based high dielectric material, for example, Gd ₂ O ₃ After forming a 5 nm-thick gate insulating film 73 made of, annealed at 400 ° C. Subsequently, a Mo film was deposited on the gate insulating film 73 by a sputtering method. After forming a resist pattern 74 on the Mo film by photolithography, the Mo film is selectively etched away using the resist pattern 74 as a mask, thereby forming the active layer 72 as shown in FIG. A gate electrode 75 having a width of 5 μm was formed on the upper gate insulating film 73.
[0085]
Next, the glass substrate 71 having the resist pattern 74 was set on the support member 2 in the chamber 1 shown in FIG. Subsequently, the silicon substrate on the support member 2 was cooled by flowing the hollow portion 5 of the support member 2 through the cooling water supply hole 3 and discharging the hollow water through the discharge hole 4. Subsequently, the opening degree of the gate valve 9 of the exhaust pipe 8 was adjusted, and a vacuum pump (not shown) was operated to exhaust the gas in the chamber 1 to a predetermined degree of vacuum. After the degree of vacuum in the chamber 1 is stabilized, the first operation (CF ₄ The operation of exposing to a gas atmosphere) and the second operation (operation of irradiating with argon ions) were alternately repeated 10 times. At this time, Gd for the active layer 67 made of polycrystalline silicon ₂ O ₃ The etching selectivity of the gate insulating film 73 made of is approximately 1.6, and the etching of the surface of the active layer 72 hardly occurs. ₂ O ₃ The gate insulating film 73 made of was removed by etching, and the surface of the active layer 72 was exposed. Subsequently, by implanting arsenic into the active layer 72 through the exposed surface thereof, an n + type source region 76 and a drain region 77 which are electrically separated from each other are formed as shown in FIG. did.
[0086]
Next, the resist pattern 74 is peeled off and the entire surface including the gate electrode 75 is covered with SiO 2. ₂ After an interlayer insulating film 78 made of is formed, the interlayer insulating film 78 is selectively etched away using a resist pattern (not shown) as a mask, thereby forming the source and drain regions 76 and 77 as shown in FIG. Contact holes 79 and 80 were opened in the portion of the interlayer insulating film 78 corresponding to. Subsequently, a wiring material film made of an Al alloy is deposited on the interlayer insulating film 78 including the contact holes 79 and 80 by vacuum deposition and patterned, thereby forming the contact holes as shown in FIG. Source and drain wirings 81 and 82 connected to the source region 76 and the drain region 77 through 79 and 80 were formed to manufacture a TFT of a liquid crystal display device.
[0087]
The obtained TFT had a very small gate length of 5 μm and had high reliability because the surfaces of the source and drain regions 66 and 67 were not etched.
[0088]
【The invention's effect】
As described above in detail, according to the present invention, it is possible to increase the etching selectivity between the high-dielectric gate insulating film and the underlying silicon layer so that impurities can be removed without excessively etching the silicon layer. It is possible to provide a method of manufacturing a highly integrated and highly reliable MIS semiconductor device capable of forming an injection window, a contact hole, and the like.
[Brief description of the drawings]
FIG. 1 is a schematic diagram showing an RIE apparatus used in an embodiment of the present invention.
FIG. 2 is a sectional view showing a manufacturing process of the n-channel MIS semiconductor device according to the first embodiment of the present invention.
FIG. 3 is a sectional view illustrating a manufacturing process of an n-channel MIS semiconductor device according to a second embodiment of the present invention.
FIG. 4 is a sectional view showing a manufacturing process of an n-channel MIS semiconductor device according to a third embodiment of the present invention.
FIG. 5 is a sectional view showing a manufacturing process of an n-channel TFT according to a fourth embodiment of the present invention.
[Explanation of symbols]
1 ... chamber,
2. Support member,
6 ... High frequency power supply,
8 ... exhaust pipe,
10, 11 ... gas supply pipe,
16 ... plasma,
21, 41, 51 ... silicon substrate,
22, 42, 52, 73 ... gate insulating film,
24, 44, 53, 75 ... gate electrode,
25, 49, 54, 76 ... source areas,
26, 50, 55, 77 ... drain regions,
27, 56, 78 ... interlayer insulating film,
71 ... glass substrate,
72 ... Active layer.

Claims (6)

Forming a gate insulating film made of an oxide-based high dielectric material on the silicon layer;
Forming a gate electrode material film on the gate insulating film, forming a predetermined etching mask on the gate electrode material film, and selectively etching away the gate electrode material film exposed from the etching mask. Forming a gate electrode;
An operation of exposing a silicon layer having the etching mask in a plasma etching apparatus and exposing the gate insulating film exposed from the etching mask to a fluorocarbon-based gas atmosphere and an operation of exposing to a rare gas ion-irradiated plasma atmosphere is alternately performed. The step of selectively exposing the surface of the silicon layer by removing the portion of the gate insulating film exposed from the etching mask and the step of implanting an impurity imparting conductivity to the silicon layer through the exposed surface to thereby electrically connect the silicon layer to each other. Forming a source and drain region which are separated from each other. Forming a gate insulating film made of an oxide-based high dielectric material on the silicon layer;
A gate electrode material film is formed on the gate insulating film, a predetermined mask made of an insulating material is formed on the gate electrode material film, and the gate electrode material film exposed from the mask is selectively etched away. Forming a gate electrode by
Forming a low-concentration impurity region by ion-implanting an impurity imparting conductivity through the gate insulating film into the silicon layer excluding the mask;
After forming a film made of an insulating material having a selective etching property with respect to the gate insulating film over the entire surface including the mask, reactive ion etching is performed on the film to form spacers on the side surfaces of the gate electrode and the mask. Process and
An operation in which a silicon layer having the mask and the spacer is provided in a plasma etching apparatus, and an operation of exposing the gate insulating film exposed from the mask and the spacer to a fluorocarbon-based gas atmosphere and an operation of exposing to a rare gas ion-irradiated plasma atmosphere Alternately repeating the step of selectively exposing the silicon layer surface by removing the gate insulating film portion exposed from the mask and the spacer, and implanting impurities imparting conductivity to the silicon layer through the exposed surface. Forming a source and drain region composed of low-concentration and high-concentration regions electrically separated from each other by forming high-concentration impurity regions. . Forming a gate insulating film made of an oxide-based high dielectric material on the silicon layer;
Forming a gate electrode on the gate insulating film;
Forming source and drain regions electrically isolated from each other in the silicon layer;
After forming an interlayer insulating film on the gate insulating film including the gate electrode, forming a predetermined etching mask,
A silicon layer having the etching mask is provided in a plasma etching apparatus, and the interlayer insulating film exposed from the etching mask is selectively removed by etching until the underlying gate insulating film is exposed. Opening a contact hole by selectively etching the gate insulating film exposed from the etching hole of the interlayer insulating film by alternately repeating an operation of exposing to an atmosphere and an operation of exposing to a rare gas ion irradiation plasma atmosphere; A method for manufacturing a MIS type semiconductor device, comprising: 4. The method according to claim 1, wherein the silicon layer is a silicon substrate containing impurities. 4. The method according to claim 1, wherein the silicon layer is a polycrystalline silicon layer formed on a transparent insulating substrate. Fluorocarbon-based _gas, C x _{F y} gas or _C x _H y _{F z} manufacturing method of the MIS-type semiconductor device of claims 1 to 5, wherein any one, characterized in that a gas.

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