JP2004014644A - Method for manufacturing transistor, integrated circuit and electro-optical device using same, as well as electronic apparatus mounted with the device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device capable of establishing the characteristics of the bulk of a gate insulating film and the characteristics of an MOS interface. <P>SOLUTION: This method for manufacturing a transistor comprises a process (Fig. (f)) for depositing silicon oxide made of at least TEOS and oxygen on a semiconductor being the active layer of an MOS transistor by a parallel flat RF plasma CVD method to form a gate insulating film, a process (Fig. 1(g)) for forming a semiconductor film on the gate insulating film, and a process (Fig. 1(g)) for carrying out heat treatment to the gate insulating film. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for manufacturing a transistor. Further, an integrated circuit employing the transistor, and electro-optics represented by an EL (electroluminescence) display device, a liquid crystal display device, or an electrophoresis device using the transistor as a switching element or a driver circuit connected to a pixel. The present invention relates to a device and an electronic apparatus equipped with the electro-optical device.
[0002]
[Prior art]
It has been studied to use a relatively large transparent substrate such as glass or resin for a substrate of an electro-optical device such as a liquid crystal display device or an organic EL display device. These substrates have relatively low heat resistant temperatures. For this reason, a technology for manufacturing a semiconductor device such as a TFT integrated on the substrate and various devices by a low-temperature process has been developed. In addition, since the organic EL display element operates by current driving, a TFT having better driving performance is required, and a technique for manufacturing a low-temperature polysilicon TFT is important.
[0003]
In manufacturing a low-temperature polysilicon TFT, a step of forming a gate insulating film of a MOS transistor is indispensable. The quality of the gate insulating film has a great effect on transistor performance. ECR-PECVD (ECR plasma chemical vapor deposition) and parallel plate RF plasma CVD are used to form the gate insulating film. When the ECR-PECVD method is used, the characteristics of the MOS interface can be improved to the same level as a thermal oxide film by applying a heat treatment after depositing the gate insulating film. When the parallel plate RF plasma CVD is used, the bulk characteristics of the gate insulating film are good.
[0004]
[Problems to be solved by the invention]
However, a gate insulating film formed by using the ECR-PECVD method has an unfavorable tendency such as a large shift of a flat band voltage and a low withstand voltage, and further improvement of the film quality is desired. On the other hand, a gate insulating film formed using parallel plate RF plasma CVD contains many defects at the MOS interface. Either method makes it difficult to obtain a gate insulating film having both good bulk characteristics and good MOS interface characteristics.
[0005]
Accordingly, it is an object of the present invention to provide a method for manufacturing a semiconductor device capable of achieving both bulk characteristics and interface characteristics of a gate insulating film by a low-temperature process.
[0006]
[Means for Solving the Problems]
In order to achieve the above object, a method for manufacturing a transistor according to the present invention includes a step of forming a gate insulating film on a first semiconductor, a step of forming a second semiconductor on the gate insulating film, and a step of forming the second semiconductor. And performing a heat treatment after the formation.
[0007]
By manufacturing in accordance with such a process, excellent quality such as a low defect density at an interface between a semiconductor film serving as an active layer of a transistor and a gate insulating film (hereinafter referred to as a MOS interface), a low charge density in the film, and a high withstand voltage. Thus, a transistor having a high-quality gate insulating film can be manufactured by a low-temperature process.
[0008]
The first semiconductor serving as the active layer of the transistor can be a silicon substrate or a silicon film formed on a substrate having at least an insulating surface. Thereby, in the manufacturing process other than the process disclosed in the present invention, it is possible to follow the manufacturing process of an integrated circuit, an amorphous silicon TFT, and a polysilicon TFT using a semiconductor substrate which is currently widely used.
[0009]
As a method for forming the gate insulating film, silicon oxide containing tetraethoxysilane and oxygen as main raw materials is deposited by a plasma CVD method, particularly, a parallel plate type plasma CVD method. Thus, an insulating film of good quality can be formed, and the insulating film can be formed uniformly in the substrate (first semiconductor) surface.
[0010]
Further, the gate insulating film is formed in an atmosphere of 350 degrees Celsius or more and 450 degrees or less. Thereby, the quality of the gate insulating film and the MOS interface after the heat treatment can be improved.
[0011]
Preferably, a silicon film or a germanium film is used as the second semiconductor film formed over the gate insulating film. This is because the influence of diffusion of impurities into the active layer of the transistor can be eliminated.
[0012]
Further, the second semiconductor is amorphous. Thus, the effect of improving the film quality and the MOS interface by the heat treatment performed in a later step can be increased.
[0013]
The second semiconductor is deposited by plasma CVD, particularly by a parallel plate type plasma CVD method. Thereby, the effect of improving the film quality and the MOS by the heat treatment performed in a later step can be increased.
[0014]
Further, the heat treatment is performed in an atmosphere of 300 ° C. or more and 450 ° C. or less. Thereby, the effect of improving the film quality of the gate insulating film and the quality of the MOS interface can be maximized as compared with the case where the heat treatment is performed in a temperature range other than the above. Further, the heat treatment includes a step of irradiating light energy. As the light energy, for example, laser light or halogen lamp light can be used. As a result, the film quality and the MOS interface can be improved in a shorter process time as compared with heating in a heating furnace or the like, so that the process time can be reduced and the manufacturing cost can be reduced. Here, even when irradiating light energy, it is important to control the light energy intensity and the irradiation time so that the temperature of the first semiconductor film is 300 to 450 degrees Celsius.
[0015]
The method may further include a step of patterning the second semiconductor and a step of implanting an impurity into the first semiconductor, wherein the heat treatment is performed after the step of implanting the impurity. More specifically, after patterning the second semiconductor film into the shape of the gate electrode, 1 × 10 5 ¹⁹ cm ^-3 1x10 ²¹ cm ^-3 The following Group 3 element or Group 5 element impurities are implanted, and then heat treatment is performed. Accordingly, impurity implantation into the source and drain portions of the transistor and impurity implantation into the gate electrode for lowering the resistance of the gate electrode can be performed simultaneously, so that the process time can be reduced and the manufacturing cost can be reduced. It becomes possible.
[0016]
Further, the invention is characterized in that the second semiconductor is used as a gate electrode. Accordingly, the step of depositing the gate electrode material can be omitted, so that the process time can be reduced and the manufacturing cost can be reduced. Here, “used as a gate electrode” includes both a case where the gate electrode is used as a part and a case where the gate electrode is used as a whole.
[0017]
The method may further include a step of removing the second semiconductor after performing the heat treatment. After the second semiconductor is removed, an electrode material different from that of the second semiconductor film may be deposited on the gate insulating film and patterned to form a gate electrode. Accordingly, a material most suitable for the gate electrode material can be used as the gate electrode. For example, by using a gate electrode material having lower resistance, it becomes possible to operate the circuit at higher speed.
[0018]
Further, it is preferable to complete the device at a process temperature of 350 ° C. or lower in all the processes after the heat treatment process. Thereby, quality deterioration of the gate insulating film and the MOS interface during the manufacturing process can be prevented, and a high-quality MOS transistor can be manufactured.
[0019]
Preferably, the MOS transistor is manufactured on a glass substrate by a low-temperature process at a process temperature of 500 degrees Celsius or less in all processes. Thus, a high-quality transistor can be manufactured at low cost.
[0020]
In the transistor manufactured by the manufacturing method of the present invention, it is possible to form a gate insulating film having excellent quality such as low defect density at the MOS interface of the transistor, low charge density in the film, and high withstand voltage. It is possible to manufacture a high-performance transistor having a simple gate insulating film by a low-temperature process.
[0021]
Further, an integrated circuit of the present invention includes a transistor manufactured by any one of the manufacturing methods described above.
[0022]
According to another aspect of the invention, there is provided an electro-optical device including a switching element and an electro-optical layer controlled by the switching element, wherein the switching element includes a transistor manufactured by the above-described method.
[0023]
Further, the electronic device of the present invention is an electronic device including an electro-optical device as a display unit,
The electro-optical device is mounted as the display unit.
[0024]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0025]
In the embodiment of the present invention, as will be described in detail below, after depositing a gate insulating film of a MOS transistor, a semiconductor film is deposited, and a heat treatment is performed in a state where the semiconductor film is deposited. Defects in the insulating film and at the MOS interface are reduced, and the film quality is improved. As the gate insulating film, for example, a thermal oxide film of silicon, a silicon oxide film deposited by CVD, or the like can be used. Particularly, in a low-temperature process that needs to be formed at about 500 ° C. or less, tetraethoxysilane and oxygen gas are used. Is deposited as a raw material by a parallel plate RF plasma CVD method, an insulating film having better characteristics can be obtained.
[0026]
As the semiconductor film, a semiconductor film of a Group 4 element such as silicon or germanium can be used. Compound semiconductors composed of compounds such as Group III elements and Group V elements may diffuse the Group III or Group V elements into the active layer portion of the transistor and the entire manufacturing apparatus during heat treatment, which may affect the characteristics of the completed transistor. Therefore, it is not preferable.
[0027]
1 and 2 are process diagrams illustrating an embodiment of a method for manufacturing a MOS transistor to which the present invention is applied. In this embodiment, a manufacturing process of a thin film transistor (TFT) will be described. However, the application range of the present invention is not limited to the TFT, and a general MOS transistor using a semiconductor substrate as the active layer of the transistor itself and a general MOS transistor. It goes without saying that the integrated circuit and the like used are also included.
[0028]
(Formation of semiconductor thin film)
As shown in FIG. 1A, a base protective film 12 is formed on a substrate 11. As the substrate 11, various substrates such as a quartz substrate, a glass substrate, a transparent insulating substrate such as a heat-resistant plastic, an opaque insulating substrate such as a ceramic, a conductive substrate such as a metal, and a semiconductor substrate can be used. The base protective film 12 prevents mobile ions such as sodium contained in a glass substrate or the like from entering the semiconductor film 13. The underlying protective film 22 is made of a silicon oxide film (SiO _x : 0 <x ≦ 2) or a silicon nitride film (Si ₃ N _x : 0 <x ≦ 2) or a laminated film thereof.
[0029]
The underlayer protective film 12 is formed by cleaning the substrate 11 with an organic solvent such as pure water or alcohol, or an acid such as sulfuric acid or nitric acid, and then applying normal pressure chemical vapor deposition (APCVD) or low pressure chemical vapor deposition on the substrate 11. It is formed by a CVD method such as a plasma CVD method (LPCVD method), a plasma chemical vapor deposition method (PECVD method), or a sputtering method. When a silicon oxide film is used as the base protective film 12, the substrate temperature is set to about 250 ° C. to about 450 ° C. in the APCVD method, and monosilane (SiH ₄ ) Or oxygen as a raw material. In the PECVD method and the sputtering method, the substrate temperature is from room temperature to about 400 ° C. When a silicon oxide film is used as the base protective film 12 in the PECVD method, monosilane and oxygen or nitrous oxide (N ₂ O) can be formed as a raw material. When a silicon nitride film is used, monosilane and ammonia (NH ₃ ) Or nitrogen as the source gas. The thickness of the base protective film 12 is set to a thickness sufficient to prevent diffusion and mixing of the impurity element from the substrate. For example, it is about 100 nm or more. Considering the variation between lots and substrates, the thickness is preferably about 200 nm or more, and if it is about 300 nm, the function as a protective film can be sufficiently achieved. If the underlying protective film (insulating film) 12 is too thick, cracks are likely to occur due to the stress of the film. From this point, the maximum film thickness is preferably about 2 μm, but when importance is placed on productivity, the film thickness of the base protective film is preferably about 300 nm.
[0030]
Next, as shown in FIG. 1B, a semiconductor film 13 is formed on the underlying protective film 12. Although the above-described underlayer protective film 12 is not essential, when a semiconductor thin film transistor is formed on a glass substrate, it is important to control impurities in the semiconductor film 13. It is preferable to deposit the semiconductor film 13 after forming the base protective film 12 so as not to be mixed in the film 13.
[0031]
As the semiconductor film 13, in addition to a single-layer semiconductor film of Group 4 such as silicon (Si) and germanium (Ge), silicon-germanium (Si) _x Ge _1-x : 0 <x <1) or silicon carbide (Si _x C _1-x : 0 <x <1) or germanium carbide (Ge _x C _1-x : A semiconductor film of a group 4 element complex such as 0 <x <1), a composite compound semiconductor film of a group 3 element and a group 5 element such as gallium arsenide (GaAs) or indium antimony (InSb), or There is a composite compound semiconductor film of a group 2 element such as cadmium selenium (CdSe) and a group 6 element.
[0032]
In addition, silicon, germanium, gallium, arsenic (Si _x Ge _y Ga _z As _z : X + y + z = 1), an N-type semiconductor film obtained by further adding a donor element such as phosphorus (P), arsenic (As), antimony (Sb) to a compound semiconductor film such as x + y + z = 1) or boron; The present invention is also applicable to a P-type semiconductor film to which an acceptor element such as aluminum (Al), gallium (Ga), and indium (In) is added.
[0033]
These semiconductor films 13 are formed by a CVD method such as an APCVD method, an LPCVD method, or a PECVD method, or a PVD method such as a sputtering method or an evaporation method.
[0034]
When a silicon film is used as the semiconductor film 13, in the LPCVD method, the substrate temperature is set to about 400 ° C. to about 700 ° C. and disilane (Si ₂ H ₆ ) Is deposited as a raw material to deposit silicon. In the PECVD method, monosilane (SiH ₄ ) Can be deposited at a substrate temperature of about 100 ° C. to about 500 ° C.
[0035]
When using the sputtering method, the substrate temperature is from room temperature to about 400 ° C. As described above, the initial state of the deposited semiconductor film 13 includes various states such as amorphous, mixed crystal, microcrystalline, and polycrystalline. However, the initial state may be any state. When the semiconductor film 13 is used for a semiconductor thin film transistor, the thickness is suitably about 20 nm to 100 nm.
[0036]
(Crystallization of semiconductor thin film)
Next, the deposited semiconductor film 13 is crystallized. Here, the term “crystallization” refers to applying thermal energy to an amorphous semiconductor film to transform it into a polycrystalline or single-crystal semiconductor film, and furthermore, a microcrystalline film or a polycrystalline semiconductor film. Is applied to improve the film quality of the crystal film or to perform recrystallization by melting and solidifying by applying heat energy to the film. In the present description, not only amorphous crystallization but also polycrystalline or microcrystalline crystallization is referred to as crystallization.
[0037]
The step of crystallizing the semiconductor film 13 can be realized by a method using so-called laser irradiation or a method using solid-phase growth, but is not limited thereto.
[0038]
As an example, a crystallization method by laser irradiation that can be performed by a low-temperature process in a method of manufacturing a polysilicon TFT will be described.
[0039]
The substrate on which the semiconductor film 13 is formed is set in a laser irradiation chamber (not shown). The laser irradiation chamber is partially formed by a quartz window, and the laser light is emitted from the quartz window after the atmosphere in the chamber is replaced in a vacuum or by a non-oxidizing gas. It is desirable that this laser light is strongly absorbed by the film surface of the semiconductor film 13 and hardly absorbed by the base insulating film 12 and the substrate 11. As the laser light, an excimer laser, an argon ion laser, a YAG laser harmonic, or the like having a wavelength in or near the ultraviolet region is preferable. In addition, in order to heat the semiconductor film 13 to a high temperature and prevent damage to the substrate 11 at the same time, it is necessary that the pulse oscillation be performed at a high output and for a very short time. Among the above laser beams, an excimer laser such as a xenon chloride (XeCl) laser (wavelength 308 nm) or a krypton fluoride (KrF) laser (wavelength 248 nm) is most suitable.
[0040]
A method for irradiating these laser beams will be described. The half width of the laser pulse intensity is very short, about 10 ns to about 500 ns. The laser irradiation is performed on the substrate 11 at about room temperature (25 ° C.) to 400 ° C. One irradiation area of the laser irradiation has a square or rectangular shape with a diagonal of about 5 mm to about 60 mm.
[0041]
For example, a case is described in which a beam that can crystallize a square area of about 8 mm square by one laser irradiation is used. After one laser irradiation to one place, the position of the laser is slightly shifted in the horizontal direction relatively to the substrate. Thereafter, one laser irradiation is performed again. By repeating this shot and scan continuously, it is possible to cope with a large area substrate. More specifically, shots are repeated with the irradiation area shifted from about 1% to about 99% for each irradiation.
[0042]
After scanning in the horizontal direction (X direction) first, the shot and scan are continuously performed while being shifted in the vertical direction (Y direction) by an appropriate amount and again shifted in the horizontal direction by a predetermined amount. Thereafter, this is repeated to perform the first laser irradiation on the entire surface of the substrate.
[0043]
This first laser irradiation energy density is 50 mJ / cm in the case of a xenon chloride laser. ² About 600mJ / cm ² Between degrees is preferred. After the first laser irradiation is completed, the second laser irradiation is performed on the entire surface as necessary.
[0044]
When performing the second laser irradiation, the energy density thereof is preferably higher than that of the first laser irradiation, and is 100 mJ / cm. ² From about 1000mJ / cm ² It may be between degrees. The scanning method is the same as that of the first laser irradiation, and scans the irradiation area in the forward direction by shifting the irradiation area in the Y direction and the X direction by an appropriate amount.
[0045]
Further, it is also possible to perform the third or fourth laser irradiation with a higher energy density as needed. When such a multi-step laser irradiation method is used, it is possible to completely eliminate the variation caused by the end of the laser irradiation area.
[0046]
Not only in each of the multi-stage laser irradiations, but also in the ordinary single-stage irradiation, all the laser irradiations are performed at an energy about 5% lower than the energy density at which the semiconductor film 13 is completely melted. Once the silicon film is completely melted, the liquid silicon film falls into a supercooled state, and as a result, high-density crystal nuclei are generated.
[0047]
The poly-Si film formed by such a phenomenon has a form of so-called microcrystal in which extremely small crystal grains exist at a high density. Since such a poly-Si film has many crystal grain boundaries, a large number of defects (mainly, dangling bonds) are present in the film, and the film cannot be used as a TFT.
[0048]
Although the laser crystallization method using a square laser beam has been described above, the irradiation region is formed into a line having a width of about 100 μm or more and a length of several tens of cm or more, and the linear laser light is scanned for crystallization. You may proceed. In this case, the overlap in the width direction of the beam for each irradiation is about 5% to about 95% of the beam width. If the beam width is 100 μm and the overlap amount for each beam is 90%, the beam advances 10 μm for each irradiation, so that the same point receives 10 laser irradiations.
[0049]
Generally, at least about five times of laser irradiation is desirable in order to uniformly crystallize a semiconductor film over the entire substrate. Therefore, the beam overlap amount for each irradiation needs to be about 80% or more. In order to reliably obtain a polycrystalline film having high crystallinity, it is preferable to adjust the overlap amount from about 90% to about 97% so that the same point is irradiated about 10 to 30 times. By using a line beam, crystallization of a large area can be performed by scanning in one direction, so that there is an advantage that the throughput can be increased as compared with the square beam described above.
[0050]
In addition, by repeating the irradiation many times as described above, the activation rate of the impurities implanted in the semiconductor film can be increased. The maximum irradiation energy density at this time follows the above-described condition.
[0051]
So far, the case of a polysilicon TFT manufactured by a low-temperature process has been described. However, as described at the beginning of the embodiment of the present invention, a semiconductor substrate is used as a substrate and this is used as it is as an active layer of a transistor. It is also possible. In this case, the steps of forming the underlayer protective film, forming the semiconductor thin film, and crystallizing the semiconductor thin film as described above become unnecessary.
[0052]
(Element separation process)
Next, element isolation for defining a region of the transistor is performed. As a device isolation technique, a LOCOS method, a field shield method, an STI method, or the like can be used. Here, a method of performing element isolation by photolithography and etching in a TFT manufacturing process will be described.
[0053]
As shown in FIG. 1C, a mask pattern using a photoresist 14 is formed by photolithography so that only a region serving as an active layer of the transistor remains.
[0054]
Next, as shown in FIG. 1D, the semiconductor film 13 is etched using the resist 14 as a mask. At this time, the etching is performed so that the end of the semiconductor film 13 has an inclined tapered surface. For example, the edge of the semiconductor film 13 is formed obliquely by performing etching by isotropic etching such as wet etching or dry etching. For example, chemical dry etching uses carbon tetrafluoride (CF ₄ ), Oxygen gas (O ₂ ) Can be adopted for the remote plasma system using a mixed gas containing
[0055]
Further, as shown in FIG. 11, the semiconductor film 13 may be etched by anisotropic etching such as reactive ion etching (RIE) with the end of the photoresist mask 14 having a tapered surface. In this case, the film thickness and the taper angle of the mask 14 are taken into consideration in consideration of the speed ratio between the etching speed of the semiconductor film 13 and the etching speed of the photoresist mask 14 so that the tapered surface shape of the mask is transferred to the semiconductor film. Is selected.
[0056]
As a method of making the end portion of the mask 14 a tapered surface, a method of defocusing at the time of pattern exposure to a photoresist, a method of pattern exposure to a photoresist using an intermediate gradation mask, and the like are appropriately selected. Thus, an appropriate tapered surface is formed on the mask 14. It is preferable that the inclination angle θ of the tapered surface be 80 degrees or less from the viewpoint of step coverage.
[0057]
After the tapered surface is formed on the semiconductor film 13 in this manner, the photoresist (mask) 14 is peeled off as shown in FIG.
[0058]
(Formation of gate insulating film)
Next, as shown in FIG. 1F, after patterning the semiconductor film 13, an insulating film 15 is formed thereon as a gate insulating layer of the TFT.
[0059]
The insulating film 15 may be formed on the substrate 11 by a CVD method such as an atmospheric pressure chemical vapor deposition method (APCVD method), a low pressure chemical vapor deposition method (LPCVD method), or a plasma chemical vapor deposition method (PECVD method). An insulating material is deposited by a sputtering method or the like. Either method can be used to form an insulating film.
[0060]
In the present invention, in particular, TEOS (tetraethoxysilane; Si (OC ₂ H ₅ ) ₄ ) And a silicon oxide film (SiO 2) using parallel plate RF plasma CVD using oxygen gas. ₂ ) Is formed as the insulating film 15. As will be described later, the MOS interface can be improved by combining this process with the semiconductor film deposition and heat treatment performed in the subsequent steps.
[0061]
In this case, the gas used in the vacuum plasma chamber is TEOS, oxygen gas O ₂ However, a diluting gas such as helium He or argon Ar may be mixed. The degree of vacuum during film formation is preferably about 100 to 200 Pa, and the substrate temperature during film formation is preferably about 350 ° C. to 450 ° C. By forming the film under such conditions, a high-quality silicon oxide film (gate insulating film) 15 having a high withstand voltage and a low charge density can be obtained.
[0062]
(Semiconductor layer deposition, heat treatment)
Next, a semiconductor film 16 is deposited on the gate insulating film 15 as shown in FIG. Here, silicon or germanium, which is a Group 4 element, is optimal as the semiconductor.
[0063]
Although any method such as a sputtering method, an evaporation method, and a CVD method may be used as a method for depositing the semiconductor film 16, a PECVD method is the most common method for depositing a semiconductor film over a wide area. When a silicon film is deposited by PECVD, monosilane or the like can be used as a source gas, and when a germanium film is deposited, monogermane or the like can be used as a source gas at a substrate temperature of about 100 ° C. to 500 ° C. The semiconductor film is desirably amorphous. Although a crystalline semiconductor has an effect of reducing defects at the MOS interface in a heat treatment step to be performed later, the effect is larger in an amorphous state, and the amorphous state can be easily obtained even in a low-temperature process. It has many advantages, for example, it can be formed, and a film forming apparatus is inexpensive and the area can be easily increased.
[0064]
Note that a compound semiconductor such as GaAs may contaminate the device in a later heat treatment step or the like, or may diffuse into the silicon oxide film 15 or the semiconductor film 13 serving as an active layer of the transistor, thereby affecting the characteristics of the transistor. It is not preferable because it may cause
[0065]
After these appropriate semiconductor films 16 are deposited, heat treatment is performed. The heat treatment may be performed in a heated furnace or by irradiating light energy such as laser light or halogen lamp light.
[0066]
When the heat treatment is performed in a furnace, the heat treatment is performed in a furnace heated to a temperature of 300 ° C. or more and 450 ° C. or less for 10 minutes or more. When the substrate is introduced into a furnace at 300 ° C. or higher, it generally takes about 20 minutes for the substrate temperature to stabilize. Therefore, it is preferable to perform the heat treatment for about 30 minutes or more. The atmosphere during the heat treatment may be any atmosphere. By performing this heat treatment, the charge density of the silicon oxide film 15 and the level density at the interface between the semiconductor film 13 and the silicon oxide film 15 are reduced while maintaining the excellent characteristics of the withstand voltage of the silicon oxide film 15. be able to. As will be described later, by performing experiments, amorphous silicon is deposited on the gate insulating film, and then heat treatment is performed at 400 ° C. for 30 minutes in a nitrogen atmosphere. ¹⁰ (Cm ^-2 eV ^-1 ) It was confirmed that it was reduced to the following. This interface state density is an extremely low value comparable to the interface state density of the thermal oxide film, and it can be said that a good interface is formed.
[0067]
The method of irradiating light energy can be performed, for example, by the method described in the section of crystallization of the semiconductor film. At this time, the semiconductor film 16 is instantaneously heated, and the heat is transmitted to the silicon oxide film 15 and the semiconductor film 13 to perform heat treatment, thereby reducing defects at the silicon oxide film 15 and the MOS interface.
[0068]
The reason that the defects are reduced as described above is that the hydrogen H in the silicon oxide film 15 is reduced. ₂ And oxygen O ₂ , Moisture H ₂ O is decomposed by the semiconductor film 16 during the heat treatment, and the unbonded end of the silicon oxide becomes water vapor H. ₂ It is presumed to be due to termination by atomic hydrogen, atomic oxygen, hydrogen ions, hydroxy ions, oxygen ions, etc. generated by decomposition of O or the like.
[0069]
(Semiconductor film removal)
Next, as shown in FIG. 1H, the semiconductor film 16 is removed by etching. In consideration of compatibility with the subsequent steps, or when it is desired to use a more preferable material for the gate wiring film, the entire surface of the semiconductor film 16 in the previous step is removed by etching. In other words, when the optimum active metal film 16 and the optimum gate wiring film are made of different materials, the active metal film 16 is removed and the gate wiring film 17 described below is formed again.
[0070]
(Gate wiring formation)
As shown in FIG. 2I, a gate wiring film 17 is formed on the silicon oxide film (gate insulating film) 15. At this time, without removing the semiconductor film 16 used in the previous step, it can be used as the whole or a part of the gate wiring film 17 as it is. In this case, the step of removing the semiconductor film 16 and the step of newly depositing the gate wiring film 17 become unnecessary, and the transistor manufacturing process can be shortened.
[0071]
Further, a gate wiring film 17 made of a different material from the semiconductor film 16 may be newly deposited. The gate wiring film 17 is deposited by selecting an appropriate deposition method such as a sputtering method, a CVD method, or an evaporation method, and depositing an appropriate metal such as tantalum or aluminum, polysilicon, or an alloy of polysilicon and a metal. Can be.
[0072]
Next, as shown in FIG. 2J, the gate wiring film 17 is patterned to form the gate wiring 17. The patterning at this time is performed by photolithography and etching.
[0073]
(Impurity injection and activation process)
Subsequently, impurity ions are implanted into the semiconductor film 15 to form source / drain regions. At this time, since the gate electrode 17 serves as a mask for ion implantation, the channel has a self-aligned structure formed only under the gate electrode. Impurity ion implantation is an ion doping method in which hydride and hydrogen of an impurity element are implanted using a mass non-separable ion implanter, and an ion implantation method in which only a desired impurity element is implanted using a mass separable ion implanter. Two types of law can be applied. As a source gas for the ion doping method, phosphine (PH) having a concentration of about 0.1% to about 10% diluted in hydrogen is used. ₃ ) And diborane (B ₂ H ₆ ) And the like are used. In order to keep the gate insulating film stable, the substrate temperature at the time of ion implantation is preferably 350 ° C. or lower in both the ion doping method and the ion implantation method. When fabricating a CMOS-TFT, one of an NMOS and a PMOS is alternately covered with a mask using an appropriate mask material such as a polyimide resin, and the respective ions are implanted by the above-described method. The impurity concentration in the source and drain portions in this impurity implantation step is 1 × 10 ¹⁹ cm ^-3 1x10 ²¹ cm ^-3 It is desirable to make the following. In the case where the impurity concentration is as described above, the resistance of the source and drain portions is sufficiently reduced by performing the impurity activation step later. When a semiconductor film is used as the gate electrode 17, the impurity is implanted into the semiconductor used as the gate electrode, whereby the resistance of the gate electrode can be reduced. In particular, when heat treatment for improving the film quality of the gate insulating film 15 is performed by laser light irradiation immediately after the formation of the semiconductor film 16, the semiconductor film 16 can be crystallized. When the gate electrode is used as the gate wiring layer 17, the impurity having the above concentration is implanted using the gate electrode as a mask, so that the gate electrode can have a sufficiently low resistance by carriers from the implanted impurity.
[0074]
Next, activation of impurities is performed. Examples of the activation method include a method by laser irradiation, a method of heating in a furnace at 300 ° C. or higher (low-temperature heat treatment), a high-speed heat treatment by a lamp, and the like. An appropriate method can be selected. It is important that the temperature of the portion of the semiconductor film 13 be 350 ° C. or less at the maximum.
[0075]
(Subsequent process)
Up to this step, the element isolation of the semiconductor film 13 is completed, and the formation of the gate wiring film 16 is also completed. It is important to carry out the process at a substrate temperature of 350 ° C. or less until the MOS transistor is completed in the subsequent steps.
[0076]
Next, as shown in FIG. 2K, silicon oxide is deposited on the substrate 11 by a CVD method or the like, and an interlayer insulating film 18 is formed.
[0077]
As shown in FIG. 2L, contact holes are formed in the source and drain portions of the interlayer insulating film 18 and the gate insulating film 15, and a metal such as aluminum is deposited by a sputtering method or the like to form a wiring film 19. .
[0078]
Next, as shown in FIG. 2M, the wiring film 19 is patterned to form source and drain electrodes and the wiring 19. A thin film transistor is completed by depositing a protective film 20 of silicon oxide, silicon nitride, PSG or the like thereon.
[0079]
In the description of the present embodiment, the steps are performed in the order described above. For example, element isolation is performed after the gate insulating film 15 is formed, or a resist mask or another metal mask is formed before the gate wiring film 15 is formed. The order of the steps may be changed as appropriate, for example, by implanting impurities using the above method.
[0080]
Further, a step of improving the film quality of the semiconductor film 13 or the gate insulating film 15 by plasma treatment or the like immediately after crystallization or immediately after the formation of the gate insulating film 15 may be included.
[0081]
Furthermore, in the case where the semiconductor film 16 immediately after the formation of the gate insulating film 15 is used as it is as all or a part of the gate wiring 17, there is a step of performing a heat treatment at 300 ° C. or more and 10 minutes or more in a subsequent step. In this case, the above-described heat treatment step immediately after the formation of the semiconductor layer 16 can be omitted.
[0082]
Next, characteristics of the gate insulating film obtained by the above embodiment will be described with reference to FIGS.
[0083]
3 and 4 show a manufacturing process according to the present invention, that is, an insulating film (silicon oxide film) is formed by a parallel plate RF plasma CVD method using TEOS and oxygen as source gases, and then a silicon film is deposited. 9 is a graph illustrating characteristics of an insulating film when heat treatment (nitrogen atmosphere, 400 ° C., 1 hour) is performed.
[0084]
FIG. 3 shows a capacitance (C) -gate voltage (V) characteristic (CV characteristic) of a gate insulating film of a MOS transistor in a manufacturing process according to the present invention. The low frequency (Low) characteristic curve in the figure shows the characteristic when the gate voltage frequency is 5 to 10 Hz, and the high frequency (High) characteristic curve shows the characteristic when the gate voltage application frequency is 100 kHz. ing. From these two curves, the level density at the interface between the semiconductor film and the gate insulating film can be obtained (Quasistatic Method). According to this, the interface state density Dit (Density of interface trapstate) is 2.4 × 10 ¹⁰ / Cm ² eV, which is a sufficiently low value. It can be seen that the shift of the flat band voltage is sufficiently small and the charge density in the gate insulating film is also small. From this CV characteristic curve, it can be seen that a good gate insulating film and an interface are formed.
[0085]
FIG. 4 shows a current density (I) versus electric field strength (V) characteristic (IV characteristic) of a gate insulating film in a MOS transistor manufacturing process according to the present invention. A total of five measurements are performed, and the respective IV characteristics are superimposed and displayed in the figure. Dielectric breakdown occurs in a portion where the current suddenly increases with respect to the applied electric field (horizontal axis). 1x10 at current density ^-2 A / cm ² If the applied electric field when the current flows is defined as the withstand voltage, the withstand voltage is 8 MV / cm or more, which indicates the same high insulating property as a silicon thermal oxide film.
[0086]
As described above, according to the manufacturing process of the present invention, a favorable gate insulating film having an interface with few crystal defects and a high withstand voltage is obtained.
[0087]
FIGS. 5 and 6 are graphs illustrating advantages of the present invention based on a characteristic example (comparative example) of a gate insulating film in a conventional low-temperature polysilicon TFT manufacturing process.
FIG. 5 shows a method of depositing a gate insulating film most commonly used in a low-temperature process, using a parallel plate RF plasma CVD method, using TEOS and oxygen as source gases and forming a SiO 2 as a gate insulating film on a Si substrate. ₂ This shows an example of CV characteristics when a film is deposited and a heat treatment is performed at 400 ° C. for one hour in a nitrogen atmosphere without depositing a semiconductor film on the gate insulating film. Under this condition, the interface state density Dit is 8.5 × 10 ¹¹ / Cm ² eV. This insulating film differs from the insulating film having the characteristics shown in FIG. 3 only in whether or not a silicon film exists on the gate insulating film at the time of heat treatment. 5 and FIG. 3 clearly show that heat treatment in a state where a semiconductor film is present on the gate insulating film as in the present invention is extremely effective for forming a high quality MOS interface. .
[0088]
FIG. 6 shows an example of IV characteristics of a gate insulating film of another comparative example. The method for forming the gate insulating film shown in FIG. 6 is a method in which SiH4 and O2 are used as source gases and deposited at a substrate temperature of about 25 [deg.] C. by an ECR-plasma CVD method, and heat treatment is performed. According to this method, it is conventionally known that the Dit at the MOS interface is equivalent to that of the present invention, and it has been confirmed by the author's experiment. However, as shown in FIG. 6, the dielectric withstand voltage of this film is about 2.5 MV / cm on average, and the insulation of the gate insulating film is not sufficient.
[0089]
Therefore, TEOS and O ₂ The process of the present invention in which an insulating film is formed by a parallel plate type plasma CVD method using as a source gas, a semiconductor film is deposited on the insulating film, and heat treatment is performed, has better characteristics (interface defects, It has become clear to provide a gate insulating film having a withstand voltage.
[0090]
FIGS. 7 and 8 show another method of forming a gate insulating film by using an ECR-plasma CVD method at a substrate temperature of about 300.degree. ₄ And O ₂ Using SiO as the source gas ₂ FIG. 9 is a graph illustrating the degree of improvement of the MOS interface by heat treatment (Comparative Example 2) in the case where heat treatment (400 ° C., nitrogen atmosphere, 1 hour) is performed by depositing silicon thereon and then performing heat treatment (400 ° C., nitrogen atmosphere, 1 hour).
[0091]
FIG. 7 shows CV characteristics when a silicon oxide film is deposited using silane and oxygen at a substrate temperature of about 300 ° C. by an ECR-plasma CVD method and a heat treatment is performed at 400 ° C. for 1 hour in a nitrogen atmosphere. Is shown. In this example, the interface state density Dit is 5.5 × 10 ¹¹ / Cm ² eV.
[0092]
On the other hand, FIG. 8 shows that a silicon oxide film is deposited using silane and oxygen as materials by ECR-plasma CVD method, and further, a silicon film is deposited on the silicon oxide film, and then at 400 ° C., 1 ° C. in a nitrogen atmosphere. This shows the CV characteristics when heat treatment is performed for a long time. In this example, the interface state density Dit is 3.5 × 10 ¹¹ / Cm ² eV.
[0093]
Thus, even if the method of depositing the silicon oxide film is changed, the effect of reducing the Dit at the MOS interface due to the presence of the silicon film on the gate silicon oxide film during the heat treatment can be confirmed. Therefore, the effectiveness of the presence of the semiconductor film on the gate insulating film during the heat treatment is apparent. However, there is a great difference in the magnitude of the Dit reduction effect depending on the method of depositing the gate insulating film. ₂ It is desirable to deposit a film.
[0094]
【Example】
Next, a more preferred embodiment of the present invention will be described with reference to FIGS.
[0095]
The substrate 11 and the underlying protective film 12 used in the present invention follow the above description, but here, a 300 mm × 300 mm square general-purpose non-alkali glass is used as an example of the substrate 11. First, a base protective film 12 as an insulating material was formed on a substrate 11. In the example, a silicon oxide film 12 having a thickness of about 500 nm was deposited by a parallel plate type PECVD apparatus (FIG. 1A).
[0096]
Next, an intrinsic silicon film was formed as the semiconductor film 13 to be an active layer of the thin film transistor later. The thickness of the semiconductor film 13 was about 50 nm. In this example, a high-vacuum LPCVD apparatus is used to produce disilane (Si ₂ H ₆ ) At about 200 SCCM to deposit an amorphous silicon film at a deposition temperature of 425 ° C.
[0097]
First, a plurality of (for example, 17) substrates were placed inside a reaction chamber of a high-vacuum LPCVD apparatus at 250 ° C. with the front side facing down. After this, the operation of the turbo-molecular pump was started. After the turbo molecular pump reached steady state rotation, the temperature in the reaction chamber was increased from 250 ° C. to a deposition temperature of 425 ° C. over about one hour. During the first 10 minutes after the start of the temperature rise, the temperature was raised in a vacuum without introducing any gas into the reaction chamber, and thereafter, nitrogen gas having a purity of 99.9999% or more was continuously flowed at 300 SCCM. The equilibrium pressure in the reaction chamber at this time was 3.0 × 10 ^-3 Torr. After reaching the deposition temperature, disilane (Si ₂ H ₆ ) Was flowed at 200 SCCM, and helium (He) for dilution having a purity of 99.9999% or more was flowed at 1000 SCCM. The pressure in the reaction chamber immediately after the start of the deposition was about 0.85 Torr. As the deposition progressed, the pressure in the reaction chamber gradually increased, and the pressure immediately before the termination of the deposition was approximately 1.25 Torr. The thickness of the silicon film 13 thus deposited was within ± 5% within a 286 mm square region excluding the peripheral portion of about 7 mm of the substrate 11.
[0098]
Next, irradiation with one laser beam was performed. In this example, an excimer laser (wavelength: 308 nm) of xenon chloride (XeCl) was irradiated at a substrate temperature of 25 ° C. in a vacuum chamber. The half width of the laser pulse intensity (half width with respect to time) was 25 nS.
[0099]
One laser irradiation area is a line shape of 150 mm length × 400 μm width, and the energy density on the irradiation surface is 400 mJ / cm. ² Met. Irradiation was repeated while overlapping the laser beams by 95% in the width direction (that is, by 20 μm for each irradiation) and relatively shifted. Thus, the amorphous silicon of the entire substrate having a side of 300 mm was crystallized. In order to minimize the occurrence of roughness at the crystal grain boundaries of the semiconductor layer due to crystallization, the edge region is 200 μm before and after the edge region in the width direction of the line beam (that is, a region with a low energy density). 400 mJ / cm for (a-Si) ² Before the laser irradiation with the energy density of? Was performed, the laser irradiation with lower energy was performed. By increasing the irradiation energy stepwise as described above, crystallization was performed while suppressing the surface roughness (FIG. 1B).
[0100]
Next, in order to perform photolithography, a photoresist 14 was applied, and a portion to be an active layer of the transistor was patterned (FIG. 1C). Using this as a mask, the semiconductor film 13 was etched to perform element isolation. As a method of etching the semiconductor film 13, CF ₄ Gas and oxygen gas O ₂ The chemical dry etching of the remote plasma method was performed using the mixed gas of FIG. 1 (FIG. 1D). Thereby, the end portion of the semiconductor layer 13 has a tapered surface, and for example, a tapered surface with an inclination angle of about 60 degrees could be obtained. After the etching of the semiconductor film 13, the photoresist 14 was removed by ashing using atmospheric pressure oxygen plasma (FIG. 1E).
[0101]
Next, the substrate 11 was transferred to a process chamber of a parallel plate type RF plasma CVD apparatus for forming an insulating film. TEOS gas and oxygen O in the chamber ₂ Gas and helium He gas were introduced, and the chamber pressure was adjusted to 1 (Torr). At this time, the substrate temperature was adjusted to 400 ° C. When the gas pressure in the chamber was stabilized, RF (high frequency) discharge was started, and formation of a silicon oxide film was started. The input microwave power was 1 kW. The film was formed at a film formation rate of 100 nm / min. Thereby, the gate insulating film 15 was formed to have a thickness of 100 nm (FIG. 1F).
[0102]
Next, the substrate 11 was transferred to a process chamber of a parallel plate RF plasma CVD apparatus for depositing amorphous silicon. Amorphous silicon is used as the semiconductor layer 16 at a substrate temperature of 300.degree. ₄ Using a gas as a source gas, deposition was performed by 200 nm sputtering. At this time, the chamber pressure was 1 Torr, and RF power of 1 kW was applied (FIG. 1 (g)).
[0103]
Next, the substrate 11 is placed in a furnace, heated to 400 ° C., and subjected to a heat treatment in a nitrogen atmosphere for 30 minutes. Then, the substrate 11 is taken out and subjected to chemical dry etching of a remote plasma method using CF 4 and oxygen. The entire surface of the amorphous silicon film 16 was removed (FIG. 1H).
[0104]
Next, a tantalum thin film 17 having a thickness of 600 nm to be a gate electrode 16 was formed by a sputtering method. The substrate temperature when forming the tantalum thin film was 180 ° C. (FIG. 2 (i)).
[0105]
The thin film 17 serving as a gate electrode was patterned by photolithography and etching, and subsequently, impurity ions were implanted into the semiconductor film 13 to form source / drain regions and channel regions. At this time, since the gate electrode 17 serves as a mask for ion implantation, the channel has a self-aligned structure formed only under the gate electrode. In this example, phosphine (PH) is used as a source gas by using an ion implantation apparatus with the aim of forming an NMOS. ₃ ) Was implanted at an acceleration voltage of 100 keV. The ion implantation amount is 1 × 10 ¹⁶ cm ^-2 Met.
[0106]
Next, heat treatment was performed at 300 ° C. for 4 hours in a nitrogen atmosphere to activate the implanted impurity phosphorus.
[0107]
Next, a 500 nm silicon oxide film was deposited as an interlayer insulating film 18 at a substrate temperature of 300 ° C. by parallel plate PECVD using a mixed gas of TEOS gas and oxygen gas (FIG. 2K). Next, contact holes are formed on the source / drain, and aluminum is deposited as a source / drain extraction electrode and a wiring film 19 at a substrate temperature of 150 ° C. by a sputtering method (FIG. 2 (l)), and the film 19 is patterned. Then, a protective film was deposited to complete a thin film transistor (FIG. 2 (m)).
[0108]
The MOS transistor manufactured by the manufacturing process of the present invention is particularly suitable for use in an electro-optical device such as a semiconductor integrated circuit device, a liquid crystal display device, and an organic EL display device. An example of an electronic device including such a display device will be described below, but the application of the present invention is not limited to the example.
[0109]
<Mobile computer>
First, an example in which the display device including the transistor according to the above-described embodiment is applied to a mobile personal computer (information processing device) will be described. FIG. 9 is a perspective view showing the configuration of this personal computer. In the figure, a personal computer 1100 includes a main body 1104 having a keyboard 1102, and a display device unit having the above-described display device 1106. Further, the inside of the personal computer includes many of the above-mentioned semiconductor integrated circuits not shown.
[0110]
<mobile phone>
Next, an example in which the display device according to the above-described embodiment is applied to a display unit of a mobile phone will be described. FIG. 10 is a perspective view showing the configuration of the mobile phone. In the figure, a mobile phone 1200 includes, in addition to a plurality of operation buttons 1202, an earpiece 1024, a mouthpiece 1206, the above-described display device 1208, and the above-described semiconductor integrated circuit (not shown).
[0111]
<Digital still camera>
A digital still camera using the display device according to the above-described embodiment as a finder will be described. FIG. 11 is a perspective view showing the configuration of the digital still camera, but also simply shows the connection with an external device.
[0112]
While an ordinary camera exposes a film with an optical image of a subject, the digital still camera 1300 photoelectrically converts the optical image of the subject with an image sensor such as a CCD (Charge Coupled Device) to generate an image signal. The display device 1304 described above is provided on the back of the case 1302 of the digital still camera 1300, and is configured to perform display based on an imaging signal from a CCD. Therefore, the display device 1304 functions as a finder that displays a subject. A light receiving unit including an optical lens, a CCD, and the like is provided on the observation side (the back side in the figure) of the case 1302.
[0113]
When the photographer confirms the image of the subject displayed on the display device 1304 and presses the shutter button 1308, the imaging signal of the CCD at that time is transferred and stored in the memory of the circuit board 1310. Further, the digital still camera 1300 includes a video signal output terminal 1312 and an input / output terminal 1314 for data communication on a side surface of the case 1302. As shown in the figure, a television monitor 1430 is connected to a video signal output terminal 1312, and a personal computer 1430 is connected to an input / output terminal 1314 for data communication as necessary. By this operation, the imaging signal stored in the memory of the circuit board 1308 is output to the television monitor 1330 and the computer 1340.
[0114]
As described above, complicated signal processing is performed in the digital still camera, and a plurality of the above-described semiconductor integrated circuits are included for the signal processing and image storage.
[0115]
<E-book>
FIG. 12 is a perspective view showing a configuration of an electronic book as an example of the electronic apparatus of the present invention. In the figure, reference numeral 1400 indicates an electronic book. The electronic book 1400 has a book-type frame 1402 and a cover 1403 that can be opened and closed on the frame 1402. The frame 1402 is provided with a display device 1404 with a display surface exposed on the surface thereof, and further provided with an operation unit 1405. The frame 1402 contains a plurality of the above-described semiconductor integrated circuits such as a controller, a counter, and a memory. In the present embodiment, the display device 1404 includes a pixel portion formed by filling a thin film element with electronic ink, and a peripheral circuit integrated with the pixel portion and integrated. The peripheral circuit includes a decoder-type scan driver and a data driver.
[0116]
In addition to the personal computer shown in FIG. 9, the digital still camera shown in FIG. 11, and the electronic book shown in FIG. 12, electronic paper and a liquid crystal television, a viewfinder type, and a monitor Type video tape recorders, car navigation devices, pagers, electronic organizers, calculators, word processors, workstations, videophones, POS terminals, devices with touch panels, and the like. The display device described above can be applied to the display units of these various electronic devices.
[0117]
As described above, in the conventional MOS transistor manufacturing technology, particularly in a low-temperature process, it is possible to simultaneously reduce the defect density at the MOS interface, reduce the charge density of the gate insulating film, and increase the withstand voltage. It is difficult, and there is a limit in improving the performance of the transistor. According to the present invention, an extremely high-quality gate insulating film can be formed at a low temperature, and a high-performance transistor can be manufactured by a low-temperature process.
[0118]
The present invention is applicable not only to MOS transistors but also to all semiconductor devices that require a high-quality silicon oxide / silicon interface and bulk characteristics of a silicon oxide film. Further, the present invention can be applied to all semiconductor elements and the like in which a protective film having a low interface state density needs to be formed of a silicon oxide film as a protective film for a semiconductor film. In particular, this is an extremely effective means when formation at a low temperature is essential.
[0119]
【The invention's effect】
According to the present invention, a semiconductor film is deposited after a gate insulating film is deposited, and heat treatment is performed to obtain a high-quality gate insulating film with a reduced defect density at a MOS interface. It is possible to manufacture a simple transistor.
[Brief description of the drawings]
FIG. 1 is a process diagram illustrating an embodiment (a process of manufacturing a TFT) of the present invention.
FIG. 2 is a process chart illustrating an embodiment of the present invention.
FIG. 3 is a graph illustrating CV characteristics of a gate insulating film according to the present invention.
FIG. 4 is a graph illustrating a withstand voltage characteristic of a gate insulating film according to the present invention.
FIG. 5 is a graph illustrating CV characteristics of a gate insulating film of a reference example.
FIG. 6 is a graph illustrating the absolute IV characteristics of the gate insulating film of the reference example.
FIG. 7 is a graph illustrating CV characteristics of a gate insulating film of a reference example.
FIG. 8 is a graph illustrating CV characteristics of a gate insulating film of a reference example.
FIG. 9 is an explanatory diagram illustrating an example in which the TFT according to the present invention is used in a portable personal computer.
FIG. 10 is an explanatory diagram illustrating an example in which the TFT according to the present invention is used for a mobile phone.
FIG. 11 is an explanatory diagram illustrating an example in which a TFT according to the present invention is used in a digital camera.
FIG. 12 is an explanatory diagram illustrating an example in which the TFT according to the present invention is used in an electronic book.
[Explanation of symbols]
11 Substrate
12 Protective film
13 Semiconductor film
14 Photoresist
15 Gate insulating film
16 Active metal film
17 Gate electrode film
18 interlayer insulating film

Claims (12)

In a method for manufacturing a transistor,
Forming a gate insulating film on the first semiconductor;
A method for manufacturing a transistor, comprising: a step of forming a second semiconductor over the gate insulating film; and a step of performing a heat treatment after the formation of the second semiconductor. The method for manufacturing a transistor according to claim 1,
The method for manufacturing a transistor, wherein the gate insulating film is formed in an atmosphere at a temperature of 350 to 450 degrees Celsius. The method for manufacturing a transistor according to claim 1 or 2,
The method for manufacturing a transistor, wherein the second semiconductor is amorphous. The method for manufacturing a transistor according to claim 1, wherein
A method for manufacturing a transistor, wherein the second semiconductor is deposited by a plasma CVD method. The transistor according to any one of claims 1 to 4,
The method for manufacturing a transistor, wherein the heat treatment is performed in an atmosphere of 300 to 450 degrees Celsius. The method for manufacturing a transistor according to claim 1, wherein
The method for manufacturing a transistor, wherein the heat treatment includes a step of irradiating light energy. The method for manufacturing a transistor according to claim 1, wherein
Patterning the second semiconductor; and implanting an impurity into the first semiconductor,
The method for manufacturing a transistor, wherein the heat treatment is performed after the step of implanting the impurity. The method for manufacturing a transistor according to claim 1, wherein the second semiconductor is used as a gate electrode. The method for manufacturing a transistor according to claim 1, wherein
A method for manufacturing a transistor, further comprising a step of removing the second semiconductor after performing the heat treatment. An integrated circuit including a transistor manufactured by the method according to claim 1. In an electro-optical device including a switching element and an electro-optical layer controlled by the switching element,
The electro-optical device according to claim 1, wherein the switching element includes a transistor manufactured by the method according to any one of claims 1 to 9. In electronic equipment including an electro-optical device as a display unit,
An electronic apparatus comprising the electro-optical device according to claim 11 as the display unit.

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