JP2004013389A - System and method for data transfer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a system and a method for data transfer which can support efficient memory access by enabling many kinds of plan addressing modes to be set. <P>SOLUTION: A linear mode, a 2D mode, and a circular mode are settable as addressing modes. In the linear mode, data as many as an access number specified with a byte count are accessed sequentially from the position specified by a start address. A parameter of a jump is usable to map a block base when data in macro block units are accessed in MPEG image processing. In the 2D mode, access to a two-dimensional block base becomes possible. In the circular mode, data as many as the access number specified by the byte count can cyclically be accessed. The circular mode is used to access data by lines. <P>COPYRIGHT: (C)2004,JPO

Description

となり、アドレス「３４ｈ」からアクセスが開始される。
【００６３】
１バイト進むと

となり、以下、

となり、アドレス「３５ｈ」、「３６ｈ」、「３７ｈ」がアクセスされる。
【００６４】
アドレス「３７ｈ」がアクセスされると、次のワードに移り、

となり、アドレス「３８ｈ」、「３９ｈ」、「３Ａｈ」、「３Ｂｈ」、「３Ｃｈ」、「３Ｄｈ」、「３Ｅｈ」、「３Ｆｈ」がアクセスされる。アドレス「３８ｈ」から「３Ｆｈ」の６４ビットがアクセスされると、次のワードに移る。
【００６５】
次のアドレスでは、

＝２０ｈ＋０＝２０ｈとなり、アドレス「２０ｈ」に戻る。それから、
【００６６】

となり、アドレス「２１ｈ」、「２２ｈ」、「２３ｈ」、「２４ｈ」、「２５ｈ」、「２６ｈ」「２７ｈ」がアクセスされる。アドレス「２０ｈ」から「２７ｈ」の６４ビットがアクセスされると、次のワードに移る。
【００６７】
次からのアドレスでは、

となり、アドレス「２８ｈ」、「２９ｈ」、「２Ａｈ」、「２Ｂｈ」、「２Ｃｈ」、「２Ｄｈ」「２Ｅｈ」、「２Ｆｈ」がアクセスされる。アドレス「２８ｈ」から「２Ｆｈ」の６４ビットがアクセスされると、次のワードに移る。
【００６８】
次からのアドレスでは、

となり、アドレス「３０ｈ」、「３１ｈ」、「３２ｈ」、「３３ｈ」がアクセスされる。
【００６９】
このようにしてアクセスされたデータを読み出すと、図１４に示すように、ヘッダのワードＨ２１と、データのワードＤ２１からＤ２４と、エンドオブパケットのワードＤ２５とからなるパケットとなる。
【００７０】
図１５Ａに示すように、ヘッダには、ヘッダのワードであることを示すフラグ「０１」が付加される。ヘッダには、図２Ａに示したような各種の情報が記述される。
【００７１】
図１５Ｂから図１５Ｅに示すように、ワードＤ１１からＤ１３には、データのワードであることを示すフラグ「１０」が付加される。ワードＤ２１には、アドレス「３４ｈ」から「３７ｈ」の４バイトのデータが配置される。なお、４バイトのデータは６４ビットに満たないので、ここには、スタッフィングバイトが挿入される。ワードＤ２２には、アドレス「３８ｈ」から「３Ｆｈ」の６４ビットのデータが配置される。ワードＤ２３には、アドレス「２０ｈ」から「２７ｈ」の６４ビットのデータが配置される。ワードＤ２４には、アドレス「２８ｈ」から「２Ｆｈ」の６４ビットのデータが配置される。ワードＤ２５には、エンドオブパケットのワードであることを示すフラグ「１１」が付加される。ワードＤ２５には、アドレス「３０ｈ」から「３３ｈ」の４バイトのデータが配置される。なお、４バイトのデータは６４ビットに満たないので、ここには、スタッフィングバイトが挿入される。
【００７２】
このサーキュラモードは、例えば、ライン毎のデータをアクセスするのに用いることができる。例えば、図１６に示すように、１ラインのデータをバイトカウントのデータとすると、そのラインのデータを一度にアクセスすることができる。これは、各ラインのデータをキャッシュレジスタに取り込みようなときに利用できる。
【００７３】
このように、メモリバス１０に転送されるデータは、パケット構造となっている。クライアントデバイス１１、１２、１３からメモリコントローラ１４側に送るパケットの種類は、図１７に示すように、ライトリクエストのパケット（図１７Ａ）と、リードリクエストのパケット（図１７Ｂ）との２つに分けられる。
【００７４】
ライトリクエストのパケットは、図１７Ａに示すように、ヘッダのワードと、数ワードの書き込みデータとからなり、最後に、エンドオブパケットのワードが来る。
【００７５】
リードリクエストのパケットは、図１７Ｂに示すように、リードヘッダの１ワードであり、データワードやエンドオブパケットのワードは存在しない。
【００７６】
リードリクエストかライトリクエストかは、パケットの先頭に付加されたヘッダのワードのＲ／Ｗビットにより識別できる（図２Ａ参照）。
【００７７】
メモリコントローラ１４からクライアントデバイス１１、１２、１３側に送られてくるパケットは、クライアントデバイス１１、１２、１３からのリードリクエストに対応してメモリ１５から読み出されてきたリードデータのパケットである。このリードデータのパケットは、図１８に示すように、ヘッダのワードと、数ワードの書き込みデータとからなり、最後に、エンドオブパケットのワードが来ることになる。
【００７８】
図１９に示すように、各クライアントデバイス１１、１２、１３には、ユニークなデバイスＩＤが割り振られる。例えば、図１９に示すように、クライアントデバイス１１には、デバイスＩＤとして（ＩＤ＝０１ｈ）が割り当てられ、クライアントデバイス１２には、デバイスＩＤとして（ＩＤ＝０２ｈ）が割り当てられ、クライアントデバイス１３には、デバイスＩＤとして（ＩＤ＝０３ｈ）が割り当てられる。
【００７９】
図１９Ａは送信バス１０Ａに転送されるワードを示し、図１９Ｂは受信バス１０Ｂに転送されるワードを示す。図１９Ａに示すように、例えば、クライアントデバイス１１が１６バイトのデータをメモリ１５から読み出す要求をしたとすると、クライアントデバイス１１から送信バス１０Ａを介して、リードリクエストのパケットＰ１が送られる。このリードリクエストのパケットＰ１はヘッダのみであり、このヘッダには、デバイスＩＤ（ＩＤ＝０１ｈ）で、バイトカウント（Ｂｙｔｅ　Ｃｏｕｎｔ＝１６）が記述される。
【００８０】
次に、クライアントデバイス１２が８バイトのデータをメモリ１５から読み出す要求をしたとすると、クライアントデバイス１２から送信バス１０Ａを介して、リードリクエストのパケットＰ２が送られる。このリードリクエストのパケットはヘッダのみであり、このヘッダには、デバイスＩＤ（ＩＤ＝０２ｈ）で、バイトカウント（Ｂｙｔｅ　Ｃｏｕｎｔ＝８）が記述される。
【００８１】
次に、クライアントデバイス１３が２４バイトのデータをメモリ１５に書き込む要求をしたとすると、クライアントデバイス１３から送信バス１０Ａを介して、ライトリクエストのパケットＰ３が送られる。このライトリクエストのパケットＰ３は、ヘッダのワードと、これに続く２バイト分のデータのワードと、１ワードのエンドオブパケットのワードからなる。このヘッダには、デバイスＩＤ（ＩＤ＝０３ｈ）で、バイトカウントが（Ｂｙｔｅ　Ｃｏｕｎｔ＝２４）が記述される。
【００８２】
このように、メモリバス１０の送信バス１０Ａには、クライアントデバイス１１、１２、１３から、リード又はライトのリクエストがパケット構造で次々に送られてくる。このリード又はライトのリクエストの各ワードは、送信バス１０Ａから、ＦＩＦＯメモリ２３に一旦読み込まれる。
【００８３】
ＦＩＦＯメモリ２３に読み込まれたワードは、順に、メモリコントローラ１４に送られる。メモリコントローラ１４で、各リクエストに応じて、メモリ１５がアクセスされる。
【００８４】
すなわち、クライアントデバイス１１からのリードリクエストのパケットＰ１に応答して、メモリ１５から所望のアドレスのデータが１６バイト分読み出される。このリードデータは、ヘッダと、それに続く１ワードのデータワードと、１ワードのエンドオブパケットからなるパケットＰ１１にパケット化される。このリードデータのパケットＰ１１は、図２０Ｂに示すように、メモリコントローラ１４から、受信バス１０Ｂを介して送られる。このリードデータのパケットのヘッダには、デバイスＩＤとして（ＩＤ＝０１）が記述される。クライアントデバイス１１では、デバイスＩＤが（ＩＤ＝０１）であることから、自分宛のリードデータであることがわかり、このリードデータのパケットＰ１１がクライアントデバイス１１で受信される。
【００８５】
クライアントデバイス１２からのリードリクエストのパケットＰ２に応答して、メモリ１５から所望のアドレスのデータが８バイト分読み出される。このリードデータは、ヘッダと、それに続く１ワードのエンドオブパケットからなるパケットＰ１２にパケット化される。このリードデータのパケットＰ１２は、図２０Ｂに示すように、メモリコントローラ１４から、受信バス１０Ｂを介して、送られる。このリードデータのパケットのヘッダには、デバイスＩＤとして（ＩＤ＝０２）が記述される。クライアントデバイス１２では、デバイスＩＤが（ＩＤ＝０２）であることから、自分宛のリードデータであることがわかり、このリードデータのパケットＰ１２がクライアントデバイス１２で受信される。
【００８６】
クライアントデバイス１３からのリードリクエストのパケットＰ３に応答して、メモリ１５の所望のアドレスに、ライトデータとしてクライアントデバイス１３から転送されてきた２４バイト分のデータが書き込まれる。
【００８７】
なお、上述の例では、画像信号処理チップを構成する場合について説明したが、この発明は、複数のクライアントで１つのリソースを共用するようなシステムでは、同様に適用することが可能である。
【００８８】
【発明の効果】
マルチアクセスパターンをサポートすることは、バスとメモリコントローラとの双方を含めて、メモリバス全体の効率を増加させる。また、マルチクライアントシステムでは、アービトレーションの作業が単純化される。なぜなら、クライアントが非隣接データ構成をアクセスするのに必要とされるアービトレーションの巡回の数が著しく削減されるからである。そして、１以上のクライアントが同じコマンドを使う場合に、メモリ中で、シングルインスタンスのクライアントから、同じアドレス計算ロジックのマルチインスタンスに置き換えることにより、チップの全体領域が削減される
【図面の簡単な説明】
【図１】この発明が適用された複数のクライアントデバイスとリソースとからなるシステムの一例のブロック図である。
【図２】バスに転送されるパケットの各ワードの説明に用いる略線図である。
【図３】バスに転送されるパケットのデータの説明に用いる略線図である。
【図４】バスに転送されるパケットのヘッダの説明に用いる略線図である。
【図５】リニアモードのプラス方向ジャンプの説明に用いる略線図である。
【図６】リニアモードのプラス方向ジャンプの説明に用いるタイミング図である。
【図７】リニアモードのプラス方向ジャンプの説明に用いる略線図である。
【図８】リニアモードのマイナス方向ジャンプの説明に用いる略線図である。
【図９】リニアモードのマイナス方向ジャンプの説明に用いるタイミング図である。
【図１０】リニアモードのマイナス方向ジャンプの説明に用いる略線図である。
【図１１】リニアモードのジャンプの説明に用いる略線図である。
【図１２】２Ｄモードの説明に用いる略線図である。
【図１３】サーキュラモードの説明に用いる略線図である。
【図１４】サーキュラモードの説明に用いるタイミング図である。
【図１５】サーキュラモードの説明に用いる略線図である。
【図１６】サーキュラモードの説明に用いる略線図である。
【図１７】送信バスに送られるパケットの説明に用いる略線図である。
【図１８】受信バスに送られるパケットの説明に用いる略線図である。
【図１９】この発明が適用された複数のクライアントデバイスとリソースとからなるシステムの一例の説明に用いるブロック図である。
【図２０】この発明が適用された複数のクライアントデバイスとリソースとからなるシステムの一例の説明に用いるタイミング図である。
【符号の説明】
１０・・・メモリバス、１１、１２、１３・・・クライアントデバイス、１４・・・メモリコントローラ、１５・・・メモリ、１６・・・アービタ[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a data transfer system in which a single memory is shared by a plurality of client devices and a data transfer method of the data transfer system, and more particularly to an improvement in memory access efficiency.
[0002]
[Prior art]
For example, a transport stream of MPEG (Moving Picture Coding Experts Group) 2 used in digital satellite broadcasting or the like is processed, video packets and audio packets are separated from the transport stream, and decoded video data is processed. Image processing chips that perform image processing or superimpose an OSD (On Screen Display) image have been developed. Such an image processing chip performs a graphics engine for performing various types of image processing, a BitBLT (Bit Block Transfer) engine for copying an image of an arbitrary source rectangular area to a destination area, and a still image processing. (Joint Photographic Experts Group) engine for display, a display processor for generating and superimposing an OSD screen, and enlarging and reducing the screen. These processors are connected to a memory controller via a memory bus, and these processors share a memory.
[0003]
When each processor requests a transaction from the memory controller via the memory bus, conventionally, only access from a specified address to a continuous address is supported. That is, the request from each processor to the memory controller is either write or read. The conventional write request protocol is to write data to the memory by the count specified from the start address, and the read protocol is to read data from the memory by the count specified by the start address. It is. In this protocol, continuous addresses are accessed by a specified access count from a start address.
[0004]
[Problems to be solved by the invention]
The use of the bus protocol can be enhanced by extending the concept of the memory bus protocol to include support for a number of different parameterized non-contiguous access patterns.
[0005]
Supporting a variety of access patterns increases the efficiency of the entire memory bus, including both the bus and the memory controller. In a multi-client system, arbitration work is simplified. This is because the number of arbitration rounds required by the client is significantly reduced.
[0006]
Further, for clients accessing non-contiguous data, the complexity of the client design is reduced. This is because data objects can be requested in natural units. On the other hand, in the conventional memory protocol, in the case of non-consecutive data access, the data access is one data word at a time, which is inefficient.
[0007]
When one or more clients use the same command, the entire area of the chip is reduced by replacing a single-instance client with a multi-instance of the same address calculation logic in the memory.
[0008]
SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to solve the above-described problems, and to provide a data transfer system and method that can support an efficient memory access by enabling a plurality of alternative addressing modes to be set. To provide.
[0009]
[Means for Solving the Problems]
The invention comprises a plurality of client devices,
Memory shared by multiple client devices;
Memory control means for controlling the memory;
A bus connecting between the plurality of client devices and the memory control means,
When accessing the memory, the plurality of client devices transmit a request to the resource control unit via the bus,
The request includes an address mode, and is a data transfer system in which a plurality of address modes can be set.
[0010]
The present invention relates to a plurality of client devices, a memory shared by the plurality of client devices, a memory control means for controlling the memory, and a data transfer between a bus connecting the plurality of client devices and the memory control means. The method,
When accessing the memory, the plurality of client devices transmit a request to the resource control unit via the bus,
The request includes an address mode, and is a data transfer method in which a plurality of address modes can be set.
[0011]
In the present invention, a linear mode, a 2D mode, and a circular mode can be set as the addressing mode.
[0012]
In the linear mode, jump (Jump) and byte count (Byte Count) are designated as parameters. The linear mode accesses the data of the access number specified by the byte count (Byte Count) sequentially from the position specified by the start address, and is the most standard addressing mode.
[0013]
The jump (Jump) specifies a word (64 bits) to be jumped by a two's complement numerical value. Jumps occur at word boundaries. For example, if the jump is set to (Jump = 2 words), the address is advanced by jumping 2 words at a word boundary. By specifying a negative value, addressing in the reverse way is also possible. Jump parameters can be used to perform block-based mapping when accessing data in units of macroblocks in MPEG image processing, for example.
[0014]
In the 2D mode, jump (Jump), height (High), column (Col), and row (Row) can be designated as parameters. In the 2D mode, two-dimensional block-based access is enabled, and addresses can be specified two-dimensionally by rows and columns. The 2D mode can be used to set a search block or a reference block when obtaining a motion vector by MPEG.
[0015]
In the circular mode, a byte count (Byte Count) is specified as a parameter. In the circular mode, data of the access number specified by the byte count (Byte Count) is accessed cyclically. That is, in the circular mode, cyclic addressing is performed such that the end address returns to the start address within the range in which the byte count (Byte Count) is specified. The circular mode can be used, for example, to access data for each line.
[0016]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 illustrates an overall configuration of a system to which the present invention is applied.
[0017]
In FIG. 1, client devices 11, 12, and 13 are devices that access a memory 15 that is a shared resource. For example, in a system constituting a signal processing chip, the client devices 11, 12, and 13 are processors such as a BitBLT (Bit Block Transfer) engine and a JPEG (Joint Photographic Experts Group) engine. These client devices 11, 12 and 13 are connected to the memory bus 10 via FIFO (First-In First-Out) memories 21A, 21B and 21C and FIFO memories 22A, 22B and 22C, respectively. Further, a memory controller 14 is connected to the memory bus 10 via FIFO memories 23 and 24. The memory controller 14 controls reading / writing of the memory 15.
[0018]
The memory 15 is a resource that can be commonly used by a plurality of client devices 11, 12, and 13. As the memory 15, for example, an SDRAM (Synchronous Dynamic Random Access Memory) is used. The SDRAM is capable of continuous data transfer synchronized with a clock, and when burst transfer is specified, data transfer of the specified number of data can be performed continuously in units of one clock. Here, the memory 15 configured as an SDRAM can transfer 64-bit data in one clock. The SDRAM may be an SDR (Dingle Data Rate) or a DDR (Double Data Rate). Further, as the memory 15, a DirectRDRAM may be used.
[0019]
The memory bus 10 is a bus for transferring data between the client devices 11, 12, and 13 and the memory controller 14. The memory bus 10 includes a transmission bus 10A for transmitting data from the client devices 11, 12, and 13 to the memory controller 14, and a reception bus 10B for receiving data from the memory controller 14 on the client devices 11, 12, and 13. Consists of
[0020]
Between the client devices 11, 12, 13 and the memory bus 10, FIFO memories 21A, 21B, 21C and FIFO memories 22A, 22B, 22C are provided. These FIFO memories 21A, 21B, 21C and FIFO memories 22A, 22B, 22C are provided as buffers. Since FIFO memories 21A, 21B, 21C and FIFO memories 22A, 22B, 22C are provided between each client device 11, 12, 13 and the memory bus 10, each client device 11, 12, 13 Request transmission and data reception can be performed asynchronously with the transfer clock of the memory bus 10.
[0021]
Further, a FIFO memory 23 and a FIFO memory 24 are provided between the memory controller 14 and the memory bus 10. Since the FIFO memory 23 and the FIFO memory 24 are provided between the memory controller 14 and the memory bus 10, the memory controller 14 receives requests and transmits data asynchronously with the transfer clock of the memory bus 10. Can be performed.
[0022]
A unique device ID is allocated to each of the client devices 11, 12, and 13. When accessing the memory 15, each of the client devices 11, 12, and 13 transmits a request via the transmission bus 10A of the memory bus 10. This request has a packet structure.
[0023]
All the client devices 11, 12, and 13 can access the common memory 15. Therefore, a request to the memory 15 may occur simultaneously in a plurality of client devices 11, 12, and 13. Therefore, an arbiter 16 is provided to prevent contention of requests from the client devices 11, 12, and 13.
[0024]
When the client devices 11, 12, and 13 access the memory 15, first, a request for obtaining the right to use the bus is sent to the arbiter 16. When there are requests from a plurality of client devices, the arbiter 16 arbitrates the requests and returns a grant to only one client device that is permitted to use the memory bus 10. Of the plurality of client devices 11, 12, and 13, only the client device for which the grant has been returned can access the memory 15.
[0025]
In the case of a memory write request, a write request is transmitted from the client devices 11, 12, and 13. This write request is sent to the memory controller 14 via the transmission bus 10A. The write data sent from the client devices 11, 12, and 13 is written to a desired address in the memory 15 by the memory controller 14 in response to the write request.
[0026]
In the case of a memory read request, a read request is transmitted from the client devices 11, 12, and 13. This read request is sent to the memory controller 14 via the transmission bus 10A. The memory controller 14 reads data from a desired address of the memory 15 in response to a read request. The read data is transferred from the memory controller 14 via the reception bus 10B, and is received by the client devices 11, 12, and 13 that have transmitted the read request.
[0027]
FIG. 2 shows a configuration of a packet transferred to the memory bus 10. As shown in FIG. 2, the data transferred to the memory bus 10 has a packet configuration including a header word, a data word, and an end-of-packet word. These header, data, and end-of-packet words are 72 bits obtained by adding control signals such as flags to 64-bit data.
[0028]
2A, 2B, and 2C show the header, data, and bit assignment of each word of the end-of-packet, respectively.
[0029]
As shown in FIGS. 2A to 2C, a 2-bit flag is provided at the head of each word. The flag identifies whether the word is a header, data, or end-of-packet. For example, if this flag is “01”, it is a header, if “10”, it is data, and if it is “11”, it is an end-of-packet.
[0030]
In the word of the header in FIG. 2A, the next 6 bits after the 2 bits of the flag can be defined on the client side.
[0031]
The next 6 bits are a device ID. A unique device number is assigned to each client device, and the device ID indicates the ID of the target client device.
[0032]
The next 6 bits are a mode. The mode indicates the address mode together with the addressing format. As the address mode, a linear mode, a 2D (two-dimensional) mode, a circular mode, and the like are prepared.
[0033]
The next one bit of the mode indicates read or write. If this bit is "1", for example, it is a write, and if it is "0", it is a read.
[0034]
The next two bits of the addressing format are reserved for future extensions.
[0035]
The next 30 bits are a start address. The start address is a start address of a memory to be read or written, and this address is set in byte units.
[0036]
As shown in FIGS. 2B and 2C, in the data word and the end of packet word, an 8-bit byte enable is arranged after a 2-bit flag, and then 64-bit data is arranged. The byte enable indicates whether the corresponding data is valid or invalid.
[0037]
That is, the transfer data of one word may be less than 64 bits. If the transfer data of one word is less than 64 bits, a stuffing byte is inserted as shown in FIG. 3 so that the data of one word becomes 64 bits.
[0038]
FIG. 3A shows a case where lower 3 bytes of 64 bits (8 bytes) are data and upper 5 bytes are stuffing bytes. In this case, as shown in FIG. 3A, out of the eight bits of the byte enable, the lower three bits become “1” indicating that the data is valid, and the upper five bits are “0” indicating that the data is invalid. It becomes.
[0039]
FIG. 3B shows a case where the upper 2 bytes of the 64 bits (8 bytes) are data and the lower 6 bytes are stuffing bytes. In this case, as shown in FIG. 3B, of the eight bits of the byte enable, the upper two bits become “1” indicating that the data is valid, and the lower six bits are “0” indicating that the data is invalid. It becomes.
[0040]
As shown in FIG. 4A, a mode and an addressing format are provided in the header word (FIG. 2A), and the mode and the addressing format indicate an address mode. As the address mode, a linear mode, a 2D mode, a circular mode, and the like are prepared.
[0041]
4B to 4D show each address mode. In the linear mode, as shown in FIG. 4B, four bits of the mode are “0000”.
[0042]
In the linear mode, jump (Jump) and byte count (Byte Count) are designated as parameters. The linear mode accesses the data of the access number specified by the byte count (Byte Count) sequentially from the position specified by the start address, and is the most standard addressing mode.
[0043]
The jump (Jump) specifies a word (64 bits) to be jumped by a two's complement numerical value. Jumps occur at word boundaries. For example, if the jump is set to (Jump = 2 words), the address is advanced by jumping 2 words at a word boundary. By specifying a negative value, addressing in the reverse way is also possible. The byte count (Byte Count) sets the required number of bytes.
[0044]
In the 2D mode, as shown in FIG. 4C, four bits of the mode become “0001”. In the 2D mode, jump (Jump), height (Height), column (Col), and row (Row) can be designated as parameters. In the 2D mode, two-dimensional block-based access is enabled, and addresses can be specified two-dimensionally by rows and columns.
[0045]
In the circular mode, as shown in FIG. 4D, four bits of the mode are “0010”. In the circular mode, a byte count (Byte Count) is specified as a parameter. In the circular mode, data of an access number specified by a byte count (Byte Count) is cyclically accessed. That is, in the circular mode, cyclic addressing is performed such that the end address returns to the start address within the range in which the byte count (Byte Count) is specified.
[0046]
FIG. 5 shows a linear mode in which the start address is “05h (h is a hexadecimal number)” (Start Address = 5h), the jump is “2 words” (Jump = 2word), and the byte count is “31” (Byte Count = 1Fh). ) Indicates access when specified. This indicates an access that accesses 31 bytes from the address “5h” on the memory and jumps by two words at the boundary between words.
[0047]
As shown in FIG. 5, first, 3-byte data of "05h" to "07h" are sequentially accessed. Two words are jumped from "07h" which is a boundary between words, one word from "10h" to "17h" is accessed, two words are jumped at a word boundary, and one word from "20h" to "27h" is jumped. A word is accessed, a two-word jump is performed at a word boundary, one word from "30h" to "37h" is accessed, a two-word jump is performed at a word boundary, and 4-byte data from "40h" to "43h" is stored. Is accessed. As a result, 31 bytes of data are accessed sequentially from the address “05h”.
[0048]
When the data accessed in this manner is read, as shown in FIG. 6, a packet is formed of the word H1 of the header, the words D1 to D4 of the data, and the word D5 of the end-of-packet.
[0049]
As shown in FIG. 7A, a flag “01” indicating that the word is a header is added to the word H1 of the header. Various kinds of information as shown in FIG. 2A are described in the header.
[0050]
As shown in FIGS. 7B to 7E, a flag “10” indicating data is added to the words D1 to D4. In the word D1, 3-byte data of addresses “05h” to “07h” are arranged. Note that since the 3-byte data is less than 64 bits, a stuffing byte is inserted here. In word D2, 64-bit data of addresses "10h" to "17h" are arranged. In word D3, 64-bit data of addresses "20h" to "27h" are arranged. In word D4, 64-bit data of addresses "30h" to "37h" are arranged. A flag “11” indicating the end of packet is added to the word D5. In the word D5, 4-byte data of addresses "40h" to "47h" are arranged. Since 4-byte data is less than 64 bits, a stuffing byte is inserted here.
[0051]
FIG. 8 shows a linear mode in which the start address is designated as "52h" (Start Address = 52h), the jump is designated as "-3 words" (Jump = -3word), and the byte count is designated as "27" (Byte Count = 1Bh). This indicates the access when it is performed. This indicates an access that accesses 27 bytes from the address “52h” on the memory and jumps in the minus direction by 3 words at the boundary between words.
[0052]
As shown in FIG. 8, first, 6-byte data of "52h" to "57h" are sequentially accessed. At the boundary between words, the word is jumped three words in the minus direction, one word from "38h" to "3Fh" is accessed, and at the word boundary, three words are jumped in the minus direction, and one word from "20h" to "27h" is accessed. A word is accessed and jumped by three words in the minus direction at the word boundary, and 5-byte data from "08h" to "0Ch" is accessed. As a result, 27 bytes of data are accessed sequentially from the address “52h”.
[0053]
When the data accessed in this manner is read, as shown in FIG. 9, a packet is formed of the word H11 of the header, the words D11 to D13 of the data, and the word D14 of the end of packet.
[0054]
As shown in FIG. 10A, a flag “01” indicating a header word is added to the word H11 of the header. Various kinds of information as shown in FIG. 2A are described in the flag.
[0055]
As shown in FIGS. 10B to 10D, a flag “10” indicating that the word is a data word is added to words D11 to D13. In word D11, 6-byte data of addresses "82h" to "87h" are arranged. Since 6-byte data is less than 64 bits, a stuffing byte is inserted here. In word D12, 64-bit data of addresses "38h" to "3Fh" are arranged. In the word D13, 64-bit data of addresses “20h” to “27h” are arranged. A flag “11” indicating that the word is an end-of-packet word is added to the word D14. In the word D14, 4-byte data of addresses "08h" to "0Ch" are arranged. Since 4-byte data is less than 64 bits, a stuffing byte is inserted here.
[0056]
As described above, in the linear mode, the addresses are sequentially accessed from the start address by the number of accesses indicated by the byte count (Byte Count). In this example, the parameter of the jump can be set in the positive and negative directions. Jump parameters can be used to perform block-based mapping when accessing data in units of macroblocks in MPEG image processing, for example.
[0057]
That is, as shown in FIG. 11, the height of the macroblock (MB) is “16”. When a value of "16" is set in the jump (Jump), the image is jumped by an (8 × 16) byte address at a word boundary, and as a result, a continuous image in the line direction can be accessed.
[0058]
FIG. 12 shows access in the 2D mode. The 2D mode is an address mode for performing block-based mapping memory access. In the 2D mode, as shown in FIG. 12, access is performed by the number of bytes represented by (Row × Col). The 2D mode can be used to set a search block or a reference block when obtaining a motion vector by MPEG.
[0059]
FIG. 13 shows access in the circular mode. In the circular mode, data of a data amount specified by a byte count (Byte Count) is cyclically accessed from a position specified by a start address (Start Address).
[0060]
That is, in the circular mode, the range specified by the byte count (Byte Count) is accessed in the order represented by the following expression.
for (i = 0; i <ByteCount; i ++)
Address_i = trunc (StartAddress, ByteCount) + mod (StartAddress + i, ByteCount) trunc (A, B): multiple of B closest to A
mod (A, B): remainder when A is divided by B
i is in bytes
[0061]
In other words, starting from the position of the multiple of the byte count closest to the start address, the access is performed sequentially from the start address while rotating by the byte count remainder calculation by the byte count access count. Therefore, the end address returns to the start address.
[0062]
For example, as shown in FIG. 13, if the byte count is “32” bytes (Byte Count = 20h) and the start address is “34h”,
Byte Count = 20h
Start Address = 34h
In the start address (Start Address),

And the access is started from the address “34h”.
[0063]
One byte forward

And below,

And the addresses “35h”, “36h”, and “37h” are accessed.
[0064]
When the address “37h” is accessed, the processing moves to the next word,

And the addresses “38h”, “39h”, “3Ah”, “3Bh”, “3Ch”, “3Dh”, “3Eh”, and “3Fh” are accessed. When 64 bits of “3Fh” are accessed from the address “38h”, the process moves to the next word.
[0065]
At the following address:

= 20h + 0 = 20h, and returns to the address “20h”. then,
[0066]

And the addresses “21h”, “22h”, “23h”, “24h”, “25h”, “26h” and “27h” are accessed. When the 64 bits of the addresses “20h” to “27h” are accessed, the process moves to the next word.
[0067]
In the following address,

And the addresses “28h”, “29h”, “2Ah”, “2Bh”, “2Ch”, “2Dh”, “2Eh”, and “2Fh” are accessed. When 64 bits of “2Fh” are accessed from the address “28h”, the process moves to the next word.
[0068]
In the following address,

And the addresses “30h”, “31h”, “32h”, and “33h” are accessed.
[0069]
When the data accessed in this manner is read, as shown in FIG. 14, it becomes a packet including the word H21 of the header, the words D21 to D24 of the data, and the word D25 of the end of packet.
[0070]
As shown in FIG. 15A, a flag “01” indicating the word of the header is added to the header. Various kinds of information as shown in FIG. 2A are described in the header.
[0071]
As shown in FIGS. 15B to 15E, a flag “10” indicating that the word is a data word is added to the words D11 to D13. In the word D21, 4-byte data of addresses "34h" to "37h" are arranged. Since 4-byte data is less than 64 bits, a stuffing byte is inserted here. In word D22, 64-bit data of addresses "38h" to "3Fh" are arranged. In word D23, 64-bit data of addresses "20h" to "27h" are arranged. In the word D24, 64-bit data of addresses “28h” to “2Fh” are arranged. A flag “11” indicating that the word is an end-of-packet word is added to the word D25. In the word D25, 4-byte data of addresses "30h" to "33h" are arranged. Since 4-byte data is less than 64 bits, a stuffing byte is inserted here.
[0072]
This circular mode can be used, for example, to access data for each line. For example, as shown in FIG. 16, when one line of data is byte count data, the data of that line can be accessed at a time. This can be used when data of each line is taken into a cache register.
[0073]
Thus, the data transferred to the memory bus 10 has a packet structure. As shown in FIG. 17, the types of packets sent from the client devices 11, 12, and 13 to the memory controller 14 are divided into two types: a write request packet (FIG. 17A) and a read request packet (FIG. 17B). Can be
[0074]
As shown in FIG. 17A, the write request packet includes a header word and several words of write data. Finally, an end-of-packet word comes.
[0075]
As shown in FIG. 17B, the read request packet is one word of the read header, and there is no data word or end-of-packet word.
[0076]
Whether the request is a read request or a write request can be identified by the R / W bit of the word of the header added to the head of the packet (see FIG. 2A).
[0077]
Packets sent from the memory controller 14 to the client devices 11, 12, 13 are read data packets read from the memory 15 in response to read requests from the client devices 11, 12, 13. As shown in FIG. 18, the read data packet includes a header word and several words of write data, and finally an end-of-packet word comes.
[0078]
As shown in FIG. 19, a unique device ID is assigned to each of the client devices 11, 12, and 13. For example, as shown in FIG. 19, the client device 11 is assigned (ID = 01h) as a device ID, the client device 12 is assigned (ID = 02h) as a device ID, and the client device 13 is assigned. , And (ID = 03h) are assigned as device IDs.
[0079]
FIG. 19A shows words transferred to the transmission bus 10A, and FIG. 19B shows words transferred to the reception bus 10B. As shown in FIG. 19A, for example, if the client device 11 requests to read 16-byte data from the memory 15, a read request packet P1 is transmitted from the client device 11 via the transmission bus 10A. This read request packet P1 has only a header, and in this header, a device ID (ID = 01h) and a byte count (Byte Count = 16) are described.
[0080]
Next, assuming that the client device 12 has made a request to read 8-byte data from the memory 15, a read request packet P2 is sent from the client device 12 via the transmission bus 10A. This read request packet has only a header, and the header describes a device ID (ID = 02h) and a byte count (Byte Count = 8).
[0081]
Next, assuming that the client device 13 makes a request to write 24-byte data to the memory 15, a write request packet P3 is sent from the client device 13 via the transmission bus 10A. The write request packet P3 includes a header word, a 2-byte data word following the header word, and a 1-word end-of-packet word. In this header, a device ID (ID = 03h) and a byte count (Byte Count = 24) are described.
[0082]
As described above, read or write requests are sequentially transmitted from the client devices 11, 12, and 13 in a packet structure to the transmission bus 10A of the memory bus 10. Each word of the read or write request is once read into the FIFO memory 23 from the transmission bus 10A.
[0083]
The words read into the FIFO memory 23 are sent to the memory controller 14 in order. The memory controller 14 accesses the memory 15 in response to each request.
[0084]
That is, in response to the packet P1 of the read request from the client device 11, 16 bytes of data at the desired address are read from the memory 15. This read data is packetized into a packet P11 including a header, a data word of one word following the header, and an end of packet of one word. The packet P11 of the read data is sent from the memory controller 14 via the reception bus 10B as shown in FIG. 20B. In the header of the packet of the read data, (ID = 01) is described as a device ID. Since the device ID is (ID = 01), the client device 11 knows that the read data is addressed to itself, and the client device 11 receives the packet P11 of the read data.
[0085]
In response to a read request packet P2 from the client device 12, data of a desired address is read from the memory 15 for 8 bytes. This read data is packetized into a packet P12 consisting of a header and a one-word end-of-packet following the header. The packet P12 of the read data is sent from the memory controller 14 via the reception bus 10B as shown in FIG. 20B. In the header of the packet of the read data, (ID = 02) is described as a device ID. Since the device ID is (ID = 02) in the client device 12, it is known that the read data is addressed to itself, and the packet P12 of this read data is received by the client device 12.
[0086]
In response to the read request packet P3 from the client device 13, the 24-byte data transferred from the client device 13 as write data is written to a desired address in the memory 15.
[0087]
In the above example, the case where the image signal processing chip is configured has been described. However, the present invention can be similarly applied to a system in which a plurality of clients share one resource.
[0088]
【The invention's effect】
Supporting multiple access patterns increases the efficiency of the entire memory bus, including both the bus and the memory controller. In a multi-client system, arbitration work is simplified. This is because the number of arbitration cycles required for a client to access a non-contiguous data structure is significantly reduced. When one or more clients use the same command, the entire area of the chip is reduced by replacing a single-instance client with a multi-instance of the same address calculation logic in the memory.
[Brief description of the drawings]
FIG. 1 is a block diagram of an example of a system including a plurality of client devices and resources to which the present invention is applied.
FIG. 2 is a schematic diagram used to explain each word of a packet transferred to a bus.
FIG. 3 is a schematic diagram used for describing data of a packet transferred to a bus.
FIG. 4 is a schematic diagram used for describing a header of a packet transferred to a bus.
FIG. 5 is a schematic diagram used for describing a positive-direction jump in a linear mode.
FIG. 6 is a timing chart used for describing a positive-direction jump in the linear mode.
FIG. 7 is a schematic diagram used for describing a positive-direction jump in a linear mode.
FIG. 8 is a schematic diagram used for describing a minus jump in the linear mode.
FIG. 9 is a timing chart used to explain a minus jump in the linear mode.
FIG. 10 is a schematic diagram used for explaining a minus jump in the linear mode.
FIG. 11 is a schematic diagram used to explain a jump in a linear mode.
FIG. 12 is a schematic diagram used for describing a 2D mode.
FIG. 13 is a schematic diagram used for describing a circular mode.
FIG. 14 is a timing chart used for explaining a circular mode.
FIG. 15 is a schematic diagram used for describing a circular mode.
FIG. 16 is a schematic diagram used for describing a circular mode.
FIG. 17 is a schematic diagram used for describing a packet sent to a transmission bus.
FIG. 18 is a schematic diagram used for describing a packet sent to a reception bus.
FIG. 19 is a block diagram used to describe an example of a system including a plurality of client devices and resources to which the present invention has been applied.
FIG. 20 is a timing chart used for describing an example of a system including a plurality of client devices and resources to which the present invention is applied.
[Explanation of symbols]
10: memory bus, 11, 12, 13 ... client device, 14: memory controller, 15: memory, 16: arbiter

Claims (18)

Multiple client devices,
A memory shared by the plurality of client devices;
Memory control means for controlling the memory,
A bus connecting the plurality of client devices and the memory control means,
The plurality of client devices, when accessing the memory, transmit a request to the resource control unit via the bus,
A data transfer system in which an address mode is included in the request and a plurality of address modes can be set. 2. The data transfer system according to claim 1, wherein the memory is read / written in units of words having a predetermined data length. 3. The data transfer system according to claim 2, wherein the memory is an SDR or DDR SDRAM. 2. The data transfer system according to claim 1, wherein the request is packetized, and a word of a header of the packet includes the start address, the addressing mode, and a parameter. 2. The method according to claim 1, wherein the address mode is a linear mode, and in the linear mode, a start address and a parameter of an access count are designated, and the addresses are sequentially accessed from the start address until the access count is reached. Data transfer system as described. 6. The data transfer system according to claim 5, wherein in the linear mode, a jump parameter is further specified, and the data is jumped and accessed at an address specified by the jump at a word boundary. 7. The data transfer system according to claim 6, wherein the jump parameters can be set in positive and negative directions. 2. The address mode is a two-dimensional mode. In the two-dimensional mode, a start address, a parameter in a row direction, and a parameter in a column direction are designated, and a two-dimensional address is accessed. Data transfer system as described. 9. The data transfer system according to claim 8, wherein in the two-dimensional mode, a jump parameter is further specified, and the data is jumped and accessed by an address specified by the jump at a word boundary. The above-mentioned address mode is a circular mode. In the above-mentioned circular mode, a start address and an access count parameter are specified, and the address is circulated so that the end address returns to the start address from the start address until the access count is reached. 2. The data transfer system according to claim 1, wherein the data transfer system is accessed dynamically. A plurality of client devices; a memory shared by the plurality of client devices; a memory control means for controlling the memory; and a data transfer between a bus connecting the plurality of client devices and the memory control means. The method,
The plurality of client devices, when accessing the memory, transmit a request to the resource control unit via the bus,
A data transfer method in which the request includes an address mode, and a plurality of address modes can be set. 12. The data transfer method according to claim 11, wherein the request is packetized, and a word of a header of the packet includes the start address, the addressing mode, and a parameter. The address mode is a linear mode, and in the linear mode, a start address and an access count parameter are designated, and addresses are sequentially accessed from the start address until the access count is reached. Data transfer method described. 14. The data transfer method according to claim 13, wherein in the linear mode, a jump parameter is further specified, and a jump is performed at a word boundary by an address specified by the jump. 15. The data transfer method according to claim 14, wherein the jump parameters can be set in positive and negative directions. The address mode is a two-dimensional mode, and in the two-dimensional mode, a start address, a parameter in a row direction, and a parameter in a column direction are designated, and a two-dimensional address is accessed. Data transfer method described. 17. The data transfer method according to claim 16, wherein in the two-dimensional mode, a jump parameter is further specified, and the data is jumped and accessed by an address specified by the jump at a word boundary. The above-mentioned address mode is a circular mode. In the above-mentioned circular mode, a start address and an access count parameter are specified, and the address is circulated so that the end address returns to the start address from the start address until the access count is reached. The data transfer method according to claim 11, wherein the data transfer is performed in a dynamic manner.

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