JP2000339220A - Cache block reserving method and computer system with cache block reserving function - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make cache storage possible to be used by real time application. SOLUTION: Main storage is divided into physical pages, a set of indexes to be obtained from all addresses to be included in the physical page by a hash device is defined as color and the physical pages to be included in the main storage are classified by color IDs. In the case of execution of the real time application, when an allocation request to a storage area to be permanently arranged, namely, in which no paging is generated is performed by defining a virtual address, the size and a thread ID of the storage area as a subtracting number, the thread ID and the color ID are managed so that the physical page with specified color ID is allocated from a set of the physical pages managed for real time thread and the remaining physical page with color IDs are not allocated to other threads.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a computer system comprising an arithmetic unit, an address translator, and a storage unit, wherein the storage unit is a high-speed storage unit between the main storage unit and the arithmetic unit and the main storage unit. A method for reserving one or more cache blocks for exclusive use in executing a real-time application when the computer system executes a real-time application, and an apparatus for implementing the method. .

[0002]

2. Description of the Related Art Real-time applications such as multimedia mail, electronic conferencing, remote control, and virtual reality are known. Real-time applications are required to process constantly changing signals, such as moving images and sounds, quickly, not late and under strict time requirements. If processing cannot be performed correctly at regular time intervals and the processing is delayed or performed too early, the image or sound is disturbed. For example, in order to process a television image by a computer system, it is necessary to perform image processing for one screen 30 times per second. For this purpose, the image processing for one screen needs to be 1/30 second or less, and the image processing for one screen needs to be started strictly at 1/30 second intervals. If the image processing time for one screen varies, the image processing for one screen needs to be 1/30 second or less even in the worst case where the longest processing time is required. As described above, in order to execute a real-time application on a computer system, it is necessary to guarantee an accurate prediction of the processing time, and when the processing time varies, an accurate prediction of the longest processing time is guaranteed. Need to be done.

One of the requirements for guaranteeing an accurate prediction of the processing time is that the time at which the arithmetic unit accesses data can be predicted. If the computer system has a main memory and a cache memory, the access time is the time to access the data in the cache memory when the cache memory hits, and the shortest, and when the cache memory misses, This is the time for transferring the entire cache block including the data in the main memory to the cache memory. When the main memory has a burst mode transfer function, the time becomes the same as the time when the cache memory is not provided. When I made a mistake,
And when it is necessary to replace the cache block,
When it is necessary to write the cache block back to the main memory, the sum of the time for writing the cache block back to the main memory and the time for transferring the entire cache block including the data in the main memory to the cache memory is obtained. ,
This is about twice as long as when there is no cache memory. Thus, the access time is greatly affected by whether or not the cache storage hits. Whether or not the cache storage hits is greatly affected by whether or not other threads use the cache storage at the same time.
Unless it is guaranteed that a real-time application will exclusively use some or all of the cache storage, access times will vary non-deterministically. In this case, the prediction of the access time is the sum of the longest access time, that is, the time to write back the cache block to the main memory and the time to transfer the entire cache block including the data in the main memory to the cache memory. For this reason, the conventional storage management method disables cache storage when executing a real-time application so that the access time to data is the time to access the data in main storage. Thus, the access time is decisive and the predictability of the access time is guaranteed.

[0004]

When a real-time application is executed by such a storage management method, access to data is always access to main storage, so that most of execution cycles of the arithmetic unit wait for data. In order to execute a real-time application requiring a high-speed operation, a high-speed main memory is required. However, high-speed accessibility of the main memory is not always compatible with other conditions required for the main memory, for example, a condition that the main memory must have a certain storage capacity. Therefore, even in a computer system having an arithmetic unit having a high operating frequency and having a main memory and a cache memory, conventionally, high-speed execution of a real-time application has not been performed.

An object of the present invention has been made in view of the above-mentioned drawbacks of the conventional storage management method, and makes it possible for a real-time application to use cache storage so that a cache block used by the real-time application can be used. Ensure that access times do not vary non-deterministically when running real-time applications by ensuring that they are not modified by the execution of other real-time applications, operating systems, or non-real-time applications Provided is a cache block reservation method and device capable of performing higher-speed processing of a real-time application by guaranteeing an access time shorter than an access time to a main memory. In the door.

[0006]

A cache block reserving method according to the present invention includes an arithmetic unit, an address translating unit, and a storage unit, and the storage unit includes a main storage unit, an arithmetic unit, and a main storage unit. Has a high-speed cache storage device in between,
The cache storage device is composed of a hash device and a set of cache blocks. The cache storage device specifies the position of the cache block by an index, and the cache storage device uses a part of the physical address of the data requested by the arithmetic device to perform the hashing. A physical address cache storage device that generates an index by a device, wherein the cache storage device uses a modulo hashing algorithm as an algorithm used by the hash device; and the cache storage device stores the index number generated by the hash device as a cache. Implemented by a computer system that is an N-way set associative cache storage, where N is an integer less than the number of blocks. In the following description, the above computer system is referred to as a "computer system for implementing the present invention."
It is written.

In order to achieve the above object, a cache block reserving method according to the present invention divides a main memory of a main memory into physical pages, and obtains the data from all addresses included in the physical pages by a hash device. A set of indices is defined as a color, physical pages included in main memory are classified by color ID, and one or more color IDs are selected from a set of color IDs that are currently unused when executing a real-time application. The thread ID and the color ID are set so that the physical page having the selected color ID can be exclusively used by the thread executing the real-time application.
And manage.

[0008] A computer system with a cache block reservation function according to the present invention is a computer system for implementing the present invention, characterized by having physical page management means. The physical page management means classifies the physical pages in the main memory by a color ID, and selects one or a plurality of color IDs from a set of currently unused color IDs at the time of execution of the real-time application, and selects the selected color ID. It has a function of managing the thread ID and the color ID so that the thread executing the real-time application can exclusively use the physical page having the given color ID.

The physical page management means has a physical page management unit, a paging management unit, and a kernel storage management unit. When the computer system is started, the physical page management unit divides an unused area of the main storage into physical pages and assigns a color ID when the address translation device is not operating at the time. The physical pages having some color IDs are used for the real-time thread and the operating system, the physical pages are managed using the color ID, the thread ID, and the physical page number, and the physical pages having the other color IDs are not used. Manage for real-time threads.

The kernel storage management unit acquires a physical page by specifying a thread ID so as not to access the same cache block as another application (so that access to the cache block does not conflict). The kernel storage management unit also has a function of allocating a storage area for a data structure created inside the operating system, such as a network buffer, a thread structure, and a file structure, by the operating system.

[0011] When the real-time application accesses the cache block, the paging management unit specifies a thread ID to acquire a physical page so as not to collide with the operating system or another application, and then uses an address translation device. It has a function of constructing a page table for converting a virtual page number into a physical page number. Further, the paging management unit has a function of constructing a page table so that when a non-real-time application acquires a physical page, access of the cache block by the non-real-time application does not conflict with access by the operating system or the real-time application. Have. At this time, the possibility that the access of the non-real-time application to the cache block collides with another non-real-time application is not excluded.

[0012] The physical page manager resides in main memory to ensure that access to data is to main storage or cache storage during execution of the real-time application, ie, no paging occurs. When a storage area allocation request is made using the virtual address, size, and thread ID of the storage area as arguments, it is called without an argument to allocate an arbitrary physical page as in the conventional physical page management method. Instead of allocating a physical page with a specific color ID from a set of physical pages managed for real-time threads, reserve the remaining physical pages with the color ID so that they cannot be allocated to other threads I do.

As described above, the main memory is stored for each physical page.
Classifying using color IDs, the real-time application classifies a set of physical pages having a specific color ID into
Thread ID and color ID for exclusive use
And that the access to the cache storage of the real-time application does not conflict with other threads without changing the application.

In the present invention, since the main memory is classified for each physical page using the color ID, the hash device of the cache storage device must be able to classify the main memory in page units. In the modulo hashing algorithm, successive physical pages of main storage are mapped to successive locations of cache storage. For example, FIG.
Shows how a physical page is mapped onto cache storage when it has a 1-way set associative cache storage with a capacity of 16K bytes and the page size is 4K bytes.

As can be seen from FIG. 1, every fifth physical page wraps around to the beginning of cache storage. All physical pages with the same pattern are mapped to portions of cache storage with the same pattern. In the present invention, each pattern is defined as a color, and a physical page and a color ID are defined.
Is defined by the following equation (claim 2).

When the capacity of the N-way set associative cache storage device is CAB bytes and the page size is PGB bytes, the number of colors COT of the main memory is as follows: COT = CAB / (PGB * N) (1) In the present invention, the relationship between the physical page having the physical page number PFN and the color ID COI is defined by the following equation: COI = PFN mod COT (2)

[0017]

By using the above physical page management method, when a real-time application requests the operating system to allocate a physical page and issues a storage allocation request, a certain color ID is assigned to the real-time application. , And assigns the same color I as the physical page.
Physical pages with a D are guaranteed not to be allocated to other real-time applications, operating systems, or non-real-time applications, resulting in one or more cache blocks being reserved for that real-time application. Is done.

As described above, the real-time application makes a reservation for exclusive use of one or a plurality of cache blocks, and executes by using only the reserved cache blocks. To ensure that access does not conflict with access to the cache block by other threads, avoid non-deterministic access time, and achieve predictable access time in less time than main memory access time This makes it possible to calculate the processing time required for a real-time application in a predictable manner at a higher speed.

[0019]

FIG. 2 is a block diagram showing an example of the configuration of a computer system used to implement a cache block reservation method according to the present invention. The computer system according to the present embodiment includes an arithmetic unit 21, an address translator 22, a main memory 23, and a cache memory 2.
4, an auxiliary storage 25, a paging management unit 26, and a physical page management unit 27. Further, the computer system has, as a logical function, a virtual memory based on a multiple virtual address space that makes it appear as if a plurality of applications have a unique storage area that is vast and linearly spread. It has multiple programming as a logical function to operate multiple applications simultaneously.

In the virtual storage, the application is divided into pages of the same size, and the main storage 23 is divided into physical pages. The application page is stored in the auxiliary storage 25.
When the application is not executed, it is stored only in the auxiliary storage 25. However, at the time of execution, the physical page of the main storage 23 can be occupied further.

The paging management unit 27 manages a page table for each virtual address space, and the page table holds information indicating where each page of the application is located. That is, it holds the physical page number of the application or the I / O address on the auxiliary storage 25. When a running application accesses specific data in the virtual address space, if the data is also present in a physical page, the access proceeds normally. If not, a page fault interrupt occurs, and the paging management unit 26 adjusts the main memory 23 so that the failed access succeeds by retry (described later).

The address translator 22 is the most important hardware in virtual storage. When one byte of data is accessed at the time of executing an application, the address translator 22 translates the virtual address of the data generated by the arithmetic unit 21. Upon receiving the data, it outputs a physical address designating 1-byte data in the physical page of the main memory 23 corresponding to the received data. This conversion is performed by sending the virtual page number to the paging management unit 26, and the paging management unit obtains the physical page number from the page table of the application. The paging management unit 26 manages the page table on the main memory. Address translation is very slow. Therefore, for the purpose of suppressing the time required for the conversion to an allowable level, the address conversion device 22 is provided with a special associative register, a part of the page table is held thereon, and the conversion operation is performed by another operation device. Generally, the operation can be performed overlapping with the operation. When the requested page is not present in the physical page, the address translator generates a page fault interrupt.

The physical page management unit 27 manages physical pages that are not currently used by the operating system or the application among the physical pages in the main memory.

The page fault interruption is processed by the paging management unit 26. For example, if the running application accesses a page that is in the auxiliary storage 25 but does not occupy the physical page, the paging management unit 26 first sends the physical page management unit 27 Request page allocation. The physical page management unit returns the physical page number of one of the physical pages in the main memory that is not currently used by the operating system or the application. Next, the paging management unit 26 reads, from the entry for managing the corresponding page in the page table for managing the virtual address space of the application, the auxiliary storage 2 for the page.
5. Get the I / O address in 5. Paging management unit 26
Finally, the page in the auxiliary storage 25 is transferred to the physical page by designating the physical page number and the I / O address,
After replacing the I / O address in the page table with the physical page number, the execution of the application is resumed.

The computer system according to the present embodiment includes:
There is a main memory 23 and a high-speed cache memory 24 between the arithmetic unit 21 and the main memory 23. The cache store 24 is designed so that the application is completely or almost unaware that it exists.
Therefore, the application itself only keeps accessing the main memory by the address.
4 is automatically accessed by the hardware controlling it. When the arithmetic unit 21 generates an address of the main memory to be accessed, the address is sent to the cache memory 24, and the hardware executes the cache memory 2
4 to search for data corresponding to the address. If the data exists in the cache memory 24, the data is transferred to the arithmetic unit 21 as if it were read from the main memory 23. If the data does not exist in cache store 24, the address is
And reaches the main memory 23, where the addressed location is accessed. In this case, the data is transferred to the cache storage 24 and the arithmetic unit 21. To take advantage of spatial locality, the entire block containing the data that the arithmetic unit 21 is trying to access is transferred to the cache storage 24.

The purpose of the cache memory 24 is to
First, data is transferred faster than the main memory 23. Therefore, if the address of the data requested by the arithmetic unit 21 is given, the search of the cache memory 24 for the data must be performed at a high speed. Also, the search technique must be simple so that high speed hardware implementations are practical and economical. For this reason, the cache memory 24 is generally searched using a simplified hash table technique. In the cache memory 24 according to the present embodiment, the search is performed using a modulo hashing algorithm. To search the cache store 24, the address from the arithmetic unit is hashed and an index to one or N cache blocks in the cache store 24 is generated. The number of generated indices is called a set associativity, and a set associativity of 1 is called a one-way set associative cache storage or a direct map cache storage, and the set associativity is larger than 1 and smaller than the number of cache blocks. Are referred to as set associative cache storage, and those whose set associativity is equal to the number of cache blocks are referred to as full associative cache storage. In the present embodiment, direct map cache storage or set associative cache storage is used.

The cache memory 24 can be designed so as to use either a virtual address or a physical address as an address of data used for generating an index. Those using the physical address are called physical address cache storage. In the present embodiment, physical address cache storage is used. In the computer system of the present embodiment, virtual storage is used, and the arithmetic unit 21 gives a virtual address when requesting data, so that the address translation unit 22 is provided between the arithmetic unit 21 and the cache storage unit 24. Then, the result obtained by the address translator 22 translating the virtual address into the physical address is given to the cache memory 24.

FIG. 3 is a diagram for explaining a physical page management unit 37, a paging management unit 36, and a kernel storage management unit 38 according to a conventional storage management method. The functions of the physical page management unit 37 and the paging management unit 36 are as described in FIG. 2, and the physical page management unit 37 is not currently used by the operating system or the application among the physical pages in the main memory. The physical page is managed, and the paging management unit 36, for example,
When processing a page fault interrupt, the physical page management unit 37 is requested to allocate a physical page. The kernel storage management unit 38 allocates and releases a storage area to the operating system when the operating system needs dynamic storage management during its operation.
In FIG. 2, the kernel storage management unit is omitted for the sake of simplicity.

In FIG. 3, the main memory 33 is divided into 4K-byte physical pages, and the starting physical addresses of each physical page are aligned on 4K-byte boundaries, and are 0x0000, 0x1000, 0x2000, and the like. ing. The physical page number of each physical page is
It is defined as a value obtained by dividing the head address of the physical page by several 4K, and becomes 0x0, 0x1, 0x2, and the like. In FIG. 3, the operating system has a physical page number 0x
A physical page of 0, a real-time thread occupies a physical page of 0x1, and a non-real-time thread occupies a physical page of 0x5. Therefore, the state shown in FIG.
Assuming that the execution of the operating system is one thread, on the computer system, the operating system, the real-time thread, and the non-real-time thread are operating in a total of three threads, and each thread occupies one physical page. It is in a state of occupying and operating.

The physical page management unit 37 manages a physical page that is not currently used.
Physical pages other than 0x0, 0x1, and 0x5 must be managed. The implementation of the physical page management unit shown in FIG. 3 is a known implementation by a conventional physical page management unit, and is managed in a single list structure. With this structure, as many threads repeatedly request and release physical pages, the order of physical page numbers in the list structure becomes random, and when a thread issues a physical page allocation request, It is uncertain whether the physical page of the physical page number is allocated.

The paging management unit 36 manages each page table in order to provide a unique virtual address space to a real-time thread and a non-real-time thread. FIG. 5 shows the status of the virtual address space of the real-time thread and the non-real-time thread and the status of the corresponding page table. FIG. 5 shows a state in which the virtual address space is 24 Kbytes, which is 6 pages in size. Although real-time applications and non-real-time applications both have their own address space, the application address space is also used by the operating system. Only half and the lower half are used by the operating system. The paging management unit manages the page table so that the lower half of the real-time application and the lower half of the non-real-time application are completely in the same state. In FIG. 5, both the real-time application and the non-real-time application are executing somewhere in the first page of the virtual address space (indicated by the hatching to indicate that they are being executed). However, according to the page table, the page 0x0 of the real-time application is replaced with the physical page 0x of the main storage.
0, and the page 0x0 of the non-real-time application occupies the physical page 0x5 of the main storage. The V in the page table flag indicates that this page table entry is valid. In this example, physical page 0x1 and physical page 0x5 collide on cache storage.

FIG. 4 is an explanatory diagram of one embodiment of a physical page management unit according to the method of managing unused physical pages according to the present invention. FIG. 4 shows a main memory 43, a physical page management unit 47, a kernel storage management unit 48, and a paging management unit 46, which are completely the same as those in FIG. The difference from FIG. 3 is that the color ID is assigned to the physical page of the main storage, and that the physical page management unit 47 manages unused physical pages in a plurality of list structures.

The assignment of the color ID is performed by the physical page management unit 47 when the computer system is started up and the address translator is not operating.

FIG. 7 is a flowchart showing a method for classifying physical pages by color ID when the physical page management unit is initialized in the present invention. First, the physical page management unit calculates the number of colors COT (Step S).
1). The number of colors COT of the main memory is as follows, where the capacity of the N-way set associative cache storage device is CAB bytes and the page size is PGB: COT = CAB / (PGB * N). The cache storage of the present embodiment is, for example, as shown in FIG.
In the case of a direct map cache storage having a capacity of 16 Kbytes, which is the same as the case of (1), and the page size is 4 Kbytes, the number of colors COT becomes 4. Next, the physical page management unit 47 calculates a color ID of a physical page not used by the operating system at that time. First, the top physical page is set as a calculation target (step S2), and it is determined whether the page is already used by the OS (step S3). If the OS does not use the physical page, the color ID of the physical page is calculated (step S4). Then, the physical page is linked to the calculated color ID list structure (step S5). Next, it is determined whether the physical page is the last physical page (step S6). If it is not the last physical page, the operation target is moved to the next physical page (step S7), and the process returns to step S3. If it is determined in step S3 that the physical page has already been used by the OS, the process proceeds to step S6. In this way, the processing from step S3 to step S6 is repeated up to the last physical page.

In the example of FIG. 4, the physical page number obtained by modulo the color number COT = 4 is the color ID, and the color ID is one of 0, 1, 2, and 3.
FIG. 4 shows, for simplicity, a case where the operating system does not use the main storage at all when the color ID is calculated. In FIG. 4, the color I
Physical pages with D of 0 and 1 are assigned to the operating system and real-time thread, respectively, and managed in a list structure for each color ID. Physical pages with color IDs 2 and 3 are managed in a single list structure for non-real-time threads. In other words, color I
Special management is performed for physical pages with D of 0 and 1, and management similar to that of the related art is performed for physical pages with color IDs of 2 and 3. The list structure linked for each color ID holds a color ID and a thread ID in its header.

In FIG. 4, the physical page management unit 47 of the present invention is requested to allocate a physical page by using a thread ID as an argument in addition to the simple physical page allocation function of the physical page management unit 37 of FIG. When a specific color I
It has a function of allocating a physical page having D. The kernel storage management unit 48 assigns a physical page by designating the thread ID of the operating system as shown in FIG.
Of the kernel storage management unit 38 of FIG.

The paging management unit 46 is modified as follows as compared with the paging management unit 36 of FIG. During execution of a real-time application, in order to guarantee that access to data becomes access to main storage or cache storage, the operating system or When the paging management unit 46 is called with the virtual address of the storage area, the size, and the thread ID as arguments, the paging management unit 46 specifies the thread ID of the real-time application and specifies the physical page. Is assigned. This point is the paging management unit 36 in FIG. 3 that allocates a physical page regardless of the thread ID.
Is different. In FIG. 4, the paging management unit 46
As a process executed by the application, the meaning of the term described as assignment / assignment with thread ID means that when a real-time application is being executed, an assignment specifying a thread ID is requested, and when the real-time application is not being executed. Means that the conventional assignment without specifying the thread ID in FIG. 3 is requested.

FIG. 8 shows that a real-time thread and an operating system may have one or more color IDs.
9 is a flowchart showing a method of allocating a physical page for exclusively using. First, the physical page management unit determines whether the thread ID is specified as an argument (step S1). If the thread ID is not specified, the request is from a non-real-time thread, and one physical page linked to the non-real-time thread list structure is allocated (step S5). In the embodiment of FIG. 4, a physical page having a color ID of 2 or 3 is allocated, but it is not known which color ID is allocated. If the thread ID is specified (step S1), the color I
The header of the list managed for each D is searched (step S2). If there is a list with the same thread ID, it is determined whether or not the list is an empty list (step S3). If there is a list other than the physical page, one physical page linked to the list is allocated (step S4). When there is no list that is not an empty list, a list in which a valid ID is not set in the thread ID (a list structure not reserved for a valid thread ID) is searched (step S6). If there is such a list, a thread ID is set in the header of the list, and the thread having the thread ID reserves the list (step S7). And then
A physical page linked to the list is assigned (step S8). In step S6, the thread I
If there is no list in which a valid ID is not set in D, the real-time thread is forcibly terminated (step S9).

In FIG. 4, a physical page with a color ID of 0 is assigned to the operating system, a physical page with a color ID of 1 is assigned to the real-time thread, and a color ID 2 is assigned to the non-real-time thread. 3 and 3 physical pages are allocated.

FIG. 6 shows the state of the virtual address space and the state of the page table of the real-time application and the non-real-time application when the physical page management unit of the present invention is used. When the state of the virtual address space and the state of the page table of the real-time application and the non-real-time application when the conventional physical page management unit is used are compared with FIG. 5 showing the state of the page table, the state of the virtual address space is completely the same. It can be seen that the structure of the table is exactly the same, but only the physical page number written is different.

From FIGS. 5 and 6, it is possible to compare the access status of the cache storage between the case of the conventional storage management method and the case of the unused physical page management method of the present invention. That is, in the conventional storage management method, there is a possibility that contention of cache storage may occur, and the management method of the present invention eliminates the possibility.

In FIGS. 5 and 6, the fact that the state of the virtual address space is exactly the same means that there is no need to change the application, and the fact that the structure of the page table is exactly the same means that the paging management unit has Means little change. As described above, in the present embodiment, the intended effect can be obtained by devising a method of managing unused physical pages in the physical page management unit.

[0043]

As described above, according to the present invention, a real-time application makes a reservation for exclusive use of one or a plurality of cache blocks, and executes using only the reserved cache blocks. This has the following effects. 1. When executing a real-time application, a predictable calculation of the processing time can be achieved. 2. When executing a real-time application, high-speed calculation can be realized because the cache storage can be used.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating an example of classification of physical pages by color ID and an example of mapping of physical pages having each color ID to cache storage.

FIG. 2 is a block diagram showing an example of a configuration of a computer system used to execute a cache block reservation method of the present invention.

FIG. 3 is a diagram illustrating a physical page management unit, a paging management unit, and a kernel storage management unit according to a conventional storage management method.

FIG. 4 is an explanatory diagram of an embodiment of a physical page management unit according to the unused physical page management method of the present invention.

FIG. 5 is a diagram illustrating an access state of cache storage according to a conventional storage management method.

FIG. 6 is a diagram illustrating an access state of a cache storage according to a method of managing unused physical pages according to the present invention.

FIG. 7 is a flowchart illustrating a method of classifying physical pages by color ID when a physical page management unit is initialized in the present invention.

FIG. 8 is a flowchart illustrating a method of allocating a physical page for a real-time thread and an operating system to exclusively use one or more color IDs according to the present invention.

[Explanation of symbols]

 Reference Signs List 21 arithmetic unit 22 address translation unit 23, 33, 43 main storage 24 cache storage 25 auxiliary storage 26, 36, 46 paging management unit 27, 37, 47 physical page management unit 38, 48 kernel storage management unit

Claims (8)

[Claims] 1. A computer system having an arithmetic unit, an address translator, and a storage unit, the storage unit having a main storage unit, and a high-speed cache storage unit between the arithmetic unit and the main storage unit. The cache storage device is composed of a hash device and a set of cache blocks. The cache storage device specifies a position of a cache block by an index, and the cache storage device uses a part of a physical address of data requested by an arithmetic device. A physical address cache storage device that generates an index using a hash device, wherein the cache storage device uses a modulo hashing algorithm as an algorithm used by the hash device, and the cache storage device stores the number of indexes generated by the hash device. Is the number of cache blocks In the case of an N-way set associative cache storage device with a smaller integer N, when the computer system executes a real-time application, the real-time application exclusively uses one or more cache blocks in executing the real-time application. In the cache block reservation method of making a reservation to do, the main storage of the main storage device is divided into physical pages, a set of indexes obtained by the hash device from all the addresses included in the physical page is defined as a color,
Physical pages included in the main memory are classified by color ID, and at the time of execution of the real-time application, one or more color IDs are selected from a set of currently unused color IDs, and the selected color IDs are determined. , So that the thread executing the real-time application can use the physical page exclusively.
A method for reserving a cache block, comprising managing a thread ID and a color ID. 2. When the capacity of the N-way set associative cache storage device is CAB bytes and the page size is PGB bytes, the number of colors COT of main memory is COT = CAB / (PGB * N), and a modulo function is provided. 2. The cache block reserving method according to claim 1, wherein COI, which is the color ID of the physical page, is determined from the physical page number PFN by the following formula: COI = PFN mod COT. 3. The cache according to claim 1, further comprising an arithmetic unit, an address translator, and a storage unit, wherein the storage unit includes a main storage unit, and a high-speed cache storage unit between the arithmetic unit and the main storage unit. The storage device is composed of a hash device and a set of cache blocks, the cache storage device specifies the position of the cache block by an index, and the cache storage device uses a part of the physical address of the data requested by the arithmetic device, A physical address cache storage device that generates an index by a hash device, wherein the cache storage device uses a modulo hashing algorithm as an algorithm used by the hash device, and the cache storage device has a number of indexes generated by the hash device, An integer N smaller than the number of cache blocks A computer system, which is an N-way set associative cache storage device, and executes a real-time application when executing the real-time application.
In a computer system with a cache block reservation function that reserves one or more cache blocks for exclusive use, a main memory of a main storage device is divided into physical pages, and all addresses included in the physical pages are divided. When defining a set of indices obtained by a hash device from as a color, the physical pages included in the main memory are classified by color ID, and at the time of execution of a real-time application, one of the currently unused color IDs is selected from the set. Alternatively, a physical page that selects a plurality of color IDs and manages the thread ID and the color ID so that a thread that executes the real-time application can exclusively use a physical page having the selected color ID. A cache having page management means. Gerhard block reservation function with a computer system. 4. When the capacity of the N-way set associative cache storage device is CAB bytes and the page size is PGB bytes, the physical page management means sets COT = CAB / (PGB * as the number of colors COT of main memory. 4. The computer system according to claim 3, wherein when N) is calculated and the modulo function is mod, the COI that is the color ID of the physical page is determined from the physical page number PFN by COI = PFN mod COT. 5. The physical page management means, when the computer system is started up, divides an area of the main storage that is not used at that time into physical pages in a state where the address translator is not operating. , A physical page having several color IDs is used for a real-time thread and an operating system, and those physical pages are assigned a color ID and a thread ID.
And physical page numbers, and the other color I
The computer system according to claim 3, further comprising a physical page management unit that manages a physical page having D for a non-real-time thread. 6. The physical page management means has a paging management unit, and the paging management unit uses a virtual page number output by the address translation device to convert a physical page number into a physical page number for each virtual address space. It has a function of constructing a page table for converting to a number and managing the page table, and the paging management unit is configured such that, when a real-time application is executed, data access is performed to a main storage or a cache storage. In order to guarantee access, when a request is made for allocating a storage area resident in the main storage, that is, when paging does not occur, the storage area is called with the virtual address, the size, and the thread ID as arguments. Request, a physical page allocation request is made to the physical page management unit by designating the thread ID, and the non-real During im application execution, perform an allocation request of a physical page without specifying a thread ID, and build a page table using the physical page number of the resulting physical page, the computer system according to claim 5. 7. The physical page management means according to claim 1, wherein when the operating system requires dynamic storage management during its operation, the operating system specifies a thread ID of the operating system to the physical page management unit. 6. The computer system according to claim 5, further comprising a function of making a page allocation request and allocating a storage area for a data structure created by the operating system. 8. An apparatus comprising an arithmetic unit, an address translator, and a storage unit, wherein the storage unit includes a main storage unit, and a high-speed cache storage unit between the operation unit and the main storage unit. The storage device is composed of a hash device and a set of cache blocks, the cache storage device specifies the position of the cache block by an index, and the cache storage device uses a part of the physical address of the data requested by the arithmetic device, A physical address cache storage device that generates an index by a hash device, wherein the cache storage device uses a modulo hashing algorithm as an algorithm used by the hash device, and the cache storage device has a number of indexes generated by the hash device, An integer N smaller than the number of cache blocks A computer system, which is an N-way set associative cache storage device, and executes a real-time application when executing the real-time application.
In a computer system having a cache block reservation function for making a reservation for exclusive use of one or a plurality of cache blocks, a recording medium in which a physical page management program for managing a physical page is recorded, wherein the main storage device has The main memory is divided into physical pages, a set of indices obtained by the hash device from all addresses included in the physical page is defined as a color, a color ID is assigned to each color, and a physical ID included in the main memory is assigned. When pages are classified by color ID, the physical page management program that manages physical pages by color ID and thread ID responds to a physical page allocation request by requesting the thread ID of the operating system or application that uses the physical page. Is specified as an argument A first procedure of determining whether or not a thread ID is specified; a second procedure of allocating one physical page having a color allocated to a non-real-time thread; and specifying a thread ID. If there is a third procedure of searching for a given thread ID for a set of physical pages managed for each color ID, and if there is a set of physical pages having the same thread ID, A fourth procedure for determining whether or not there is an unused physical page having the color ID for all sets of those physical pages; A fifth procedure of allocating one physical page having a color ID, and, in the case of an empty set, a set of physical pages to which a valid thread ID is not assigned. A sixth procedure for searching, and when there is such a set of physical pages, a seventh procedure for reserving a set of unused physical pages of the color ID by assigning a thread ID, Eighth procedure that allocates one physical page from the set of physical pages having the color ID in the seventh procedure, and in the sixth procedure, there is no set of physical pages to which a valid thread ID is not assigned. In a case, a ninth procedure for forcibly terminating the real-time thread is provided, wherein the recording medium stores a physical page management program.