JP2002084311A - Packet transmission equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the speed of transfer in equipment, regarding packet transmission equipment which transfer variable length packets according to destinations. SOLUTION: This packet transmission equipment transfers packet from a receiving memory, corresponding to receiving side ports of packet end portions 16, 17 to a buffer memory 11, and transfers the packets from the buffer memory 11 to a transmitting side memory corresponding to transmitting side ports of packet forming parts 18, 19 which correspond to destinations. It is provided with a content addressable memory 12 (CAM), a means of a receiving control part 14, a transmitting control part 15, etc., and a means for transferring from the receiving memory to a buffer memory 11 with a block unit of a prescribed length. The memory 12 stores the transmitting side ports, corresponding to MAC addresses and reads a transmitting port, corresponding to the MAC address coincident to a destination MAC address. The control parts 14, 15 access the memory 12 by the destination MAC address of the packet received and stored in the receiving memory, read the transmitting side port, and transfer the packets from the buffer memory 11 to a transmitting memory, corresponding to the transmitting side port.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a packet transfer processor for receiving variable-length packets from a plurality of receiving ports and transmitting the packets from a transmitting port corresponding to the destination of each packet.

[0002]

2. Description of the Related Art A network for transmitting and receiving a variable-length packet has a single or a plurality of packet transfer processors for transferring the packet to its destination address. For example, as shown in FIG.
It is provided between a local network including the subscriber node device 55 and the Internet network 54, and distributes received packets according to destination addresses.

The packet transfer processing device 51 has a configuration including a subscriber node interface unit 52 to which a plurality of subscriber node devices 55 are connected, and a packet distribution unit 53 that distributes a packet according to a destination address. The client node device 55 connects a plurality of personal computers (personal computers) 56 and transfers a packet from the Internet network 54 to the personal computer 56 corresponding to the destination address.
Also, the packet from the personal computer 56 is transferred to a provider or the like included in the Internet network 54 corresponding to the destination address.

FIG. 9 is an explanatory view of a conventional packet transfer processing apparatus, in which 61 is a subscriber terminating unit, 62 is an Internet network terminating unit, 63 is a buffer memory, 64 is a distribution destination port table, and 65 is transmission / reception control. Unit, 66 is a subscriber side packet generation unit, 67 is an Internet network packet generation unit, Pin11-Pin1n, Pin21-Pin2n
Is the port on the receiving side of the packet, Pout11 to Pout1
n, Pout21 to Pout2n indicate transmission-side ports.

A packet has a destination MAC (Media Accesses).
s Control) address, source MAC address, and n
Byte data and CRC (Cyclic Redundancy Che)
ck) (or FCS; Frame Check Sequence), and the n-byte data is of variable length. The distribution destination port table 64 includes destination MAC addresses and transmission-side ports Pout11 to Pout1n and Pout21 to Pout.
It is a table in which t2n is associated. Further, the subscriber-side terminating unit 61 and the Internet network terminating unit 62 each include a receiving memory for temporarily storing received packets,
The subscriber-side packet generation unit 66 includes a transmission memory for temporarily storing packets to be transmitted, and a function of generating a packet in a format compatible with the local network. The Internet network packet generation unit 67 includes a transmission memory, It has a function of generating packets in a format compatible with the Internet network.

The transmission / reception control unit 65 includes a subscriber-side termination unit 61
When the packet has been received by the reception memory of the Internet network termination unit 62, the packet is transferred to the buffer memory 63 according to the reception completion order, and the distribution destination port table 64 is searched based on the destination MAC address. Read the sender port corresponding to the address,
The subscriber side packet generator 66 to which the transmitting side port belongs
Alternatively, the packet from the buffer memory 63 is transferred to the transmission memory of the Internet network packet generator 67. Thereby, the packet received in the receiving memory of the subscriber side terminating unit 61 is transferred from the subscriber side packet generating unit 66 as a local network packet format according to the destination MAC address. Alternatively, the packet is transferred from the Internet network packet generator 67 as an Internet network packet format.

[0007]

Since the packet length is variable, when the packet is transferred from the reception memory of the subscriber-side terminal unit 61 or the Internet-side terminal unit 62 to the buffer memory 63, for example, the maximum length or close to the maximum length is used. When a packet having a packet length is transferred, the packet cannot be transferred to the buffer memory 63 even if the packet is received and stored in another reception memory during that time. In other words, when a packet having a long packet length is transferred within the device, the transfer of another packet within the device is awaited, and there is a problem that the transfer delay of the packet increases.

[0008] Also, MA from the distribution destination port table 64 sequentially
The transmission / reception control unit 65 reads the C address, compares the MAC address with the destination MAC address of the packet to be transferred to the buffer memory 63, and reads the transmission-side port number corresponding to the matched MAC address. Although the packet can be transferred from 63 to the transmission port corresponding to the destination MAC address, the time required for the search processing of a large number of MAC addresses becomes long. As a result, there is a problem that packet transfer delay increases. An object of the present invention is to speed up the transfer of a packet in a device.

[0009]

Referring to FIG. 1, a packet transfer processing device according to the present invention transfers a packet from a reception memory in a packet termination unit corresponding to a plurality of reception ports to a buffer memory 11, This buffer memory 1
1. A packet transfer processing device for transferring from 1 to a transmission memory in a packet generator of a transmission port corresponding to a destination,
Stores transmission-side port information (for example, a port number) corresponding to the AC address, and stores the M that matches the destination MAC address.
The contents referenceable memory 12 is accessed by using the contents referenceable memory 12 (CAM) for reading the transmission side port corresponding to the AC address and the destination MAC address of the packet received and stored in the reception memory, and the transmission side port information is read. The transfer destination control unit 13 and the transmission control unit 1 that transfer a packet from the buffer memory 11 to the transmission memory corresponding to the transmission side port
5 and the like.

A destination port table in which MAC addresses are stored as read addresses for all transmission ports and a destination MAC address
When a MAC address that matches the address is not stored, a learning control unit that writes the transmission port and the destination MAC address read from the distribution destination port table can be provided. Also, means for adding the packet length of the packet from the receiving port as a length, adding the packet length to the head of the packet and writing it to the reception memory, and determining whether or not the packet length of the packet is longer than a predetermined length by the length. Means for dividing the data into blocks when the data is long, transferring the data from the reception memory to the buffer memory 11 in block units, securing a continuous area corresponding to the length in the buffer memory 11, and writing data in block units. be able to.

When a plurality of reception memories are transferred to the buffer memory 11 in units of blocks, a modulo adding unit for adding information (for example, a modulo number) for identifying each different packet to each block, Means for sequentially writing data in block units in the area corresponding to the modulo number. Also, the data is transferred from the reception memory to the buffer memory 11 in block units,
According to the destination MAC address included in the head block of one packet, the content-accessible memory is accessed to read the transmission-side port, and 1 is transferred from the reception memory to the buffer memory 11.
Means may be provided for transferring a single packet from the buffer memory 11 to the transmission memory corresponding to the transmission-side port when the transfer of all blocks of the packet is completed.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is an explanatory view of an embodiment of the present invention. 1 is a packet transfer processing device, 2 is a local network, 3 is an Internet network, 11 is a buffer memory,
2 is a content referable memory (CAM; Content Address)
able Memory, associative memory), 13 is a transfer destination control unit,
14 is a reception control unit, 15 is a transmission control unit, 16 and 17 are packet termination units, and 18 and 19 are packet generation units.

A packet termination unit 1 connected to a local network 2
Reference numeral 6 denotes a subscriber-side termination unit.
The packet terminating unit 17 connected to is equivalent to the Internet-side terminating unit, and includes a plurality of receiving ports and a receiving memory. The packet generator 18 connected to the local network corresponds to a subscriber-side packet generator, and the packet generator 19 connected to the Internet 3 corresponds to an Internet network packet generator, each having a plurality of transmission ports. And a transmission memory.

The content referenceable memory 12 (CAM)
A MAC address and transmission-side port information are stored. By accessing using the destination MAC address of the packet terminated by the packet terminating units 17 and 18, the MAC address corresponding to the destination MAC address is corresponded. This is to read out the transmission side port information. Therefore, the transmission-side port information corresponding to the destination MAC address can be obtained at a high speed without performing the process of reading the MAC address and comparing with the destination MAC address. The transfer destination control unit 13 uses the transmission-side port information.
Controls the transmission control unit 15 to transfer packets from the buffer memory 11 to the transmission memories of the packet generation units 18 and 19 corresponding to the transmission-side ports.

The transfer of packets from the receiving memory, not shown, of the packet terminating units 16 and 17 controlled by the receiving control unit 14 to the buffer memory 11 is performed for blocks of a predetermined length. That is, a packet having a long packet length is divided into blocks of a predetermined length, and a plurality of packets are sequentially transferred in block units. In this case, a modulo number is added to a block as information for identifying a packet in the transfer process and the block is transferred. The buffer memory 11 deletes the modulo number and sequentially stores blocks having the same modulo number in a continuous area. Thus, one packet is formed.

For example, when the first to third packets received from the first to third receiving ports are alternately transferred in block units, the transfer block for the first packet is “01”, and the first packet is “01”. "10" for the transfer block of the second packet and "1" for the transfer block of the third packet.
A modulo number of 1 "can be added and transferred.
At the end of the transfer, the modulo number is set to "00". When the transfer of a new packet in the block unit transfer process is started, a modulo number “00” due to the end of transfer is added as a modulo number different from other modulo numbers that are not in use. Can be.

Therefore, one block of a packet of another modulo number can be transferred by ending the transfer of one block of a packet of a certain modulo number without waiting for the entire transfer of a packet having a long packet length. In addition, the waiting time for a packet having a short packet length can be reduced. That is, the processing time of the intra-device transfer can be reduced.

FIG. 2 and FIG. 3 are explanatory diagrams of the packet transfer processing device according to the embodiment of the present invention.
Is the subscriber end unit, 22 is the Internet network end unit,
23 and 25 are reception memories, 24 and 26 read request management units,
27 is a read request receiving unit, 28 is a read order managing unit, 29 is a read waiting managing unit, 30 is a modulo adding unit, 31 is a length fetching unit, 32 is a block size determining unit, 33 is a data read control unit, and 34 is Data head indicator, 35 is DPRA
M write control unit, 39 is a read end data management unit, Pin1
1 to Pin21 and Pin21 to Pin2m indicate receiving ports.

In FIG. 3, reference numeral 36 denotes a buffer memory (dual-port memory DPRAM), 37 denotes a data head fetch unit, 38 denotes a memory (FIFO), and 40 denotes a CA.
M search unit, 41 is a CAM learning control unit, 42 is a content accessible memory (CAM), 43 is a distribution destination port table,
4 is a distribution destination determination unit, 45 is a DPRAM read control unit, 4
6 and 48 are transmission memories, 47 is a subscriber side packet generation unit, 49 is an Internet network packet generation unit, and Pout
11 to Pout1n and Pout21 to Pout2m indicate transmitting ports. In addition, although it includes a plurality of highways, it is illustrated as one highway for simplification.

The buffer memory 36 corresponds to the buffer memory 11 of FIG. 1, the content referenceable memory 42 corresponds to the content referenceable memory 12 of FIG.
To Pin21 and transmission-side ports Pout11 to Pout1
n are connected to the local network 2 in FIG.
in21-Pin2m and transmission-side ports Pout21-P
out2m is connected to the Internet network 3 of FIG.

Receiving ports Pin11 to Pin21, P
Packets from in21 to Pin2m are terminated by the subscriber side terminating unit 21 and the Internet network terminating unit 22, and are written into the receiving memories 23 and 25. At this time, the packet length including the destination MAC address and the transmission source MAC address can be obtained by a counter or the like that counts bits at the time of writing. The length information of the packet thus obtained is added to the head of the packet written in the reception memories 23 and 25. This length adding function can be provided in the subscriber side termination unit 21 and the Internet network termination unit 22. Note that length information may be added to the packet in some cases, but usually indicates a data length, and information indicating a packet length including a header such as a destination MAC address is not added. Then, when the writing of one packet to the reception memories 23 and 25 is completed, the read request management units 24 and 26 send a read request to the read request reception unit 27.

If the read requests do not conflict, the read order management unit 28 notifies the read request to the data read control unit 33. If the read requests conflict, the data is managed by a queue of the read wait management unit 29. Then, the read request is taken out of the queue in the order according to the control of the read order management unit 28 and notified to the data read control unit 33. The length fetch unit 31 fetches the length information of the packets stored in the reception memories 23 and 25,
In step 2, a block size for dividing the packet is determined, and the data read control unit 33 is notified. For example, a packet having a minimum packet length is set as a block size, and other packets are divided into the block size. Alternatively, the block size can be fixedly determined in advance. Even if the last block of the packet divided according to the block size becomes fractional, the packet is transferred as it is as one block. In this case, whether or not the packet length is long according to the predetermined length to be divided into blocks can be immediately determined from the above-described length information.

The data read control unit 33 is based on the block size information from the block size determination unit 32 and the read request from the read order management unit 28, and
4 and 26 are read from the reception memories 23 and 25 in block units and transferred to the buffer memory 36. At this time, a modulo number that allows different packets to be identified in the modulo adding section 30 is added to the buffer memory 36.
Transfer to The writing means of the DPRAM writing control unit 35 controls writing to the buffer memory 36 in block units based on the read control information from the data reading control unit 33. In this case, a modulo number added corresponding to a block is deleted by a write control function for the buffer memory 36 (not shown), and blocks having the same modulo number are sequentially written in the same continuous area. In this case, since the length indicating the packet length can be determined, a continuous area can be easily secured. When the transfer of all blocks is completed, the transfer of one packet to the buffer memory 36 is completed.

The data head fetch unit 37 is provided in the reception memory 2.
3, 25, the head portion of the packet transferred in block units to the buffer memory 36, that is, the block including the destination MAC address is fetched, and the first-in first-out memory 38
(FIFO) is sequentially written to the destination MAC address, CA
The destination MAC address is sequentially read and transferred to the M search control unit 40.

Using the destination MAC address, the CAM search control section 40 reads out the transmission-side port information corresponding to the MAC address stored in the content referenceable memory 42 (CAM), and notifies the distribution destination determination section 44 of the information. In this case, the destination MA
When the C address does not exist in the contents referable memory 42, the CAM learning control unit 41 is started, and the CAM learning control unit 41 reads out the transmission side port information corresponding to the destination MAC address from the distribution destination port table 43, and reads the MA.
The transmission-side port information is written into the content referenceable memory 42 in association with the C address. Therefore, the MAC address and the transmission-side port information actually used for packet transfer can be stored in the content referenceable memory 42 by the learning control unit such as the CAM learning control unit 41. Thus, from the next time, the transmission-side port information corresponding to the MAC address can be immediately read out from the content referenceable memory 42.

The distribution destination judging section 44 includes a buffer memory 36
When one packet of data is transferred to the block, the transmission port number from the CAM search control unit 40 is set to D.
Notify the PRAM read control unit 45. The DPRAM read control unit 45 causes the transmission memory 46 or the transmission memory 48 corresponding to the transmission-side port to read and transfer one packet of data from the buffer memory 36. The subscriber-side packet generation unit 47 converts the packet into a packet format compatible with the local network, and specifies the designated transmission-side ports Pout11 to Pout1.
n. The internet network packet generation unit 48 converts the packet into a packet format compatible with the internet network, and specifies the designated transmission-side ports Pout21 to Pout21.
The packet is transmitted to ut2m.

FIG. 4 is an explanatory diagram of the distribution destination judging process, showing the contents referable memory 42 (CAM) and the distribution destination port table 43, R / W is a read / write control signal, and CMD / DT is command data. Switching control signal, DT
B indicates a data bus for transferring a MAC address, and MF indicates a match flag. The distribution destination port table has a configuration in which distribution destination highway information HW and distribution destination port information (transmission side port information) P are stored in an area where the MAC address is a read address, and the distribution destination highway information HW and the distribution destination The port information P is set for all distribution destination ports in the packet transfer device by, for example, an upper-level operating system.

The content referenceable memory 42 learns the MAC address by the CAM learning control unit 41 (see FIG. 3), and stores the destination highway information HW and the destination port information P corresponding to the MAC address. . The content referenceable memory 42 stores the destination MA added from the CAM search control unit 40 (see FIG. 3) via the data bus DTB.
It has a flag area for setting a match flag MF when a MAC address that matches the C address is stored.

As described above, the content-accessible memory 42 is accessed from the CAM search control unit 40 using the destination MAC address, and the read / write control signal R / W indicates a read, and the MAC address matching the destination MAC address. Is stored, the distribution destination highway information HW and the distribution destination port information P can be read. At that time, the match flag MF is set, and the read distribution destination highway information HW and the distribution destination port are read. The information P and the CAM search control unit 40 are transferred. The match flag MF is configured to be reset by re-reading, or
It may be configured to be reset at the start of the AC address search.

The CAM search control unit 40 sets the match flag M
When F is set, the destination highway information HW and the destination port information P read from the content referenceable memory 42 are read.
Is transferred to the distribution destination determination unit 44. Also, match flag MF
Is not set, it is determined that a MAC address that matches the destination MAC address is not stored in the content referenceable memory 42. Therefore, the CAM learning control unit 4
1 is activated, and the destination highway information HW and the destination port information P corresponding to the destination MAC address read from the destination port table 43 and the read / write control signal R / W indicating write are stored in the content referenceable memory 42. In addition, M
AC address and corresponding destination highway information H
W and distribution destination port information P are written. In this way, the contents referenceable memory 42 can learn the distribution destination highway HW and the distribution destination port that are actually used.

FIG. 5 is a diagram for explaining transfer in block units.
When writing a variable-length packet including a source MAC address, a destination MAC address, n-byte data, and a CRC into a reception memory, as described above, this packet length is obtained and added to the beginning as a length. . Then, when transferring data from the receiving memory to the buffer memory, the data is read out and transferred in divided block units. It should be noted that the first to fourth blocks are each transferred as a block of m bytes, and the fifth block is a block having a number of bytes of m bytes or less.

FIG. 6 is a diagram for explaining the transfer of a plurality of packets in units of blocks. In the case where packets received from the ports Pa, Pb, and Pc on the receiving side are transferred in units of blocks, for example, at time t0, the port on the receiving side is transferred. Pa, Pb,
Assuming that the reception of the packets A1, B1, and C1 has been completed in the reception memory corresponding to Pc and the reception of the packet B2 has been completed at time t1, the packet B1 having a short packet length is divided into one block, and the other packets A1 and C1 are divided. For example, time t
11, the block A1-1 obtained by dividing the packet A1 is transferred from the reception memory to the buffer memory without transferring the entire length of the packet A1 to the packet B1 at the next time t12.
At the next time t13.
1-1, and the blocks A1-2 of the packet A1 are sequentially transferred in units of blocks such that the blocks A1-2 of the packet A1 are transferred at the next time t14.

In that case, the block A1 of the packet A1
−1 to A1-6 each have a modulo number such as “0”.
1 "indicates that the packet is a packet A1, and the packet B1 has a modulo number, for example," 1 ".
0 "and the blocks C1-1 to C1-3 of the packet C1.
Are respectively added with a modulo number "11". Then, when writing to the buffer memory, the modulo number is removed from the continuous area corresponding to each modulo number, and the data is sequentially written in block units. Therefore, the packet B1 having a short packet length can be transferred to the buffer memory without waiting until the transfer of the packet A1 having the long packet length is completed. That is, the speed of the transfer in the device can be increased.

FIGS. 7A and 7B are explanatory diagrams for comparing a conventional example of intra-device transfer with the present invention. FIG. 7A shows a conventional example, and FIG. 7B shows a case of the present invention. Also, packets A from the receiving ports Pa to Pc
When the reception completion times of the packets A1, B1, B2, and C1 are different from each other, the packet A1 and C1 are divided into blocks A1-1 to A1-6 and C1-1.
-C1-3.

In the conventional example shown in FIG. 3A, the packet A1 previously received is transferred from the reception memory to the buffer memory, and after the transfer of the packet A1, the packet B1 is transferred to the reception memory. To the buffer memory, then the packet C1 is transferred, and after the completion of the transfer of the packet C1, the next packet B2 is transferred. That is, the packet B1 after the reception of the packet A1 is completed.
Are waiting until the transfer of the packet A1 having a long packet length is completed, and the delay of the transfer of the packet B1 in the device is large.

On the other hand, according to the present invention, as shown in (B), a packet having a long packet length is divided into, for example, m-byte blocks. Transfer to buffer memory,
When the next block A1-2 is also transferred and the reception of the m-byte packet B1 of one block length is completed, the packet B1 is transferred next to the block A1-2, and then the block of the packet A1 is transferred. A1-3 is transferred.

At this time, assuming that the reception of the packet C1 having a length of 3 blocks has been completed, the block C1-1 of the packet C1 is transferred after the block A1-3, and the block A1-4 of the packet A1 is transferred next. Then, the block C1-2 of the packet C1 is transferred, and then the block A1-5 of the packet A1 is transferred. At this time, assuming that the reception of the m-byte packet B2 of one block length has been completed, the packet B2 is transferred next to the block A1-5, and then the block C1-3 of the packet C1 is transferred. Packet A
One block A1-6 is transferred. Therefore, a packet with a short packet length is not waited until the transfer of a packet with a long packet length is completed, so that the overall speed of transfer within the apparatus can be increased.

[0038]

As described above, according to the present invention, the MAC
A buffer memory 11, a content-accessible memory (CAM) 12 and 42 storing transmission-side port information corresponding to an address, and a transmission-side port corresponding to a destination MAC address.
There is provided a means such as a distribution destination determination unit 44 and a DPRAM read control unit 45 for transferring the transmission data from the transmission memory 36 to the transmission memories 46 and 48 corresponding to the transmission ports, and high-speed reading of the transmission port information corresponding to the destination MAC address of the packet. Since it is possible, there is an advantage that the speed of the packet transfer process in the device can be increased. Also, C
The learning control means such as the AM learning control unit 41
Since it is possible to learn about the address and the port information on the transmission side, there is an advantage that correspondence by expansion of the system or the like is simplified.

The receiving memories 21 and 2 corresponding to the receiving ports
2 is transferred to the buffer memory 36 by dividing the packets into blocks of a predetermined length, and transferring the blocks in units of blocks. Since the transfer can be performed to the buffer memory 36 by the completion of the transfer in units of blocks without waiting, there is an advantage that the waiting time can be shortened and the speed of the transfer of the packet in the device can be increased.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of an embodiment of the present invention.

FIG. 2 is an explanatory diagram of a packet transfer processing device according to an embodiment of the present invention.

FIG. 3 is an explanatory diagram of a packet transfer processing device according to an embodiment of the present invention.

FIG. 4 is an explanatory diagram of a distribution destination determination process.

FIG. 5 is an explanatory diagram of transfer in block units.

FIG. 6 is an explanatory diagram of transfer of a plurality of packets in block units.

FIG. 7 is a diagram illustrating a comparison between a conventional example of intra-device transfer and the present invention.

FIG. 8 is an explanatory diagram of a network configuration.

FIG. 9 is an explanatory diagram of a conventional packet transfer processing device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Packet transfer processing apparatus 11 Buffer memory 12 Content referenceable memory (CAM) 13 Transfer destination control unit 14 Reception control unit 15 Transmission control unit 16, 17 Packet termination unit 18, 19 Packet generation unit

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Toshihiro Noguchi 3-22-8 Hakata Ekimae, Hakata-ku, Fukuoka City, Fukuoka Prefecture Inside Fujitsu Kyushu Digital Technology Co., Ltd. (72) Inventor Toyohiko Yoshino Nakahara-ku, Kawasaki City, Kanagawa Prefecture 4-1, Kamikodanaka, Fujitsu Limited (72) Inventor Hideshi Abe 4-1-1, Kamikodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture F-term within Fujitsu Limited (reference) 5K030 GA03 HA08 HB28 HC01 HD03 JA05 JL07 KA03 KA05 KA13 MA13 MB11

Claims (5)

[Claims] 1. A packet transfer processor for transferring a packet including a MAC address indicating a destination from a reception memory corresponding to a plurality of reception ports to a buffer memory and transferring the packet from the buffer memory to a transmission memory corresponding to a transmission port. And stores the sender port information corresponding to the MAC address,
A memory capable of reading the contents of the transmission-side port corresponding to the MAC address corresponding to the MAC address indicating the destination, a memory capable of referring to contents, and an M indicating the destination of the packet received and stored in the reception memory
Means for accessing the contents referable memory by using an AC address, reading the transmission-side port information, specifying a transmission memory from the transmission-side port information, and transferring a packet from the buffer memory to the specified transmission memory. A packet transfer processing device characterized by the above-mentioned. 2. A destination port table storing transmission side port information using the MAC address as a read address, and a destination MA of the packet in the content referenceable memory.
Learning control means for writing, when a MAC address corresponding to the C address is not stored, the transmission-side port information read from the distribution destination port table and the destination MAC address to the content referenceable memory. 2. The packet transfer processing device according to claim 1, wherein: 3. A means for adding a packet length of a packet from the receiving port as a length and adding the packet to the head of the packet and writing the packet into the reception memory, and determining whether the packet length of the packet is longer than a predetermined length. Judgment is made based on the length added to the head of the packet, and when the length is longer than a predetermined length, the packet is divided into blocks of the predetermined length and transferred in blocks from the reception memory to the buffer memory, and the length is stored in the buffer memory. 3. The packet transfer processing device according to claim 1, further comprising means for securing a corresponding continuous area and writing the data in block units. 4. A modulo adder for adding a modulo number to each block to identify different packets when transferring from the plurality of reception memories to the buffer memory in block units, and a modulo number of the buffer memory. 4. The packet transfer processing device according to claim 1, further comprising: means for sequentially writing data in block units in a corresponding area. 5. The reception memory transfers data in block units from the reception memory to the buffer memory, accesses the contents referenceable memory by a destination MAC address included in a head block of one packet, and reads transmission-side port information. And means for transferring as one packet from the buffer memory to the transmission memory specified by the transmission-side port information upon completion of transfer of all blocks of the one packet from the buffer memory to the buffer memory. 5. The packet transfer processing device according to claim 4.