JP2001022638A - Information processing system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an information processing system enabling access suitable for each of localities even when processing parts having different localities are mixed concerning memory access. SOLUTION: This information processing system is composed of four modules 0 to 3 accessible at the same time and each capable of reading/writing for the unit of 16 bytes and when storing the image data of 64 bytes composed of four packs in a unified memory capable of reading/writing for the unit of 64 bytes, in a linear access mode, four packs (0, 0), (0, 1), (0, 2) and (0, 3) are stored in the modules 0, 1, 2 and 3, respectively. At the time of tile access mode, four packs (0, 0), (1, 0), (2, 0) and (3, 0) are stored in the modules 0, 1, 2 and 3, respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an information processing system in which a plurality of processing units access the same memory, and more particularly to an increase in memory access speed in a system employing a unified memory architecture (UMA).

[0002]

2. Description of the Related Art A processing unit in an information processing system has various localities (locality) regarding memory access depending on the processing performed. The locality here mainly means spatial locality. In a data structure composed of a plurality of data, when a certain data is accessed, the data arranged near the data is also accessed in the near future. It is a property that the possibility is high. Traditionally,
Ingenuity has been devised to make effective use of different localities depending on the processing.

For example, Japanese Patent Application Laid-Open No. 8-297605 discloses that a memory space is divided into small rectangular tiles, and addresses of a memory and a cache are managed so as to be linear in the tiles. When accessing, a method of transferring to a cache in tile units is disclosed.
In this method, in a process such as texture mapping, which has a two-dimensional locality to an image, that is, a process in which the next access may be performed in all the two-dimensional directions of the image, The hit rate is improved because caching is performed in units of two-dimensional tiles.

On the other hand, in recent years, in a system LSI, a unified memory architecture (U
MA) is used. Unified memory (hereinafter,
The term “UM” refers to a memory that integrates and stores data (eg, CPU instructions and data, display image data, texture data, and the like) conventionally stored in separate memories.

[0005] When such a UMA is adopted, various processing units access the UM. That is, memory accesses from processing units having different localities may access the same UM.

For example, considering a system that stores a video input image in a UM and uses the image as a texture for texture mapping, or performs a process such as applying a filter to the image, each of these processes is performed in a memory. Each has its own locality for access.

FIG. 20 is a diagram for explaining the locality of these processes.

As shown in FIG. 1, in the video input, pixel data is sent in order from the upper left to the lower right. That is, the video input unit has one-dimensional (linear) locality with respect to memory access.

On the other hand, in the texture mapping, the pixel data stored in the UM is accessed in all directions such as vertical, horizontal and diagonal according to the shape of the mounting destination. Has locality. Further, even in a filtering process for performing filtering on an image stored in the UM, generally, several pixels around a pixel of interest are weighted and averaged, and thus have two-dimensional locality with respect to memory access.

In this case, both the processing unit having one-dimensional (linear) locality and the processing unit having two-dimensional locality access the UM.

For processing having linear locality, it is desirable that addresses be managed linearly and linear access and linear caching (buffering) can be performed. In addition, for processing having two-dimensional locality, it is desirable that addresses are managed in a tile format, and tile-type access and tile-type caching can be performed.

[0012]

In the technique described in the above publication, addresses are linearly managed in a memory space in which data having linear locality such as CPU instructions is stored. That is, as shown in FIG. 21, whether to perform linear access (and linear caching) or tile access (and tile caching)
It is determined by the address area to be accessed, and it is not possible to perform both linear access and tile access to the same address space.

For example, the tile-type address area is accessible only by tile-type access on the assumption that the next access is likely to be performed in all two-dimensional directions. In this case, a process having two-dimensional locality, such as texture mapping, enables efficient memory access and can be expected to improve the cache hit rate. However, even in the video input processing in which the pixel on the right is accessed next, the tile-type address area must be accessed by tile-type access, and the access efficiency of the processing unit having linear locality is low. Will drop.

An object of the present invention is to provide an information processing system which enables memory access suitable for each locality even when processing units having different localities (locality) coexist. .

[0015]

A first information processing system according to the present invention comprises a memory composed of a plurality of modules, a processing unit for accessing the memory, and a processing unit issued from the processing unit. An address conversion unit that converts an address of the memory into an individual address for each module according to an access mode, and a data aligner unit that rearranges data read and written to the memory according to the access mode and the address. I do.

Further, the second information processing system according to the present invention comprises a memory having N modules capable of reading and writing data in a data unit having a specific size, and an N number of modules between the memory and the memory. A processing unit for reading and writing data consisting of the data unit described above, and a memory interface unit for accessing a memory in response to an access request from the processing unit. The memory interface unit includes: a module that stores each data unit according to an access mode such that each of the N data units received from the processing unit is stored in a different module; The storage position is determined.

Further, a third information processing system according to the present invention provides a memory having N modules capable of reading and writing data in a data unit having a specific size, and a memory having N modules. A processing unit for reading and writing data consisting of a plurality of data units, and an address conversion unit for performing an address conversion to an individual address for each module according to an access mode, the address issued when the processing unit accesses the memory; When data is exchanged between the processing unit and the memory, a data aligner unit that rearranges data units constituting the data according to an access mode is provided.

In this case, in the address conversion unit, in a two-dimensional array composed of N × N data units, all data units having the same X coordinate are stored in different modules and have the same Y coordinate. Data units are stored in different modules,
Address conversion may be performed, and the data aligner may rearrange data units according to the address conversion performed by the address converter.

Further, the fourth information processing system according to the present invention comprises a processing unit having different localities, a unified memory commonly accessed by each processing unit, and a temporary storage of data used by each processing unit. A cache unit for storing data, a memory interface unit for performing memory access to a unified memory in response to an access request from each processing unit, and a unified memory according to an access mode notified from each processing unit. An address conversion unit for converting an address for accessing the memory;
It is characterized by comprising a unified memory and a data aligner for rearranging data to be exchanged according to the access mode.

In this case, the unified memory may be composed of a plurality of modules, and the address translator may be provided in each of the modules. Further, the address conversion unit may be provided in the memory interface unit.

Further, a fifth information processing system according to the present invention comprises a processing unit having different localities, a unified memory commonly accessed by each processing unit, and a temporary storage of data used by each processing unit. A cache unit for storing data, a memory interface unit for performing memory access to a unified memory in response to an access request from each processing unit, and a unified memory according to an access mode notified from each processing unit. An address conversion unit for converting an address for accessing the memory;
A data selection unit that is located between the processing unit and the cache unit and selects data to be read by the processing unit according to the access mode.

Note that the information processing system according to the present invention
For example, it is implemented as a normal computer system or as a one-chip system LSI.

The processing unit includes, for example, a CPU,
A video input unit, a video output unit, a texture mapping unit, a filtering unit, and the like correspond.

[0024]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 shows a system LSI to which the present invention is applied.
FIG. 3 is a diagram showing the configuration of FIG. This system LSI is, for example,
It is composed of one chip.

As shown in FIG.
CPU 100, video input unit 110, texture mapping unit / filtering unit 120, connector unit 1
01, 111, 121 and the memory interface unit 13
0 and a unified memory (hereinafter referred to as UM) 140
And

The CPU 100 is connected to the connector unit 101, the video input unit 110 is connected to the connector unit 111, and the texture mapping unit / filtering unit 12
0 is connected to the connector 121.

The connectors 101, 111, 121 and the memory interface 130 are connected to the memory bus 150, respectively. Here, the memory bus 15
The data width of 0 is 512 bits. The access mode selection signal output from each of the connector units 101, 111, and 121 is input to the memory interface unit 130.

Further, the memory interface unit 130
It is also connected to UM140.

The CPU 100, the video input unit 110, and the texture mapping / filtering unit 120 are processing units that perform different processes. Since both the texture mapping unit and the filtering unit have two-dimensional locality, they are shown as one processing unit as a representative.

The connector units 101, 111, and 121 are functional blocks that provide an interface between each processing unit and the memory bus 150. The connector unit 101 includes a cache 102, the connector unit 111 includes a write buffer (hereinafter, referred to as a W buffer) 112, and the connector unit 121 includes a cache 122.

The cache 102 is a high-speed memory for holding data recently accessed by the CPU 100. For example, when the CPU 100 performs a memory read, if the data to be accessed is in the cache 102, the data is passed to the CPU 100. On the other hand, if the data to be accessed is not in the cache 102, the UM 14 via the memory bus 150 and the memory interface unit 130.
From 0, data of one cache line including data to be accessed (here, 512-byte data) is read, and the data to be accessed is passed to the CPU 100, and the read cache line data is stored in the cache 102. Will be retained.

The W buffer 112 is used for the video input unit 110
For example, data input in units of pixels are sequentially stored, and when the data is full, the data in the W buffer 112 is transferred to the memory bus 150 and the memory interface unit 1.
30 and is written to the UM 140. W buffer 11
Reference numeral 2 denotes a buffer for absorbing the difference between the data bus width between the video input unit 110 and the connector unit 111 and the data bus width of the memory bus 150 and reducing the number of times the memory bus 150 is used. That is, the video input data is
In the case of storing the data in the M140, if the memory access is performed for each pixel data, the frequency of use of the memory bus 150 becomes extremely high. (Here, 5
Write to the UM 140.

For example, when there is a data access request in pixel units from the texture mapping unit / filtering unit 120, if the data to be accessed has already been read into the cache 122,
The access target data in the cache 122 is passed to the texture mapping unit / filtering unit 120. on the other hand,
If the access target data is not on the cache 122,
Memory bus 150 and memory interface unit 130
To access the UM 140 via the, read out one cache line of data (here, 512-bit data) including the data to be accessed, pass the requested data to the texture mapping unit / filtering unit 120, and , And holds the read cache line data.

The memory interface unit arbitrates access requests from the processing units 100, 110, and 120, and among the processing units that issue memory access requests, a processing unit that can actually use the memory bus 150. To determine.

As a result of the arbitration, the processing unit permitted to access sends an address and an access mode selection signal to the memory interface unit 130 through the memory bus 150,
Send and receive data.

The memory interface unit 130 operates the UM 14 at a predetermined timing in accordance with the received address and the like.
0, and read / write data from / to the UM 140.

The memory interface unit 130 includes an address conversion unit 131 and a data aligner unit 132.

The address conversion unit 131 is connected to the memory bus 15
0 to the address received by the memory interface unit 130 based on the access mode selection signal.
Convert to a physical address of 0. The memory interface unit 130 exchanges data with the UM 140 using the physical address.

When the memory interface unit 130 is connected to the UM 14
When exchanging data with 0, the data aligner unit 132
Performs a conversion between a data array on the memory bus 150 and a data array on the UM 140 by rearranging the data in a predetermined data unit as necessary.

Next, the configuration of the UM 140 will be described. Here, a case where the UM 140 is configured using a DRAM will be described.

FIG. 2 is a diagram showing the configuration of the UM 140.

As shown in the figure, the UM 140 is composed of 2 ^LM independent modules 500. For example, in the case of output, 2 ^LW bytes of data are output from each module 500, and 2 ^LM output data from each module 500 are collected, and 2 ^{(LW + LM)} output from the UM 140 as a whole Construct byte data.

Each module 500 includes a bank selector 510 and 2 ^LB independent banks 520. The bank selector 510 selects one of the 2 ^LB banks as the output of the module 500 based on the LB bit bank address (B address).

Each bank 520 includes a row selector 5
21, a column selector 522, and a sense amplifier 523
And 2 ^LR × 2 ^LC memory cells 524 (one memory cell is 2 ^LW bytes).

The row selector 521 selects one row data from 2 ^LR row data (2 ^{(LC + LW)} byte data) based on the LR bit row address (R address). , To the sense amplifier 523.

The sense amplifier 523 is connected to the row selector 52
Detects 2 ^{(LC + LW)} byte row data output from 1
Amplify and retain.

The column selector 522 detects the sense amplifier 5 based on the LC bit column address (C address).
23, one of the 2 ^LC memory cell data stored in the memory cell 23 is selected, and as an output from the bank 520, 2 ^LW
Output byte data.

In the UM 140 shown in FIG. 2, the outputs from all the modules 500 are output in parallel to the outside of the UM 140. However, a selector which receives the output from each module 500 as an input is further provided, and is separately supplied. Only the outputs from some of the modules may be output from the UM 140 based on the module address. For example, when there are four modules 0 to 3 in the UM 140, when the 1-bit module address (M address) is “0”, the outputs of the modules 0 and 1 are output,
When the one-bit module address is “1”, the outputs of the modules 2 and 3 may be output.

Next, the operation of the UM 140 will be described. This is the same operation as a general multi-bank, multi-module synchronous DRAM.

Addresses such as a bank address, a row address, and a column address and commands representing read (read) and write (write) are input from the memory interface unit 130 to the UM 140. In the case of writing, data to be written is also input.

First, the operation at the time of reading will be described.

In each bank 520, when the bank address is specified by the bank address, 2 corresponding to the row address
^{The (LC + LW)} byte row data is read out to the sense amplifier 523.

The row data read by the sense amplifier 523 is input to the column selector 522. The column selector 522 selects one 2 ^LW byte data from the row data read by the sense amplifier 523 based on the column address, and outputs the data from the bank 520.

The data of 2 ^LW bytes output from each bank 520 is input to the bank selector 510. The bank selector 510 determines 2 ^LB based on the bank address.
One of the bank outputs is selected and output as a module output.

As described above, 2 ^LM 2 ^LW byte data output from each module 500, that is, a total of 2 ^{(LM + LW)}
The bytes are output from UM140. The data read from the UM 140 is passed to the memory interface unit 130.

To read the row data to the sense amplifier 523, a predetermined number of cycles (for example, 6 cycles)
Is required, but when accessing data that has already been read to the sense amplifier 523, the memory cell 524
Since it is not necessary to read the row data from, access can be made at high speed (for example, in two cycles). Therefore, it is desirable that data having high locality be read out to the sense amplifier 523 at the same time.

Next, the operation at the time of writing will be described.

In each bank 520, when the bank address is designated by the bank address, 2 ^{(LC + LW)} corresponding to the row address
The byte row data is sent to the sense amplifier 523.

The write data input to the UM 140 is
Of the row data input to each module 500 and located on the sense amplifier 123 of the bank specified by the bank address, 2 ^LW bytes of data selected by the column address are rewritten by the write data.

In the case of writing, as in the case of reading,
Since data that has already been read to the sense amplifier 123 of each bank can be accessed at high speed (for example, in one cycle), it is desirable that data with high locality be read to the sense amplifier at the same time.

In the following, LM =
Consider the case of 2, LB = 4, LR = 8, LC = 4, LW = 4. That is, the UM 140 includes four (= 2 ² ) independent modules 500. Also, each module 500
There are 16 (= 2 ⁴ ) banks 520, and each bank 52
0 is provided with 2 ⁸ × 2 ⁴ memory cells 524. Also,
Each memory cell 524 stores a 2 ⁴ bytes of data. In this case, from each module 500,
Since 16 (= 2 ⁴ ) bytes of data are output, UM
The output from 140 is 4 × 16 bytes = 64 bytes (=
512 bits).

Next, an image handled in this embodiment will be described.

FIG. 3 is a diagram showing 512 × 5 pixels handled in this embodiment.
FIG. 2 is a diagram illustrating a hierarchical structure of a 12-pixel size image.

The image data is stored on the memory in a form corresponding to the hierarchical division. Actually, this hierarchy corresponds to the address on the memory, and this correspondence is called address mapping.

As shown in the figure, in the present embodiment, one image of 512 × 512 pixels is composed of 8 × 32 blocks. Also, each block is
It is assumed that it is composed of 4 × 4 cells.

Each cell is composed of 16 × 4 pixels. Further, each pixel has R (red), G (green), B
(Blue) and α (transparency) are composed of four components of 1 byte each. That is, one pixel is composed of data of 4 bytes = 32 bits. Therefore, one image of 512 × 512 pixels is composed of 1 Mbytes of data.

Next, the image data as described above is stored in the UM1
The address mapping when the data is stored in the storage 40 will be described.

FIG. 4 is a diagram showing an example of address mapping when image data is stored in the UM 140.

Here, it is assumed that a 4-Mbyte memory area (hereinafter, referred to as an image area) of the UM 140 is used for storing image data. In this case, the image area is
It is accessed by a 22-bit address.

In the example of FIG. 4, the 22-bit address, the 2-bit module address (M [1: 0]), the 4-bit bank address (B [3: 0]) in the UM 140,
8-bit row address (R [7: 0]), 4-bit column address (C [3: 0]), 4-bit byte address (W [3:
0]).

As described above, since one image of 512 × 512 pixels is 1 Mbyte, the first two bits represent the start address of the image to be accessed in the image area. These two bits are used as B [3] and B [2]. Here, the description B [2] represents the second bit of the bank address. However, the least significant bit of B is B [0].

The next 8 bits indicate the start address of the block to be accessed in the image specified by the most significant 2 bits. Here, the upper 5 bits are the vertical address Y of the image, and the lower 3 bits are the horizontal address X of the image. These 8 bits correspond to the row address R [7] to R
Used as [0].

Similarly, the next four bits indicate the head address of the cell to be accessed in the designated block. Here, the upper two bits are the vertical address Y
The lower two bits are a horizontal address X. These 4 bits are used as B [1], C [3], B [0], and C [2].

The last 8 bits are the address inside the designated cell. Of these, the upper 2 bits are the head address of the line (the unit of 64-byte data output from the UM 140) in the cell. The remaining 6 bits are byte addresses in the line. However, since data is accessed for the UM 140 in line units,
This 6-bit in-line byte address is UM140
You do not need to enter

Next, the address assignment of the pixels in the cell at the time of the address mapping shown in FIG. 4 will be specifically described.

FIG. 5 is a diagram for explaining a storage method when image data in one cell (16 × 4 pixels) is stored in a memory.

As shown in the figure, each pixel in the cell has:
A two-dimensional address is assigned to each group of four pixels in the horizontal direction (X direction). Here, the first coordinate is represented by Y and the second coordinate is represented by X in the form of (Y, X). Hereinafter, a set of four pixels to which the two-dimensional address is assigned is referred to as a pack.

The packs (0,0) to (3,3) are (0,0,0)
0) to (0,3), (1,0) to (1,3), (2,
0) to (2,3), (3,0) to (3,3)
Assuming that the packs are stored in M140, four packs having the same X coordinate are stored in the same module (module address: X) in the address assignment shown in FIG.

That is, packs (0, 0), (1,
0), (2,0), (3,0) are stored in module 0, and packs (0,1), (1,1), (2,1),
(3, 1) is stored in the module 1 and the pack (0,
2), (1,2), (2,2), (3,2) are stored in the module 2, and packs (0,3), (1,3),
(2, 3) and (3, 3) are stored in the module 3.

At this time, four packs having the same Y coordinate (for example, packs (0, 0), (0, 1), (0,
Since (2) and (0, 3)) are stored in separate modules 500, 16 pixels arranged side by side can be accessed simultaneously. However, as described above, four packs having the same X coordinate (for example, packs (0, 0), (1,
0), (2,0), (3,0)) are the same module 5
00, the 4 × 4 pixels cannot be accessed simultaneously. That is, in this case, it is suitable for linear access but not suitable for tile access.

On the other hand, packs (0,0) to (3,3)
(0,0) to (3,0), (0,1) to (3,3),
Assuming that the data are stored in the UM 140 in the order of (0, 2) to (3, 2) and (0, 3) to (3, 3), the same Y coordinate is assigned in the address assignment shown in FIG. The four packs are stored in the same module (module address: Y). In this case, it is suitable for tile access but not for linear access.

To make it suitable for both linear access and tile access, "packs having the same X coordinate in the same cell are all stored in different modules and have the same Y coordinate. The pack is
All must be stored in different modules. "

FIG. 6 is a diagram showing a storage method satisfying such a condition. In the figure, four packs arranged in the vertical direction (Y direction) are stored in the same module.
That is, packs (0,0), (1,3), (2,
2) and (3,1) are stored in module 0, and packs (0,1), (1,0), (2,3), (3,2) are
Packs (0, 2), (1,
1), (2,0), (3,3) are stored in module 2 and packed (0,3), (1,2), (2,1),
(3, 0) is stored in the module 3.

In FIG. 6, the packs on the 0th row (Y = 0) have the X coordinates 0, 1, 2, 3, while the packs on the 1st row (Y = 1) have the X coordinates. The coordinates are shifted by 0, 1, 2, 3 by one, that is, 3, 0, 1, 2, and 3. Similarly, the second and third rows are further arranged one by one.

When packs are stored in this manner, "packs having the same X coordinate in the same cell are all stored in different modules, and packs having the same Y coordinate are all stored in different modules. Satisfies the condition, and can achieve both linear access and tile access.

FIG. 7 is a diagram showing address allocation when storing a pack in such a form.

As shown in the figure, although the address assignment is almost the same as that of FIG. 4, the line selection address in the cell is not directly a column address, and a new 2 is selected.
The difference is that bit line selection addresses L [1] and L [0] are replaced. This is because it is necessary to specify a different column address for each module when selecting a line.

Therefore, the address shown in FIG. 7 needs to be converted before the memory cell is finally accessed. Further, since the address conversion method differs depending on whether the access mode is the linear access mode or the tile access mode, it is necessary to consider the access mode selection signal when performing the address conversion. The address conversion unit 131 performs this address conversion.

Further, since the data stored in such a shifted form is different from the data arrangement at the time of access by the processing unit, the data read from the UM 140 must be rearranged before the data is passed to the processing unit. There is a need to. The data aligner 132 rearranges the data.

Next, a method of the address conversion and the data rearrangement will be described.

FIG. 8 is a diagram showing the correspondence between the address conversion result and the data alignment for the input address (line selection address) when the access mode is the linear access mode.

In the table shown in FIG. 8, the first column shows the value of the line selection address, the second column shows the module number (module address), and the column address (third column) , The coordinates of the packs stored in each module of the UM 140 (fourth column), the coordinates of the packs (fifth column) when the original pixels are rearranged so as to be arranged, and the arrangement of the packs are rearranged correctly. (The sixth column).

The symbols of S1 and S2 in the sixth column represent a specific substitution. S1 indicates a cyclic permutation for converting an array (0,1,2,3) into an array (1,2,3,0), and S2 indicates an array (0,1,2,3). Into a sequence (2,3,0,1)
That is, a substitution S1 * S1 obtained by performing the substitution S1 twice is shown. Also, 1 indicates an identity substitution that does not change the sequence.

Focusing on the address conversion in FIG.
The column address [C1, C0] matches the value of the line selection address.

The replacement shown in the figure is a replacement at the time of reading, that is, when rearranging from the state stored in each module 500 to the correct state (as in the original pixel array). At the time of writing, the reverse substitution in the sixth column may be performed. The reverse substitution of 1 is 1, the reverse substitution of S1 is S1 * S2, S2
Is S2, and the reverse substitution of S1 * S2 is S1.

FIG. 9 is a diagram showing the correspondence between the address conversion result and the data alignment for the input address (line selection address) when the access mode is the tile access mode.

The structure of the table shown in FIG. 9 is the same as the structure of the table shown in FIG.
The column indicates the module number. For these combinations, the column address (third column), the coordinates of the packs stored in each module of the UM 140 (fourth column), and the original pixels of the image are arranged. In this case, the coordinates of the packs after the rearrangement (the fifth column) and the permutation for correctly rearranging the packs (the sixth column) are shown.

Looking at the address conversion in FIG.
The column address [C1, C0] is a value obtained by subtracting the value of the line selection address from the module number by a 2-bit operation.

The sixth column in FIGS. 8 and 9 are all replaced by the same data. In this case, the data aligner 132
Does not require an access mode selection signal.

However, in general, "the same X in the cell
All packs with coordinates are stored in different modules, and packs with the same Y coordinate are all stored in different modules. " In such a case, the data aligner unit 132 performs different replacement according to the access mode selection signal.

Next, a description will be given of a connection form between the address conversion unit 131 for performing the above-described address conversion and each module 500 in the UM 140.

FIG. 10 shows the configuration of the memory interface unit 130.
FIG. 6 is a diagram showing a connection form between an address conversion unit 131 in the UM 140 and each module 500 in the UM 140.

As shown in FIG.
Thus, the upper two bits [C3, C2] of the column address are commonly supplied to each module 500. The lower two bits [C1, C0] of the column address are individually supplied to each module 500.

An address and an access mode selection signal are input to the memory interface unit 130 from the processing unit permitted to access through the memory bus 150. In the figure, the upper two bits [C3, C2] of the column address and the two bits [L1, L0] of the line selection address among the addresses passed to the memory interface unit 130.
Only is shown. Addresses not shown in the figure are broadcast to all the modules 500 at a predetermined timing as a bank address and a row address.

The memory interface unit 130 broadcasts the upper two bits of the column address to each module 500 among the input addresses. Further, based on the line selection address 2 bits and the access mode selection signal, as shown in FIGS.
Generate the lower two bits of the column address. Since the lower two bits of this column address are different for each module 500, they are individually distributed to each module 500. Each module 500 selects data to be output from the sense amplifier 123 according to the 4-bit column address.

In the embodiment described above, the address conversion unit 131 is provided in the memory interface unit 130.
00 may be provided.

FIG. 11 is a diagram showing an example in which an address conversion unit 131 is provided in each module 500. As shown in the figure, each module 500 includes an address conversion unit 131. The address conversion unit 131 includes a module address register (Mreg) 1400
g1400 is a register that stores the module address (module number) of each module. For example, “0” is set to Mreg 1400 of module 0, “1” is set to Mreg 1400 of module 1, and “2” is set to Mreg 1400 of module 2.
Is set, and the Mreg 1400 of the module 3 includes:
“3” is set. The value of Mreg 1400 may be fixed or variable.

In the case of FIG. 11, the memory interface unit 1
30 broadcasts the address received via the memory bus 150 to all the modules 500 at a predetermined timing.

Address converter 13 of each module 500
1 generates the lower two bits of the column address based on the module address stored in each Mreg 1400 and the line selection address and access mode selection signal supplied from the memory interface unit 130.

Note that the Mreg 1400 sends each module 500 to the address conversion unit 131 in each module 500.
Is provided to notify the module address (module number) of each module.
A signal indicating a module address of 00
00 may be supplied to the address conversion unit 131.

Next, the configuration of the data aligner 132 will be described.

FIG. 12 is a diagram showing a configuration example of the data aligner unit 132.

Here, for simplicity, only the data aligner 132 in the memory read direction is shown. The data aligner in the memory writing direction can also be made by overlapping two stages of cyclic permutation in the same manner as in the memory reading direction.

As shown in FIG. 12A, the data aligner unit 132 includes an S1 unit 1500 and an S2 unit 1510. The data aligner unit 132 outputs the line selection signal L
According to 0 and L1, the operation is performed as shown in FIGS. The S1 unit 1500 and the S2 unit 1510 are units that perform the replacements S1 and S2 shown in the sixth column of FIGS. 8 and 9, respectively.

As shown in FIG. 12B, the S1 unit 150
0 includes selectors 1501 to 1504. The selectors 1501 to 1504 select the input of the selector with the suffix of 0 or 1 corresponding to “0” or “1” of the selection signal L0 (line selection address L [0]). Output. That is, when L0 = “1”, the S1 unit 1500 cyclically replaces the arrangement of 3,0,1,2 with 0,1,2,3.

As shown in FIG. 12C, the S2 unit 1510 includes selectors 1511 to 1514. The selectors 1511 to 1514 select the input of the selector with the suffix of 0 or 1 corresponding to “0” or “1” of the selection signal L1 (line selection address L [1]). Output. That is, the S2 unit 1510 calculates L1 =
When “1”, the sequence of 2,3,0,1 is changed to 0,1,2,2
Cyclic substitution to 3.

One line of data rearranged as appropriate by the data aligner 132 having the above configuration is
It is stored in the caches 102, 122 and the like.

FIG. 13 is a diagram showing the arrangement of packs that fall into one line of the cache.

FIG. 13A shows linear caching.
This represents the contents of the cache when the line selection address is Y.

FIG. 13B shows tile caching.
This represents the contents of the cache when the line selection address is X.

Next, a method of storing image data different from the method shown in FIG. 6 will be described.

FIG. 14 is a diagram showing another image storage method in one embodiment of the present invention. In the storage method shown in FIG. 14, four packs having the same Y coordinate, that is, linear access for simultaneously accessing 16 pixels arranged in a row, and four packs having the same X coordinate, that is, 4 × 4 pixels In addition to the tile access for simultaneously accessing the image data, a mode for simultaneously accessing a 2 × 2 pack, that is, an area of 8 × 2 pixels is supported. Hereinafter, this access mode is referred to as an 8 × 2 access mode.

In the 8 × 2 access mode, for example, packs (0,0), (0,1), (1,0),
(1, 1) can be accessed simultaneously.

In the figure, four packs arranged in the vertical direction (Y direction) are stored in the same module. That is, packs (0,0), (1,2), (2,1),
(3,3) is stored in module 0 and pack (0,3)
1), (1,3), (2,0), (3,2) are stored in the module 1 and packed (0,2), (1,0),
(2,3) and (3,1) are stored in module 2,
Packs (0,3), (1,1), (2,2), (3,
0) is stored in module 3.

FIGS. 15 to 17 are diagrams showing a method of address conversion and data rearrangement in this case.

The structure of the tables shown in FIGS. 15 to 17 is the same as the structure of the tables shown in FIGS.

FIG. 15 is a diagram showing a case where the access mode is the linear access mode.

FIG. 16 is a diagram showing a case where the access mode is the tile access mode.

FIG. 17 shows a case where the access mode is the 8 × 2 access mode.

Note that “0” is set in the replacement column in FIGS.
There are descriptions such as “⇔2” and “2⇔3”, which are permutations in (0, 1, 2, 3) that exchange 0 and 2, and 2 and 3, respectively, ie, Replacement of (0,1,2,3) with (2,1,0,3) and (0,1,2,3)
3) represents the substitution of (0, 1, 3, 2).

Next, another embodiment of the present invention will be described.

FIG. 18 is a diagram showing the configuration of another system LSI to which the present invention is applied.

As shown in the figure, the present system LSI
The data aligner unit 132 is connected to the connector units 101 and 11.
1 and 121 are different from the system LSI shown in FIG.

When the data width between each processing unit and the connector unit is equal to or smaller than the data width of the pack, a pack containing necessary data may be selected and passed to the processing unit (in the case of reading), so that the data aligner unit 132 In effect, it becomes a selector, and the process of rearranging the data becomes unnecessary. Therefore, at this time, the system can be configured with a smaller physical quantity than placing the data aligner unit 132 in the memory interface unit 130. In this case, the packs are stored in the caches 102 and 122, for example, as shown in FIGS.
Are stored in the arrangement shown in the fourth column.

Further, the address conversion unit 131 may be included in each of the connector units 101, 111, and 121. In this case, each processing unit is the memory interface unit 1
Some of the addresses sent to 30 will be different for each module. In other words, for each part of the address, a different address is passed from module to module to the memory interface 130. The memory interface unit 130 sends an address different for each module among the addresses passed from each processing unit individually for each module, and broadcasts the remaining addresses to all modules.

Finally, an example of using the memory area according to the present invention in a system in which a general application program operates will be described.

FIG. 19 is a diagram showing a usage example of the memory area of the UM 140 to which the present invention is applied.

In this case, the UM 140 is divided into an area 1900 to which an application running on the CPU 100 directly accesses, and an image area 1910 for storing display images, textures, and the like. Then, general applications register images as textures,
When performing video input, be sure to use a standard library (collection of functions) to perform these processes.
Only the drivers of these libraries (substances of the library functions) are allowed to access the image area 1910. In this case, the driver operates the image area 1910
Is accessed in accordance with a storage method that allows linear access and tile access as shown in FIGS.

In this way, when a new system is provided, by providing a library driver together, a different access method (for example, a linear access method) can be used in the image area 1910 without changing an application program or a compiler. And tile access).

In the case of handling audio and the like in addition to images, in a system where a general application program operates, an area accessed by an application running on the CPU and resources other than the CPU such as images and audio access. By separating the area from the area, it is possible to achieve both linear access (linear caching) and tile access (tile caching) in a specific area without changing an application program or a compiler in an area accessed by resources other than the CPU. Can be.

[0142]

As described above in detail, according to the present invention, it is possible to access the same address space by different access methods such as linear access and tile access. Regarding the above, even when processing units having different localities (locality) coexist, memory access suitable for each locality can be performed.

As a result, even when processing units having different localities (localities) coexist, it is possible to prevent a decrease in the efficiency of accessing the memory. Also, if each processing unit has a cache, an improvement in hit rate can be expected,
The processing speed can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram of a system LSI according to the present invention.

FIG. 2 is a block diagram showing a configuration of a unified memory.

FIG. 3 is a diagram illustrating a hierarchical structure of an image.

FIG. 4 is a diagram showing an example of address mapping when storing image data in a memory.

FIG. 5 is a diagram illustrating an example of a storage method when an image is stored in a memory.

FIG. 6 is a diagram illustrating an image storage method according to the present invention.

FIG. 7 is a diagram showing address mapping when image data is stored by the image storage method according to the present invention.

FIG. 8 is a diagram showing correspondence between an address conversion result and data alignment for an input address in a linear access mode.

FIG. 9 is a diagram showing correspondence between an address conversion result and data alignment for an input address in a tile access mode.

FIG. 10 is a diagram showing a connection form between a memory interface unit 130 and each module 500.

FIG. 11 shows an address conversion unit 13 in each module 500.
It is a figure showing the example which put 1.

FIG. 12 is a block diagram illustrating a configuration of a data aligner unit.

FIG. 13 is a diagram showing an arrangement of packs in a cache.

FIG. 14 is a diagram illustrating another image storage method according to the present invention.

FIG. 15 is a diagram showing correspondence between an address conversion result and data alignment for an input address in a linear access mode.

FIG. 16 is a diagram showing a correspondence between an address conversion result and a data alignment for an input address in a tile access mode.

FIG. 17 is a diagram showing correspondence between an address conversion result and data alignment for an input address in an 8 × 2 access mode.

FIG. 18 is a block diagram of another system LSI according to the present invention.

FIG. 19 is a diagram illustrating an example of using a UM in a system in which a general application program operates.

FIG. 20 is a diagram illustrating the concept of locality.

FIG. 21 is a diagram illustrating an overview of memory access according to a conventional method.

[Explanation of symbols]

 Reference Signs List 100 CPU 110 Video input unit 120 Texture mapping unit / filtering unit 101, 111, 121 Connector unit 130 Memory interface unit 131 Address conversion unit 132 Data aligner unit 140 Unified memory (UM)

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Shigeru Matsuo 7-1-1, Omika-cho, Hitachi City, Ibaraki Prefecture Inside Hitachi Research Laboratory, Hitachi, Ltd. (72) Inventor Tetsuya Shimomura 7-1-1, Omika-cho, Hitachi City, Ibaraki Prefecture No. 1 Hitachi, Ltd., Hitachi Research Laboratory (72) Inventor Manabu Shiro 7-1-1, Omikacho, Hitachi City, Ibaraki Prefecture Hitachi, Ltd., Hitachi Research Laboratory (72) Inventor Jun Sato, Kodaira City, Tokyo 5-20-1, Mizumotocho F-term in Hitachi Semiconductor Group, Ltd. (Reference) 5B047 AB04 EA09 EB01 EB06 EB13 5B060 AA13 AC13 GA06 GA11 GA16 MM13

Claims (7)

[Claims] A memory configured by a plurality of modules; a processing unit that accesses the memory; and an address of the memory issued from the processing unit. An information processing system, comprising: an address conversion unit that converts data into data and a data aligner that rearranges data read and written in a memory according to an access mode and an address. 2. A process for reading and writing data consisting of N data units between a memory including N modules capable of reading and writing data in a data unit having a specific size, and the memory. And a memory interface unit that accesses a memory in response to an access request from the processing unit. The memory interface unit is different in each of the N data units received from the processing unit. A module for storing each data unit according to the access mode so as to be stored in the module,
An information processing system, wherein a storage position in each module is determined. 3. A process for reading and writing data consisting of N data units between a memory having N modules capable of reading and writing data in a data unit having a specific size, and the memory. And an address translation unit that translates an address issued when the processing unit accesses the memory into an individual address for each module in accordance with the access mode, and exchanges data between the processing unit and the memory. An information processing system, comprising: a data aligner unit for rearranging the data units constituting the data according to an access mode. 4. The data conversion unit according to claim 1, wherein in a two-dimensional array of N × N data units, all data units having the same X coordinate are stored in different modules and have the same Y coordinate. 4. The device according to claim 3, wherein the address conversion unit performs an address conversion so that all the data are stored in different modules, and the data aligner unit rearranges data units according to the address conversion performed by the address conversion unit. An information processing system according to claim 1. 5. A processing unit having different localities, a unified memory commonly accessed by each processing unit, a cache unit for temporarily storing data used by each processing unit, and each processing unit A memory interface unit that accesses the unified memory in response to an access request from the server, and an address converter that translates the address for accessing the unified memory according to the access mode notified from each processing unit And a data aligner unit for rearranging data exchanged with the unified memory according to the access mode. 6. The information processing system according to claim 5, wherein the unified memory includes a plurality of modules, and the address conversion unit is provided in each of the modules. 7. A processing unit having different localities, a unified memory commonly accessed by each processing unit, a cache unit for temporarily storing data used by each processing unit, and each processing unit A memory interface unit that accesses the unified memory in response to an access request from the server, and an address converter that translates the address for accessing the unified memory according to the access mode notified from each processing unit An information processing system, which is located between the processing unit and the cache unit and that selects data to be read by the processing unit in accordance with the access mode. .