JP2004006927A5 - - Google Patents
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- Publication number
- JP2004006927A5 JP2004006927A5 JP2003188072A JP2003188072A JP2004006927A5 JP 2004006927 A5 JP2004006927 A5 JP 2004006927A5 JP 2003188072 A JP2003188072 A JP 2003188072A JP 2003188072 A JP2003188072 A JP 2003188072A JP 2004006927 A5 JP2004006927 A5 JP 2004006927A5
- Authority
- JP
- Japan
- Prior art keywords
- pad
- solder
- solder bump
- height
- wiring board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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Description
【００１６】
【課題を解決するための手段】
請求項１の発明は、 配線基板のパッドの径が１５０μｍ以下で、かつ該パッド上に形成された半田バンプの高さが平均値で７０μｍ以下で、その高さのバラツキが該平均値の±２０％の範囲内であることを特徴とする。
本発明では、配線基板のパッドの径が１５０μｍ以下で、半田バンプの高さが平均値で７０μｍ以下と小さい半田バンプの場合でも、その高さのバラツキが平均値の±２０％の範囲内と少ないので、例えばフリップチップとの接合性が高くなる。
請求項２の発明は、前記パッドが、同一高さの半田バンプを形成するのに異なる量の半田を要するパッドが混在しているパッド群であることを特徴とする。
配線基板のパッドが、同一高さの半田バンプを形成するのに異なる量の半田を要するパッドが混在しているパッド群（例えば図９（ａ）に示す様な、パッドの形状又はサイズ（径等）が異なるパッドが混在するパッド群）であることを特徴とする場合には、フリップチップ等との接合性が悪化しがちであるが、高さバラツキが少ないので、良好な接合性を得ることができる。
請求項３の発明は、前記パッドが、ビア部パッド及び非ビア部パッドであることを特徴とする（［００８６］参照）。
尚、前記配線基板の製造に用いることができる半田バンプ形成用メタルマスクについて簡単に説明する。
半田バンプを形成するために、配線基板に対して半田ペーストを印刷する際に用いられるメタルマスクとして、形成する半田バンプに対応したパターン穴の縦断面形状が、開口端の径より中央部の径が大きい略樽形状のものを用いることができる。
[0016]
[Means for Solving the Problems]
According to the first aspect of the present invention, the diameter of the pad of the wiring substrate is 150 μm or less, and the height of the solder bump formed on the pad is 70 μm or less in average value, and the variation of the height is ±± of the average value. It is characterized by being in the range of 20%.
In the present invention, even in the case of a solder bump in which the diameter of the pad of the wiring substrate is 150 μm or less and the height of the solder bumps is as small as 70 μm in average, the height variation is within ± 20% of the average value. As the amount is small, for example, the bondability with the flip chip is enhanced.
The invention according to claim 2 is characterized in that the pad is a pad group in which pads requiring different amounts of solder to form solder bumps of the same height are mixed.
A pad group in which pads on the wiring substrate require different amounts of solder to form solder bumps of the same height (for example, the shape or size (diameter of the pad as shown in FIG. 9A) In the case of a pad group in which pads different from each other are mixed) , the bonding property to a flip chip or the like tends to deteriorate, but since the height variation is small, good bonding property can be obtained. be able to.
The invention of claim 3 is characterized in that the pad is a via pad and a non-via pad (see [0086]).
A metal mask for solder bump formation that can be used for manufacturing the wiring substrate will be briefly described.
The vertical cross-sectional shape of the pattern hole corresponding to the solder bump to be formed is a diameter of the central portion from the diameter of the opening end as a metal mask used when printing solder paste on the wiring substrate to form the solder bump A substantially barrel-shaped one can be used.
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2003188072A JP2004006927A (en) | 2003-06-30 | 2003-06-30 | Wiring board with solder bump, method of manufacturing the same, and metal mask for forming solder bump |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2003188072A JP2004006927A (en) | 2003-06-30 | 2003-06-30 | Wiring board with solder bump, method of manufacturing the same, and metal mask for forming solder bump |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11135197A Division JP3462363B2 (en) | 1997-04-28 | 1997-04-28 | Method of manufacturing wiring board having solder bumps and metal mask for forming solder bumps |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2004006927A JP2004006927A (en) | 2004-01-08 |
| JP2004006927A5 true JP2004006927A5 (en) | 2005-04-14 |
Family
ID=30438405
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2003188072A Pending JP2004006927A (en) | 2003-06-30 | 2003-06-30 | Wiring board with solder bump, method of manufacturing the same, and metal mask for forming solder bump |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2004006927A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP7075481B2 (en) * | 2018-04-12 | 2022-05-25 | 株式会社Fuji | Printed circuit board forming method and printed circuit board forming device |
-
2003
- 2003-06-30 JP JP2003188072A patent/JP2004006927A/en active Pending
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