JP2004006871A5 - - Google Patents
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- Publication number
- JP2004006871A5 JP2004006871A5 JP2003138355A JP2003138355A JP2004006871A5 JP 2004006871 A5 JP2004006871 A5 JP 2004006871A5 JP 2003138355 A JP2003138355 A JP 2003138355A JP 2003138355 A JP2003138355 A JP 2003138355A JP 2004006871 A5 JP2004006871 A5 JP 2004006871A5
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/150,303 US6882044B2 (en) | 2002-05-17 | 2002-05-17 | High speed electronic interconnection using a detachable substrate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2004006871A JP2004006871A (ja) | 2004-01-08 |
| JP2004006871A5 true JP2004006871A5 (ja) | 2006-06-29 |
Family
ID=29269793
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2003138355A Withdrawn JP2004006871A (ja) | 2002-05-17 | 2003-05-16 | 取り外し可能な基板を利用する高速な電子相互接続 |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US6882044B2 (ja) |
| EP (1) | EP1363327B1 (ja) |
| JP (1) | JP2004006871A (ja) |
| DE (1) | DE60334046D1 (ja) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7304362B2 (en) * | 2002-05-20 | 2007-12-04 | Stmicroelectronics, Inc. | Molded integrated circuit package with exposed active area |
| JP4866625B2 (ja) * | 2006-02-15 | 2012-02-01 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
| EP2091307B1 (en) * | 2006-11-15 | 2011-10-19 | Panasonic Corporation | Circuit board connection structure and circuit board |
| CN101986770B (zh) * | 2010-08-06 | 2013-04-03 | 深圳崇达多层线路板有限公司 | 多阶高密度线路板对位孔及制作方法 |
| DE102014217985A1 (de) * | 2014-09-09 | 2016-03-10 | Robert Bosch Gmbh | Verfahren zum Herstellen eines Bondpads, Bondpad und Bondverfahren |
Family Cites Families (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR1483570A (ja) * | 1965-06-23 | 1967-09-06 | ||
| GB1223705A (en) * | 1967-04-19 | 1971-03-03 | Hitachi Ltd | Semiconductor devices |
| JPS575356A (en) * | 1980-06-13 | 1982-01-12 | Toshiba Corp | Hybrid integrated circuit device |
| US5184207A (en) | 1988-12-07 | 1993-02-02 | Tribotech | Semiconductor die packages having lead support frame |
| JP2626203B2 (ja) * | 1990-08-03 | 1997-07-02 | 富士ゼロックス株式会社 | 電子写真感光体の製造方法 |
| US5060052A (en) * | 1990-09-04 | 1991-10-22 | Motorola, Inc. | TAB bonded semiconductor device having off-chip power and ground distribution |
| US5309322A (en) | 1992-10-13 | 1994-05-03 | Motorola, Inc. | Leadframe strip for semiconductor packages and method |
| DE19603444C2 (de) * | 1996-01-31 | 2003-04-24 | Siemens Ag | LED-Vorrichtung mit mindestens zwei LEDs |
| KR19980020726A (ko) | 1996-09-11 | 1998-06-25 | 김광호 | 칩 스케일의 볼 그리드 어레이 패키지 및 그의 제조 방법 |
| US6177722B1 (en) * | 1998-04-21 | 2001-01-23 | Atmel Corporation | Leadless array package |
| US6146813A (en) * | 1999-01-13 | 2000-11-14 | Applied Kinetics Inc. | Method and shunting and deshunting an electrical component and a shuntable/shunted electrical component |
| US6242280B1 (en) * | 1999-06-30 | 2001-06-05 | Agilent Technologies, Inc. | Method of interconnecting an electronic device |
| JP4441974B2 (ja) * | 2000-03-24 | 2010-03-31 | ソニー株式会社 | 半導体装置の製造方法 |
-
2002
- 2002-05-17 US US10/150,303 patent/US6882044B2/en not_active Expired - Fee Related
-
2003
- 2003-02-03 DE DE60334046T patent/DE60334046D1/de not_active Expired - Lifetime
- 2003-02-03 EP EP03002326A patent/EP1363327B1/en not_active Expired - Lifetime
- 2003-05-16 JP JP2003138355A patent/JP2004006871A/ja not_active Withdrawn