JP2004005569A - データおよび命令の流れを少なくとも１つの機能ユニットに配向（ｄｉｒｅｃｔ）するシステムおよび方法 - Google Patents

データおよび命令の流れを少なくとも１つの機能ユニットに配向（ｄｉｒｅｃｔ）するシステムおよび方法 Download PDF

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JP2004005569A
JP2004005569A JP2003104747A JP2003104747A JP2004005569A JP 2004005569 A JP2004005569 A JP 2004005569A JP 2003104747 A JP2003104747 A JP 2003104747A JP 2003104747 A JP2003104747 A JP 2003104747A JP 2004005569 A JP2004005569 A JP 2004005569A
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node
message
functional unit
nodes
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JP2004005569A5 (enExample
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Darel N Emmot
ダニエル・エヌ・エモット
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HP Inc
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Hewlett Packard Co
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/20—Processor architectures; Processor configuration, e.g. pipelining

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Image Generation (AREA)
JP2003104747A 2002-05-16 2003-04-09 データおよび命令の流れを少なくとも１つの機能ユニットに配向（ｄｉｒｅｃｔ）するシステムおよび方法 Pending JP2004005569A (ja)

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US10/147,763 US7176914B2 (en) 2002-05-16 2002-05-16 System and method for directing the flow of data and instructions into at least one functional unit

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JP2004005569A true JP2004005569A (ja) 2004-01-08
JP2004005569A5 JP2004005569A5 (enExample) 2006-01-12

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007533029A (ja) * 2004-04-12 2007-11-15 エヌヴィディア コーポレイション スケーラブルシェーダアーキテクチャ
JP2011505622A (ja) * 2007-11-30 2011-02-24 イマジネイション テクノロジーズ リミテッド タイルベース・レンダリング・システムにおけるマルチコアの形状処理

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US6825843B2 (en) * 2002-07-18 2004-11-30 Nvidia Corporation Method and apparatus for loop and branch instructions in a programmable graphics pipeline
US6809732B2 (en) * 2002-07-18 2004-10-26 Nvidia Corporation Method and apparatus for generation of programmable shader configuration information from state-based control information and program instructions
US7603506B2 (en) * 2004-06-18 2009-10-13 Broadcom Corporation Motherboard with video data processing card capability
US20050289523A1 (en) * 2004-06-24 2005-12-29 Broadcom Corporation Method and apparatus for transforming code of a non-proprietary program language into proprietary program language
US7612779B2 (en) * 2004-06-25 2009-11-03 Broadcom Corporation Video data processing circuits and systems comprising programmable blocks or components
US7821520B1 (en) * 2004-12-10 2010-10-26 Nvidia Corporation Fragment processor having dual mode register file
US8144149B2 (en) * 2005-10-14 2012-03-27 Via Technologies, Inc. System and method for dynamically load balancing multiple shader stages in a shared pool of processing units
US8237726B2 (en) * 2009-06-26 2012-08-07 Intel Corporation Register allocation for message sends in graphics processing pipelines
US8838120B2 (en) 2011-06-06 2014-09-16 Ericsson Modems Sa Methods and systems for a generic multi-radio access technology
GB2540382B (en) * 2015-07-15 2020-03-04 Advanced Risc Mach Ltd Data processing systems
GB2540227B (en) * 2015-12-21 2018-01-17 Imagination Tech Ltd Allocation of tiles to processing engines in a graphics processing system
US10437616B2 (en) * 2016-12-31 2019-10-08 Intel Corporation Method, apparatus, system for optimized work submission to an accelerator work queue
GB2558884B (en) * 2017-01-12 2019-12-25 Imagination Tech Ltd Graphics processing units and methods using cost indications for sets of tiles of a rendering space

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08202409A (ja) * 1995-01-30 1996-08-09 Hitachi Ltd 分散制御装置、システム及びコントローラ
JPH10240700A (ja) * 1997-02-28 1998-09-11 Hitachi Ltd グラフィックス並列処理装置
JPH11232233A (ja) * 1998-02-12 1999-08-27 Hitachi Ltd ネットワークコンピュータ管理方法及びネットワークコンピュータシステム
JP2001014478A (ja) * 1999-06-28 2001-01-19 Nec Eng Ltd グラフィックス並列処理装置

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US5448698A (en) * 1993-04-05 1995-09-05 Hewlett-Packard Company Inter-processor communication system in which messages are stored at locations specified by the sender
US5539730A (en) * 1994-01-11 1996-07-23 Ericsson Ge Mobile Communications Inc. TDMA/FDMA/CDMA hybrid radio access methods
US5794062A (en) * 1995-04-17 1998-08-11 Ricoh Company Ltd. System and method for dynamically reconfigurable computing using a processing unit having changeable internal hardware organization
US6347344B1 (en) * 1998-10-14 2002-02-12 Hitachi, Ltd. Integrated multimedia system with local processor, data transfer switch, processing modules, fixed functional unit, data streamer, interface unit and multiplexer, all integrated on multimedia processor
US6433802B1 (en) * 1998-12-29 2002-08-13 Ncr Corporation Parallel programming development environment
US6873331B2 (en) * 2002-03-29 2005-03-29 Hewlett-Packard Development Company, L.P. System and method for passing messages among processing nodes in a distributed system

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08202409A (ja) * 1995-01-30 1996-08-09 Hitachi Ltd 分散制御装置、システム及びコントローラ
JPH10240700A (ja) * 1997-02-28 1998-09-11 Hitachi Ltd グラフィックス並列処理装置
JPH11232233A (ja) * 1998-02-12 1999-08-27 Hitachi Ltd ネットワークコンピュータ管理方法及びネットワークコンピュータシステム
JP2001014478A (ja) * 1999-06-28 2001-01-19 Nec Eng Ltd グラフィックス並列処理装置

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007533029A (ja) * 2004-04-12 2007-11-15 エヌヴィディア コーポレイション スケーラブルシェーダアーキテクチャ
US7852340B2 (en) 2004-04-12 2010-12-14 Nvidia Corporation Scalable shader architecture
JP2011505622A (ja) * 2007-11-30 2011-02-24 イマジネイション テクノロジーズ リミテッド タイルベース・レンダリング・システムにおけるマルチコアの形状処理
JP2012146323A (ja) * 2007-11-30 2012-08-02 Imagination Technologies Ltd タイルベース・レンダリング・システムにおけるマルチコアの形状処理

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US20030217112A1 (en) 2003-11-20
US7176914B2 (en) 2007-02-13

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