JP2004005569A5 - - Google Patents
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- Publication number
- JP2004005569A5 JP2004005569A5 JP2003104747A JP2003104747A JP2004005569A5 JP 2004005569 A5 JP2004005569 A5 JP 2004005569A5 JP 2003104747 A JP2003104747 A JP 2003104747A JP 2003104747 A JP2003104747 A JP 2003104747A JP 2004005569 A5 JP2004005569 A5 JP 2004005569A5
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/147,763 US7176914B2 (en) | 2002-05-16 | 2002-05-16 | System and method for directing the flow of data and instructions into at least one functional unit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2004005569A JP2004005569A (ja) | 2004-01-08 |
| JP2004005569A5 true JP2004005569A5 (enExample) | 2006-01-12 |
Family
ID=29419102
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2003104747A Pending JP2004005569A (ja) | 2002-05-16 | 2003-04-09 | データおよび命令の流れを少なくとも１つの機能ユニットに配向（ｄｉｒｅｃｔ）するシステムおよび方法 |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US7176914B2 (enExample) |
| JP (1) | JP2004005569A (enExample) |
Families Citing this family (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6825843B2 (en) * | 2002-07-18 | 2004-11-30 | Nvidia Corporation | Method and apparatus for loop and branch instructions in a programmable graphics pipeline |
| US6809732B2 (en) * | 2002-07-18 | 2004-10-26 | Nvidia Corporation | Method and apparatus for generation of programmable shader configuration information from state-based control information and program instructions |
| US7385607B2 (en) * | 2004-04-12 | 2008-06-10 | Nvidia Corporation | Scalable shader architecture |
| US7603506B2 (en) * | 2004-06-18 | 2009-10-13 | Broadcom Corporation | Motherboard with video data processing card capability |
| US20050289523A1 (en) * | 2004-06-24 | 2005-12-29 | Broadcom Corporation | Method and apparatus for transforming code of a non-proprietary program language into proprietary program language |
| US7612779B2 (en) * | 2004-06-25 | 2009-11-03 | Broadcom Corporation | Video data processing circuits and systems comprising programmable blocks or components |
| US7821520B1 (en) * | 2004-12-10 | 2010-10-26 | Nvidia Corporation | Fragment processor having dual mode register file |
| US8144149B2 (en) * | 2005-10-14 | 2012-03-27 | Via Technologies, Inc. | System and method for dynamically load balancing multiple shader stages in a shared pool of processing units |
| GB0723536D0 (en) * | 2007-11-30 | 2008-01-09 | Imagination Tech Ltd | Multi-core geometry processing in a tile based rendering system |
| US8237726B2 (en) * | 2009-06-26 | 2012-08-07 | Intel Corporation | Register allocation for message sends in graphics processing pipelines |
| US9480077B2 (en) | 2011-06-06 | 2016-10-25 | Telefonaktiebolaget Lm Ericsson (Publ) | Methods and systems for a generic multi-radio access technology |
| GB2540382B (en) * | 2015-07-15 | 2020-03-04 | Advanced Risc Mach Ltd | Data processing systems |
| GB2540227B (en) | 2015-12-21 | 2018-01-17 | Imagination Tech Ltd | Allocation of tiles to processing engines in a graphics processing system |
| US10437616B2 (en) * | 2016-12-31 | 2019-10-08 | Intel Corporation | Method, apparatus, system for optimized work submission to an accelerator work queue |
| GB2558884B (en) * | 2017-01-12 | 2019-12-25 | Imagination Tech Ltd | Graphics processing units and methods using cost indications for sets of tiles of a rendering space |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5448698A (en) * | 1993-04-05 | 1995-09-05 | Hewlett-Packard Company | Inter-processor communication system in which messages are stored at locations specified by the sender |
| US5539730A (en) * | 1994-01-11 | 1996-07-23 | Ericsson Ge Mobile Communications Inc. | TDMA/FDMA/CDMA hybrid radio access methods |
| JP3244982B2 (ja) * | 1995-01-30 | 2002-01-07 | 株式会社日立製作所 | 分散制御システム |
| US5794062A (en) * | 1995-04-17 | 1998-08-11 | Ricoh Company Ltd. | System and method for dynamically reconfigurable computing using a processing unit having changeable internal hardware organization |
| JPH10240700A (ja) * | 1997-02-28 | 1998-09-11 | Hitachi Ltd | グラフィックス並列処理装置 |
| JPH11232233A (ja) * | 1998-02-12 | 1999-08-27 | Hitachi Ltd | ネットワークコンピュータ管理方法及びネットワークコンピュータシステム |
| US6347344B1 (en) * | 1998-10-14 | 2002-02-12 | Hitachi, Ltd. | Integrated multimedia system with local processor, data transfer switch, processing modules, fixed functional unit, data streamer, interface unit and multiplexer, all integrated on multimedia processor |
| US6433802B1 (en) * | 1998-12-29 | 2002-08-13 | Ncr Corporation | Parallel programming development environment |
| JP2001014478A (ja) * | 1999-06-28 | 2001-01-19 | Nec Eng Ltd | グラフィックス並列処理装置 |
| US6873331B2 (en) * | 2002-03-29 | 2005-03-29 | Hewlett-Packard Development Company, L.P. | System and method for passing messages among processing nodes in a distributed system |
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2002
- 2002-05-16 US US10/147,763 patent/US7176914B2/en not_active Expired - Lifetime
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2003
- 2003-04-09 JP JP2003104747A patent/JP2004005569A/ja active Pending