JP2004000756A - Pachinko game machine - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a pachinko game machine which can prevent the fraudulence using a 'hanging board' or the like. <P>SOLUTION: The subsequent updated initial value of a random number counter which determines a big win is calculated by adding the value of a byte counter to the subsequent value of the initial value memory. The value of the byte counter is updated by +1 repeatedly during the remaining time of a reset interrupt processing. As the residual time of the reset interrupt processing is an indefinite time changing in response to the situations of games, the 'hanging board' is incapable of grasping the indefinite time. Since the updated initial value of the random number counter is altered based on the value of the byte counter, which are updated repeatedly within such an indefinite time, this makes the grasp of the timing for the occurrence of a big win by the use of the 'hanging board' impossible, thereby enabling the prevention of the fraudulence using the 'hanging board'. It should be noted that the byte counter, is configured of 1 byte, so that the updated initial value of the random counter will not fall outside the correct update ranges even if reset interruption may occur at any timing whatsoever. <P>COPYRIGHT: (C)2004,JPO

Description

The present invention relates to a ball game machine typified by a pachinko game machine and the like, and more particularly to a ball game machine capable of preventing fraudulent acts such as a “hanging board”.

This kind of pachinko gaming machine is provided with a display device capable of variably displaying a plurality of types of symbols, and is configured to start the variability display when a hit ball hit into the game area passes through a symbol operation gate. . When the variable display is stopped in accordance with a predetermined combination of symbols, a big hit occurs, a predetermined game value is given to the player, and a large amount of game balls can be paid out.

有無 The presence or absence of such a big hit is determined at the timing when the hit ball passes through the symbol operation gate. That is, a counter that is updated periodically in a fixed range by one count (for example, in a range of 0 to 630 every 2 ms every one count) is provided, and when the hit ball passes through the symbol operation gate, the counter is updated. Is read, and when the read value of the counter matches a predetermined value such as “7”, a jackpot is generated. When a big hit occurs, a big hit command is transmitted to the display board of the display device via the cable connected to the connector of the control board. In the display device, the variable display is controlled based on the received big hit command, and a big hit display that stops at a predetermined combination of symbols appears.

However, recently, fraudulent activities using a fraudulent substrate called a “hanging substrate” have been reported. This fraudulent act involves hanging an improper board (attaching an improper “hanging board”) between the control board and the display board of the display device, thereby causing an unreasonable jackpot. Specifically, a counter (a counter that is periodically updated in a fixed range by one count) having the same function as the counter for determining the jackpot provided in the pachinko gaming machine is placed in the “hanging board”. By setting the value of the counter and resetting (clearing it to 0) when the power of the pachinko gaming machine is turned on, it is possible to grasp the timing of occurrence of a jackpot in the “hanging board”. Then, in accordance with the timing of the occurrence of the jackpot, the falsely generated signal for passing the gate operation symbol for the hit ball in the "hanging board" is output to the control board of the pachinko machine, thereby generating an unreasonable jackpot. It is to let. In a game arcade and the like, there has been a problem that an illegal act using the “hanging board” has caused a great deal of damage.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and makes it impossible to grasp the timing of occurrence of a jackpot, thereby preventing a fraudulent activity using a "hanging board" or the like. It is intended to provide.

In order to achieve this object, the ball game machine according to claim 1, wherein the interrupt processing is executed periodically, a random number counter composed of at least 2 bytes, and the value of the random number counter is set to the interrupt processing. First updating means for updating the value of the random number counter, and reading means for reading the value of the random number counter at a predetermined timing. The value of the random number counter read by the reading means matches one of predetermined values. In this case, a predetermined game value is given to the player under predetermined conditions, and a byte counter composed of 1 byte and the value of the byte counter are generated by the interrupt processing at the next time. A second updating means for repeatedly updating during the remaining time until the current time, a current initial value memory for storing an initial value of the random number counter being updated, and a current initial value memory based on the value of the byte counter. And a changing means for changing the random number counter and the value of the current initial value memory.

According to the first aspect of the present invention, in the interrupt processing periodically executed, the value of the random number counter is updated by the first updating means and is read by the reading means at a predetermined timing. . When the read value of the random number counter matches one of the predetermined values, a jackpot is won, and a predetermined game value is given to the player under predetermined conditions.

The changing means changes the values of the random number counter and the current initial value memory based on the value of the byte counter. That is, the initial value of the update of the random number counter is changed based on the value of the byte counter. As described above, since the initial value of the update of the random number counter is not a fixed value but a value that is periodically changed, the “hanging board” or the like may become invalid when the ball game machine is turned on. Even if the counter is reset, the value of the incorrect counter cannot be matched with the value of the random number counter. Therefore, it is possible to prevent the “hanging substrate” or the like from knowing the timing of the occurrence of the big hit.

In addition, the value of the byte counter is repeatedly updated by the second updating means during the remaining time until the next interrupt processing occurs. The length of the remaining time of the interrupt process changes according to the state of the game, and cannot be grasped by a “hanging board” or the like. Therefore, by changing the initial value of the update of the random number counter based on the value of the byte counter repeatedly updated during the remaining time, it is possible to more effectively prevent the value of the random number counter from being grasped by a “hanging board” or the like. can do.

By the way, an interrupt process for repeatedly updating the value of the byte counter may be executed in the middle of an instruction. Therefore, if the byte counter is composed of two or more bytes, the updated value of the byte counter may be out of the range of the update of the random number counter depending on the timing of the interrupt processing. The update of the byte counter is performed by reading the value once into the CPU (internal register or ALU), updating the value in the CPU, and writing the updated value into the byte counter. Therefore, if the byte counter is composed of two or more bytes, the updated value is written to the byte counter one byte at a time, so the next value is written after writing some bytes after updating and before writing all bytes. When an interrupt occurs, the value in the middle of writing becomes the value of the updated byte counter, and may become a value outside the range of updating the random number counter.
Since the initial value of the update of the random number counter is changed based on the value of the byte counter, for example, when changing the initial value of the update of the random number counter by writing the value of the byte counter to the random number counter, the value of the byte counter becomes the random number. If the value of the random number counter is out of the range for updating the counter, the value of the random number counter becomes a value outside the range that should be updated, and a predetermined problem occurs. For example, the probability of the jackpot occurrence becomes different from the expected probability, or the initial value of the update of the random number counter is not changed thereafter. However, since the byte counter is composed of one byte, the value in the middle of writing does not become the updated value of the byte counter even if the interrupt processing occurs at any timing, and the above-described problem is avoided. Can be.
According to a second aspect of the present invention, in the ball game machine according to the first aspect, the changing means includes a next initial value configured of at least two bytes for storing an initial value of a next update of the random number counter. A memory, third updating means for updating the value of the next initial value memory based on the value of the byte counter, and the third updating means when the value of the current initial value memory matches the value of the random number counter. Writing means for writing the value of the next initial value memory updated by the updating means to the random number counter and the current initial value memory.
According to a third aspect of the present invention, in the ball game machine of the first or second aspect, the third updating means is executed before the second updating means is executed.

According to the ball game machine of the present invention, the initial value of the update of the random number counter for determining the jackpot is not a fixed value but a value that is changed periodically. Therefore, even if the "hanging board" resets an invalid counter inside the same at the time of turning on the power of the ball game machine, the value of the counter cannot match the value of the random number counter. Therefore, there is an effect that it is impossible to know the timing of the occurrence of the jackpot by the "hanging board" or the like, and it is possible to prevent the illegal act by the "hanging board" or the like.
In addition, the value of the byte counter, which is the basis of the initial value of the update of the random number counter, is repeatedly updated during the remaining time of the interrupt processing that is periodically executed. The length of the remaining time of the interrupt process changes according to the state of the game, and cannot be grasped by a “hanging board” or the like. Therefore, since the value of the byte counter is repeatedly updated during the remaining time, it is possible to prevent the value of the random number counter from being grasped by the "hanging board" or the like.
Further, since the byte counter is composed of one byte, the value in the middle of writing does not become the updated value of the byte counter even if the interrupt processing occurs at any timing. Therefore, there is an effect that it is possible to avoid a problem that occurs when the value in the middle of writing becomes the value of the updated byte counter.
According to the second aspect of the present invention, when the value of the current initial value memory is equal to the value of the random number counter, the value of the next initial value memory updated by the third updating means is equal to the random number counter. And the current initial value memory. When the value of the current initial value memory matches the value of the random number counter, it means that one round of updating of the random number counter has been completed. Therefore, even if the initial value of the update of the random number counter is changed, it is possible to obtain a random number value with uniform random numbers.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. In this embodiment, a description will be given using a pachinko gaming machine as an example of a ball-and-ball gaming machine, in particular, a first-type pachinko gaming machine. Note that it is naturally possible to use the present invention for a third-type pachinko game machine and other ball and ball game machines.

FIG. 1 is a front view of the game board of the pachinko gaming machine P of the first embodiment. Around the game board 1, there are provided a plurality of winning ports 2 from which 5 to 15 game balls are paid out when a hit ball wins. In the center of the game board 1, a liquid crystal (LCD) display 3 for displaying a plurality of kinds of symbols as identification information is provided. The display screen of the LCD display 3 is divided into three parts in the horizontal direction, and in each of the three divided display areas, a variable display of a symbol is performed.

(4) A symbol operation gate (first-type starting port) 4 is provided below the LCD display 3, and when the hit ball passes through the symbol operation gate 4, the above-described variable display of the LCD display 3 is started. Below the symbol operation gate 4, a specific winning opening (large winning opening) 5 is provided. When the display result after the change of the LCD display 3 matches one of the predetermined symbol combinations, the specific winning opening 5 becomes a big hit and a predetermined time (for example, 30) is set so that the hit ball can easily win. The winning opening is opened until the second elapses or until 10 hit balls are won. The specific winning opening 5 is provided with a V zone 5a. If a hit ball passes through the V zone 5a while the specific winning opening 5 is open, a continuation right is established and the specific winning opening 5 is closed. Thereafter, the specific winning opening 5 is opened again for a predetermined time (or until a predetermined number of hit balls are won in the specific winning opening 5). The opening and closing operation of the specific winning opening 5 can be repeated up to 16 times (16 rounds), and a state in which the opening and closing operation can be performed is a state in which a predetermined game value is given (a special game state). is there.

FIG. 2 is a block diagram showing an electrical configuration of the pachinko gaming machine P. The control unit C of the pachinko gaming machine P includes a CPU 11 as an arithmetic unit, a ROM 12 storing various control programs executed by the CPU 11 and fixed value data, and a memory for temporarily storing various data. And a RAM 13. 3 to 5 are stored in the ROM 12 as a part of the control program.

The CPU 11 includes an ALU for performing an operation, an accumulator (hereinafter referred to as “Acc”) 11a, a plurality of internal registers 11b, and a flag register 11c. The value of the counter or the like provided in the RAM 13 is temporarily loaded (written) into the internal register 11b of the CPU 11, updated in the internal register 11b, and then saved (written) into the original counter of the RAM 13. T), will be updated.

The 68-system 8-bit CPU 11 saves (writes) a pair of 2-byte (16-bit) values of the internal register 11b to a 2-byte memory (in the RAM 13) of a continuous address with one instruction. be able to. In this case, the writing is performed in the order of the upper byte and the lower byte since the data bus of the bus line 14 is composed of 8 bits. On the other hand, in the 80-series 8-bit CPU, contrary to the 68-series CPU 11, the paired 2-byte (16-bit) internal register values are transferred to the 2-byte memory of the continuous address by the lower byte upper byte. It can be saved by one instruction in byte order.

The RAM 13 includes a random number counter 13a, a current initial value memory 13b, a next initial value memory 13c, and a byte counter 13d. The random number counter 13a is a counter for determining the occurrence of a jackpot, and is updated by one count every 2 ms within the range of “0 to 630 (0 to 276h)” by the random number update process (S7) of FIG. You. Therefore, the random number counter 13a is composed of 2 bytes. If the value of the random number counter 13a acquired when the hit ball passes through the symbol operation gate 4 is, for example, "7", a big hit occurs. When a big hit occurs, a big hit command is sent from the control unit C to a display device D described later. The display device D controls the variable display of the LCD display 3 to a jackpot state based on the jackpot command.

The current initial value memory 13b is a memory for storing an initial value of the random number counter 13a being updated, and the next initial value memory 13c is a memory for storing an initial value of the next update of the random number counter 13a. . Each of the current initial value memory 13b and the next initial value memory 13c is composed of 2 bytes similarly to the random number counter 13a, and each of "0 to 630 (0 to 276h)" is the same as the update range of the random number counter 13a. Updated within range. In this embodiment, the initial value of the update of the random number counter 13a is changed every time the random number counter 13a is updated. Therefore, when the updated value of the random number counter 13a matches the value of the current initial value memory 13b, it means that one round of updating of the random number counter 13a has been completed, and the coincidence of the two values 13a and 13b triggers the update. The value of the next initial value memory 13c at that time is written to the random number counter 13a and the current initial value memory 13b, and the updated initial value of the random number counter 13a is changed. Therefore, even if the initial value of the update of the random number counter 13a is changed, there is uniformity of the random numbers (the same value is not obtained when continuously obtained, and all values can be extracted with the same probability). You can get a random value.

The byte counter 13d is a counter for updating the value of the next initial value memory 13c, and is composed of one byte. The value of the byte counter 13d is within the range of "0 to 255 (0 to 0FFh)" during the remaining time until the next reset interrupt occurs after the end of the reset interrupt process from S1 to S20. It is repeatedly added (incremented) by "1" and updated. The updated value of the byte counter 13d is added to the value of the next initial value memory 13c in the next initial value memory updating process (S6) executed before the random number updating process (S7), and the next initial value memory 13c is added. Update the value of.

The reset interrupt processing is executed every 2 ms, but the processing time of each processing from S1 to S20 is programmed so as to end within 2 ms at the maximum, so that the remaining time always occurs. . Since the processing time of each processing from S1 to S20 executed in one reset interrupt processing changes according to the game situation, the remaining time of the reset interrupt processing is not a fixed time but a game time. It becomes an indefinite time that changes according to it. Since the "hanging board" cannot grasp this indefinite time, the value of the next initial value memory 13c is updated based on the value of the byte counter 13d that is repeatedly updated within the indefinite time, and the next initial value is updated. By using the value of the memory 13c as an initial value for updating the random number counter 13a, it is impossible to grasp the timing of the occurrence of the big hit by the "hanging board".

The value of the byte counter 13d is updated by first reading the value into the CPU 11, updating the value in the CPU 11, and then writing and updating the value in the byte counter 13d. On the other hand, the reset interrupt is a non-maskable interrupt for which the occurrence of an interrupt cannot be prohibited, has the highest priority of the interrupt, and is forcibly started even while the CPU 11 is executing an instruction. This is an interrupt. Therefore, the byte counter 13d is configured with one byte so that no problem occurs even if the next reset interrupt occurs at any timing during the updating of the byte counter 13d. This is because the writing of one byte of data is performed at a time, and therefore, by configuring the byte counter 13d with one byte, the value of the byte counter 13d can be prevented from becoming a value in the middle of writing.

The CPU 11, the ROM 12, and the RAM 13 are connected to each other via a bus line 14, and the bus line 14 is also connected to an input / output port 15. The input / output port 15 is connected to the display device D and another input / output device 16. The control unit C sends operation commands to the display device D and other input / output devices 16 via the input / output port 15 to control those devices. The variable display on the LCD display 3 and the opening / closing operation of the specific winning opening 5 are also controlled based on this operation command.

The display device D includes a CPU 21, a program ROM 22, a work RAM 23, a video RAM 24, a character ROM 25, an image controller 26, an input / output port 27, and the LCD display 3. The CPU 21 of the display device D performs display control (variable display) of the LCD display 3 in response to an operation command output from the control unit C. The program ROM 22 stores a program executed by the CPU 21. Have been. The work RAM 23 is a memory that stores work data used when the CPU 21 executes a program.

The video RAM 24 is a memory in which data displayed on the LCD display 3 is stored. By rewriting the contents of the video RAM 24, the display contents of the LCD display 3 are changed. That is, the change display of the symbol in each display area is performed by rewriting the contents of the video RAM 24. The character ROM 25 is a memory for storing character data such as symbols displayed on the LCD display 3. The image controller 26 adjusts the timing of each of the CPU 21, the video RAM 24, and the input / output port 27 to intervene reading and writing of data, and to display the display data stored in the video RAM 24 at a predetermined timing with reference to the character ROM 25. This is to be displayed on the LCD display 3.

Next, each processing executed in the pachinko gaming machine P configured as described above will be described with reference to the flowcharts of FIGS. FIG. 3 is a flowchart of a reset interrupt process executed every 2 ms in the control unit C of the pachinko gaming machine P. The main control of the pachinko gaming machine P is executed by this reset interrupt processing.

In the reset interrupt processing, first, a stack pointer is set (S1), and a pattern written in a predetermined area of the RAM 13 is checked (S2). As a result of the check, if the predetermined pattern is written in the predetermined area, the RAM 13 is normal without any abnormality (S2: normal), and the process proceeds to S3. On the other hand, as a result of the check in S2, if the predetermined pattern is not written in the predetermined area, it is the reset interrupt processing executed first after the power is turned on, or the RAM 13 is abnormal (S2: abnormal). In this case, the process proceeds to S23, where the contents of the RAM 13 are once cleared, and then an initial value is written into the RAM 13 (S23), and the process waits for the next reset interrupt process.

で は In the process of S3, the timer interrupt is set (S3). The timer interrupt set here includes a timer interrupt for generating a strobe signal for transmitting a command for controlling the display on the LCD display 3 to the display device D. After the setting of the timer interrupt, each interrupt is enabled (S4). After the permission of the interrupt, the output data updated in the previous reset interrupt process by the special symbol change process (S16), the display data creation process (S18), the ramp / information processing (S19), and the like are simultaneously processed. A port output process for outputting to a port is executed (S5). Thereafter, a next initial value memory update process (S6) described later is executed to update the value of the next initial value memory 13c, and a random number update process (S7) is executed to set the value of the random number counter 13a to "+1". After that, the storage timer is subtracted (S8). The storage timer subtraction process shortens the symbol change display time when the number of reserved balls for the jackpot determination is equal to or more than a predetermined number and the symbol display is being displayed on the LCD display 3.

In the switch reading process (S9), the value of each switch is read, whereby the hit ball 2 hit into the game area 1 wins the winning opening 2 or the large winning opening 5 (including the V zone 5a), and the symbol operation gate 4 This is a process for detecting a passing ball and a prize ball or a lending ball. The count abnormality monitoring process (S10) is a process for monitoring whether there is an abnormality in the switch data read by the switch reading process of S9. For example, even if the special winning opening 5 is opened and the hit ball is detected by the V count switch for detecting the passing of the hit ball through the V zone 5a, the winning in the special winning opening 5 other than the V zone 5a is detected. If one ball cannot be detected by the count switch, the 10 count switch has some abnormality, for example, the 10 count switch is removed. In addition, if one prize ball is not paid out even though the motor for paying out the prize ball is driven, some abnormality has occurred in the prize ball payout device. As described above, in the count abnormality monitoring process (S10), the presence or absence of the above-described abnormality is monitored based on the switch data read in the switch reading process (S9).

In the symbol counter updating process (S11), a counter updating process for determining a symbol to be stopped and displayed as a result of the variable display performed on the LCD display 3 is performed. Further, in the symbol check process (S12), based on the value of the counter updated in the symbol counter update process (S11), a big hit symbol used in the special symbol variation process (S16), a lost symbol, and a reach symbol. Is determined.

In the process from S3 to S12, if no error has occurred (S13: normal), the normal symbol variation process (S14) displays the 7-segment LED variation, and as a result of the variation display, a hit occurs. In such a case, a hitting process is performed to open the electric accessory (not shown) for a predetermined time. Thereafter, the state flag is checked (S15), and if the symbol is being displayed on the LCD display 3 while the symbol is being changed (S15: symbol is being changed), the timing at which the hit ball passes through the symbol operating gate 4 by the special symbol changing process (S16). Based on the value of the random number counter 13a read in step (1), it is determined whether or not a big hit has occurred, and a process of changing the display symbol on the LCD display 3 is executed. On the other hand, as a result of checking the status flag, if a big hit is being made (S15: big hit), a big hit process (S17) such as opening the big winning port 5 is executed. Further, as a result of checking the state flag, if the symbol is not fluctuating or a big hit (S15: other), the processing of S16 and S17 is skipped, and the process proceeds to the display data creation processing of S18. In the process of S13, if an error is confirmed (S13: error), each process of S14 to S17 is skipped, and the process proceeds to the display data creation process of S18.

In the display data creation process (S18), demonstration data to be displayed on the LCD display 3 and display data of a 7-segment LED are created in addition to the symbol change display. Various lamp data including data are created. In the sound effect processing (S20), sound effect data according to the game situation is created. The display data and the sound effect data are output to each device by the port output process (S5) and the timer interrupt process described above.

After the end of the sound effect processing (S20), the symbol counter updating processing (S21), which is the same processing as that of S11, and "+1" of the byte counter 13d for the remaining time until the next reset interrupt processing occurs. The increment process (S22) as addition is repeatedly executed. Since the execution time of each processing of S1 to S20 changes according to the state of the game, the remaining time until the next reset interrupt processing occurs is not a fixed time but changes according to the state of the game. Therefore, by repeatedly executing the symbol counter updating process (S21) using the remaining time, the stopped symbol can be changed at random.

{Circle around (2)} By repeatedly updating the value of the byte counter 13d using the remaining time, the value of the byte counter 13d can be made unobservable by the “hanging board”. The value of the byte counter 13d is added to the value of the next initial value memory 13c in the next initial value memory update processing (S6) to update the value of the next initial value memory 13c. Since the value of the next initial value memory 13c is a value to be the initial value of the next update of the random number counter 13a, the value of the byte counter 13d cannot be grasped by the "hanging board", so that the timing of occurrence of the jackpot can be reduced. It is not possible to grasp by the "hanging board", and it is possible to prevent fraud by the "hanging board".

FIG. 4 is a flowchart of the next initial value memory update process. In the next initial value memory update process (S6), the value of the next initial value memory 13c storing the initial value of the update of the random number counter 13a is stored in the internal register 11b of the CPU 11 based on the value of the byte counter 13d. Update is performed within the range of “0-630 (0-276h)” of the update range of 13a.

{First, the value of the next initial value memory 13c composed of 2 bytes is written into the 2-byte internal register 11b (S41). Next, the value of the 1-byte byte counter 13d is added to the internal register 11b (S42), and whether or not the value of the added internal register 11b is equal to or greater than "631", that is, the update range of the random number counter 13a is determined. It is checked whether the value is exceeded (S43).

If the value of the internal register 11b after the addition is equal to or more than "631" (S43: Yes), the value exceeds the update range value of the random number counter 13a, and the value is used as the initial value of the next random number counter 13a. It cannot be written to the initial value memory 13c. Therefore, “631 (277h)”, which is the maximum value of the update range of the random number counter 13a + 1, is subtracted from the value of the internal register 11b (S44), and the value of the internal register 11b is changed from “0 to 630 (0 to 276h)”. Set a value within the range.

On the other hand, if the value of the internal register 11b after the addition is equal to or less than “630” (S43: No), since the value is within the update range of the random number counter 13a, the process of S44 is skipped and the process proceeds to S45. I do. In the process of S45, the 2-byte value of the internal register 11b is written to the next initial value memory 13c in the order of the upper byte and the lower byte by the 2-byte write command of the 68 system CPU 11 in the order of the upper byte and the lower byte (S45), and the next initial value memory 13c is updated. To end.

FIG. 5 is a flowchart of the random number update process. In the random number updating process (S7), the value of the random number counter 13a is updated by "+1" in the range of "0 to 630 (0 to 276h)" via the internal register 11b of the CPU 11 and used by the control unit C. Other random numbers are being updated.

{First, the value of the 2-byte random number counter 13a is written to the 2-byte internal register 11b (S51). The value of the internal register 11b is incremented by 1 (S52), and it is checked whether or not the value of the internal register 11b after the addition is equal to or greater than "631", that is, whether or not the value exceeds the value of the update range of the random number counter 13a. (S53). If the value of the internal register 11b after the addition is equal to or more than "631" (S53: Yes), the value of the internal register 11b is cleared to "0" because it exceeds the value of the update range (S54). On the other hand, if the value of the internal register 11b after the addition is equal to or less than “630” (S53: No), since the value is within the update range, the process of S54 is skipped, and the process proceeds to S55.

In the process of S55, the updated value of the internal register 11b is compared with the value of the current initial value memory 13b. Since the current initial value memory 13b stores the initial value of the update of the random number counter 13a currently being updated, if the two values are equal (S55: Yes), the update of the random number counter 13a is completed. That is. Therefore, in such a case, the value of the next initial value memory 13c that stores the initial value of the next update of the random number counter 13a is written into the internal register 11b (S56), and the value of the internal register 11b is stored in the current initial value memory 13b. Writing to the random number counter 13a (S57, S58), the update initial value of the random number counter 13a is changed.

On the other hand, if the updated value of the internal register 11b is not equal to the value of the current initial value memory 13b (S55: No), the updating of the random number counter 13a has not been completed yet. The processing is skipped, the value of the internal register 11b updated in the processing of S52 to S54 is written to the random number counter 13a (S58), and the random number counter 13a is updated. After that, an update process of another random number used in the control unit C is performed (S59), and this random number update process ends.

As described above with reference to the flowcharts of FIGS. 3 to 5, the random number counter 13 a used for the jackpot determination changes the initial value of the update for each round of update, and the initial value of the update is It is calculated by adding the value of the byte counter 13d to the value of the next initial value memory 13c. Since the byte counter 13d is repeatedly updated during the remaining time of the reset interrupt process that changes according to the state of the game, the value cannot be grasped by the "hanging board". Therefore, the value of the random number counter 13a is updated from the value that cannot be grasped by the “hanging board” every time the circuit is updated. It can prevent fraud.

The reset interrupt is a non-maskable interrupt having the highest interrupt priority and is started even during the execution of an instruction. However, since the byte counter 13d is composed of one byte, No problem occurs even if the next reset interrupt occurs at any timing during the updating of the byte counter 13d. This is because 1-byte data writing is performed at a time, and the value of the byte counter 13d does not become a value in the middle of writing.

Next, a second embodiment will be described with reference to FIGS. FIG. 6 is a flowchart of the reset interrupt process of the second embodiment, and FIG. 7 is a flowchart of the random number update process of the second embodiment. In the second embodiment, if the value of the random number counter 13a matches the value of the current initial value memory 13b without using the next initial value memory 13c, the byte counter 13d To calculate the initial value of the next update of the random number counter 13a. The same portions as those in the first embodiment are denoted by the same reference numerals, and description thereof will be omitted.

In the reset interrupt process of FIG. 6, the next initial value memory update process (S6) in the reset interrupt process of the first embodiment of FIG. 3 is deleted, and the random number update process (S7) is replaced with the random number update process (S7) of FIG. (S70). Other processes (S1 to S5 and S8 to S23) are the same as the reset interrupt process of FIG.

In the random number update process (S70) of FIG. 7, first, the value of the random number counter 13a composed of 2 bytes is written into the 2-byte internal register 11b (S71), and the value of the internal register 11b is incremented by 1 ( S72), the value of the random number counter 13a is updated. It is checked whether or not the value of the internal register 11b after the addition is equal to or more than "631", that is, whether or not the value exceeds the update range value of the random number counter 13a (S73). : Yes), since the value exceeds the update range of the random number counter 13a, the value of the internal register 11b is cleared to "0" (S74). On the other hand, if the value of the internal register 11b after the addition is equal to or less than "630" (S73: No), since the value is within the update range of the random number counter 13a, the process of S74 is skipped and the process proceeds to S75. I do.

In the process of S75, the value of the updated internal register 11b is compared with the value of the current initial value memory 13b. Since the current initial value memory 13b stores the initial value of the update of the random number counter 13a currently being updated, if the two values are equal (S75: Yes), it is determined that the update of the random number counter 13a has been completed once. That is. Therefore, in such a case, the value of the 1-byte byte counter 13d is added to the internal register 11b in order to calculate the initial value of the next update of the random number counter 13a (S76). It is checked whether or not the value of the internal register 11b after the addition is equal to or greater than "631", that is, whether or not the value exceeds the update range value of the random number counter 13a (S77). : Yes), since the value exceeds the update range of the random number counter 13a, "631", which is the maximum value of the update range of the random number counter 13a + 1, is subtracted from the value of the internal register 11b after the addition (S78). The value of the internal register 11b is set to a value within the update range of the random number counter 13a. On the other hand, if the value of the internal register 11b after the addition is equal to or smaller than "630" (S77: No), the value is within the update range of the random number counter 13a, and thus the process of S78 is skipped and the process proceeds to S79. I do.

In the processing of S79, the initial value of the next update of the random number counter 13a calculated in the processing of S76 to S78 is stored in the internal register 11b, and the value of the internal register 11b is stored in the current initial value memory 13b. Writing to the random number counter 13a (S79, S80), the update initial value of the random number counter 13a is changed.

On the other hand, if the value of the internal register 11b updated in the processing of S72 to S74 is not equal to the value of the current initial value memory 13b (S75: No), the update of the random number counter 13a has not been completed yet. Therefore, the processing of S76 to S79 is skipped, the value of the internal register 11b updated in the processing of S72 to S74 is written to the random number counter 13a (S80), and the random number counter 13a is updated. Thereafter, another random number update process used by the control unit C is performed (S81), and the random number update process ends.

As described above, the initial value of the update of the random number counter 13a can be changed by directly using the value of the byte counter 13d without using the next initial value memory 13c.

Next, a third embodiment will be described with reference to FIG. In the third embodiment, not only the next initial value memory 13c is not used, but also the current initial value memory 13e is composed of one byte. That is, when the upper byte of the random number counter 13a is a predetermined value ("0" in the third embodiment) and the lower byte of the random number counter 13a matches the value of the 1-byte current initial value memory 13e, The value of the byte counter 13d is written to the lower byte of the random number counter 13a and the 1-byte current initial value memory 13e to change the initial value of the update of the random number counter 13a. Thus, in the third embodiment, the initial value of the update of the random number counter 13a is changed within the range of “000h to 0FFh”. The same parts as those in the second embodiment are denoted by the same reference numerals, and description thereof will be omitted. The reset interrupt processing of the third embodiment uses the reset interrupt processing of the second embodiment of FIG.

In the random number updating process (S70) of FIG. 8, first, the value of the random number counter 13a composed of 2 bytes is written into the 2-byte internal register 11b (S91), and the value of the internal register 11b is incremented by 1 (S91). S92), the value of the random number counter 13a is updated. It is checked whether or not the value of the internal register 11b after the addition is equal to or greater than "631", that is, whether or not the value exceeds the update range value of the random number counter 13a (S93). : Yes), the value of the internal register 11b is cleared to "0" because the value exceeds the update range value of the random number counter 13a (S94). On the other hand, if the value of the internal register 11b after the addition is equal to or smaller than "630" (S93: No), the value is within the update range of the random number counter 13a, and thus the process of S94 is skipped and the process proceeds to S95. I do.

In the process of S95, it is checked whether or not the value of the upper byte of the updated internal register 11b is “0” (S95). If it is “0” (S95: Yes), the lower byte of the internal register 11b is further checked. The byte value is compared with the 1-byte value of the current initial value memory 13e (S96). Since the lower byte of the update initial value of the random number counter 13a currently being updated is stored in the current initial value memory 13e, if the two values are equal (S96: Yes), the update of the random number counter 13a goes around once. It is finished. Therefore, in such a case, in order to change the initial value of the update of the random number counter 13a, the value of the 1-byte byte counter 13d is written to the lower byte of the 2-byte internal register 11b (S97), and the value of the internal register 11b is changed. To the initial value of the next update of the random number counter 13a. The value of the lower byte of the internal register 11b is written into the 1-byte current initial value memory 13e (S98), the value of the current initial value memory 13e is updated, and the values of the upper byte and the lower byte of the internal register 11b are updated. Writing to the 2-byte random number counter 13a (S99), the initial value of the update of the random number counter 13a is changed.

On the other hand, in the process of S95, when the value of the upper byte of the internal register 11b updated in the processes of S92 to S94 is not “0” (S95: No), the value of the upper byte of the updated internal register 11b is “0”. Even if it is "0" (S95: Yes), if the value of the lower byte of the internal register 11b is not equal to the value of the 1-byte current initial value memory 13e (S96: No), the random number counter 13a is updated. It has not been completed yet. Therefore, in this case, the processing of S97 and S98 is skipped, the value of the internal register 11b updated in the processing of S92 to S94 is written to the random number counter 13a (S99), and the random number counter 13a is updated.

After the process of S99 is completed, another random number used in the control unit C is updated (S100), and the random number update process is ended. As described above, the current initial value memory 13e is composed of 1 byte without using the next initial value memory 13c, and the initial value of the update of the random number counter 13a is changed by directly using the value of the byte counter 13d. You can also. In this case, the match between the value of the 2-byte random number counter 13a and the value of the 1-byte current initial value memory 13e is compared when the upper byte of the random number counter 13a has a predetermined value ("0" in the third embodiment). ), Depending on whether the lower byte of the random number counter 13a matches the value of the current initial value memory 13e.

In the process of S95, since the value of the upper byte of the internal register 11b updated in the processes of S92 to S94 is compared with “0”, the initial value of the update of the random number counter 13a is in the range of “000h to 0FFh”. Will be changed within. Therefore, when the value of the upper byte of the updated internal register 11b is compared with “1” in the process of S95, the initial value of the update of the random number counter 13a is changed in the range of “100h to 1FFh”. . When the value is compared with "2", the initial value of the update of the random number counter 13a is changed in the range of "200h to 276h". In this case, the lower byte of the internal register 11b is processed in S97. If the value of the byte counter 13d to be written to the memory is "77h to 0FFh", a process of correcting the value to be in the range of "00h to 76h" is required.

Next, a fourth embodiment will be described with reference to FIG. FIG. 9 is a flowchart of the reset interrupt process according to the fourth embodiment. In the fourth embodiment, after the value of the byte counter 13d is cleared to "0", the value of the byte counter 13d is repeatedly updated using the remaining time of the reset interrupt processing. The same portions as those in the first embodiment are denoted by the same reference numerals, and description thereof will be omitted.

As shown in FIG. 9, after the end of the sound effect processing (S20), the value of the byte counter 13d is cleared to "0" (S101), and the symbol counter is kept for the remaining time until the next reset interrupt processing occurs. The update process (S21) and the increment process (S22), which is an addition of “+1” to the byte counter 13d, are repeatedly executed.

As long as the value of the byte counter 13d is not updated one or more times by the processing of S22 during the remaining time of one reset interrupt processing, the value of the byte counter 13d is set to “0” before the processing of S22 as described above. By clearing, it is possible to obtain the same effect as repeatedly updating the value of the next initial value memory 13c during the remaining time of the reset interrupt processing. That is, according to the configuration of the fourth embodiment, the value of the next initial value memory 13c can be continuously updated.

In place of the process in S101, the value of the byte counter 13d may be cleared to "0" in the next initial value memory update process (S6) in FIG. Specifically, the value of the byte counter 13d may be cleared to "0" after the execution of the process of S45.

Also, in the reset interrupt processing of FIG. 6 of the second and third embodiments, similarly to the reset interrupt processing of FIG. 9, immediately after the sound effect processing of S20 and before the repetition processing of S21 and S22, A "0" clearing process of the byte counter 13d corresponding to the process of S101 is added, or immediately after the process of S80 in the random number updating process of FIG. 7, or immediately after the process of S99 in the random number updating process of FIG. , A "0" clear process of the byte counter 13d corresponding to the process of S101 may be added.

In each of the above embodiments, the non-maskable reset interrupt processing corresponds to the interrupt processing according to claim 1, and the first update means includes the processing of S51 to S54 and S58 of the random number update processing (S7) of FIG. The processes from S71 to S74 and S80 of the random number update process (S70) in FIG. 7 correspond to the processes from S91 to S94 and S99 in the random number update process (S70) in FIG. 8, respectively. The second updating means corresponds to the processing of S22 of FIGS. 3 and 6, and the changing means corresponds to the processing of S55 to S58 of the random number updating processing (S7) of FIG. 5, and the random number updating processing (S70) of FIG. ) Correspond to the processing from S75 to S80, and the processing from S95 to S99 in the random number update processing (S70) in FIG.

As described above, the present invention has been described based on the embodiments. However, the present invention is not limited to the above embodiments, and it is easily understood that various improvements and modifications can be made without departing from the spirit of the present invention. It can be inferred.

For example, in each of the above-described embodiments, the value of the byte counter 13d is updated in the adding direction by increment. However, the present invention is not limited to this. The updating may be performed in the subtracting direction by decrement or the like. The updating of the value of the next initial value memory 13c in the first embodiment (S42 to S44) and the updating of the value of the current initial value memory 13b in the second embodiment (S76 to S79) are performed by updating the value of the byte counter 13d. Although the addition has been performed, these may be performed by subtracting the value of the byte counter 13d.

Also, in each of the above embodiments, the byte counter 13d is composed of 1 byte (8 bits), but the size of the byte counter 13d is not necessarily fixed to 8 bits. For example, if the CPU can update 16-bit data at one time, the byte counter may be configured with 16 bits. If the CPU can update 32-bit data at one time, the byte counter may be configured with 32 bits. You may. That is, the size of the byte counter can be set within the range of the maximum number of bits that can be updated at a time by the CPU.

(5) Modifications of the present invention are described below. 2. The ball game machine according to claim 1, wherein the changing means stores a next initial value memory composed of at least 2 bytes for storing an initial value of a next update of the random number counter, and a value of the next initial value memory. A third updating means for updating based on the value of the byte counter; and a next initial value memory updated by the third updating means when the value of the current initial value memory matches the value of the random number counter. A ball and ball game machine 1 comprising writing means for writing a value to the random number counter and a current initial value memory.

弾 In the ball game machine 1, the ball game machine 2 is characterized in that the third updating means is executed before execution of the second updating means.

2. The bullet game machine according to claim 1, wherein said changing means changes the value of said byte counter by adding or subtracting it from said random number counter and a value of a current initial value memory. Ball game machine 3.

2. The ball game machine according to claim 1, wherein said current initial value memory is composed of 2 bytes, and said changing means stores a value of said byte counter of 1 byte in said lower byte of said random number counter and current initial value memory. A ball game machine 4 which writes and changes those values.

2. The ball and ball game machine according to claim 1, wherein said current initial value memory is composed of one byte, and said changing means judges whether said one byte current initial value memory matches said two byte random number counter. Comparing means for determining whether the value of the lower byte of the random number counter matches the value of the current initial value memory when the upper byte of the random number counter is a predetermined value (for example, “0”). Writing means for writing the value of the byte counter of 1 byte to the lower byte of the random number counter of 2 bytes and the current initial value memory of 1 byte when it is determined by the comparing means that they match. A ball game machine 5 characterized by the following.

The ball game machine according to claim 1, further comprising reset means for resetting a value of said byte counter before execution of said second updating means.

1 is a front view of a game board of a pachinko gaming machine according to a first embodiment of the present invention. It is a block diagram showing the electrical configuration of the pachinko gaming machine. 9 is a flowchart illustrating a reset interrupt process. It is the flowchart which showed the next initial value memory update process. 9 is a flowchart illustrating a random number update process. 9 is a flowchart illustrating a reset interrupt process according to the second embodiment. It is a flow chart which showed random number updating processing of a 2nd example. It is the flowchart which showed the random number update process of 3rd Example. 14 is a flowchart illustrating a reset interrupt process according to a fourth embodiment.

Explanation of reference numerals

11 CPU of control unit
11b Internal register of CPU of control unit 13 RAM of control unit
13a Random number counters 13b, 13e Current initial value memory 13c Next initial value memory 13d Byte counter C Control unit P Pachinko game machine (ball game machine)

Claims (3)

Interrupt processing that is periodically executed, a random number counter composed of at least two bytes, first updating means for updating the value of the random number counter by the interrupt processing, and a value of the random number counter at a predetermined timing Readout means for reading out the random number counter, and when the value of the random number counter read out by the readout means coincides with one of the predetermined values, a bullet giving a predetermined game value to the player under predetermined conditions. In ball game machines,
A byte counter consisting of one byte,
Second updating means for repeatedly updating the value of the byte counter during the remaining time until the next occurrence of the interrupt processing by the interrupt processing;
A current initial value memory for storing an initial value of the random number counter being updated;
Changing means for changing the value of the random number counter and the current initial value memory based on the value of the byte counter. The changing means includes a next initial value memory configured of at least 2 bytes for storing an initial value of a next update of the random number counter, and a second initial value memory that updates a value of the next initial value memory based on the value of the byte counter. 3 updating means, and when the value of the current initial value memory matches the value of the random number counter, the value of the next initial value memory updated by the third updating means is stored in the random number counter and the current initial value memory. The ball game machine according to claim 1, further comprising writing means for writing. 3. The ball game machine according to claim 2, wherein the third updating means is executed before the second updating means is executed.

Images