JP2003511857A - 一様な浅いトレンチ・エッチング・プロファイルのための方法 - Google Patents

一様な浅いトレンチ・エッチング・プロファイルのための方法

Info

Publication number
JP2003511857A
JP2003511857A JP2001529011A JP2001529011A JP2003511857A JP 2003511857 A JP2003511857 A JP 2003511857A JP 2001529011 A JP2001529011 A JP 2001529011A JP 2001529011 A JP2001529011 A JP 2001529011A JP 2003511857 A JP2003511857 A JP 2003511857A
Authority
JP
Japan
Prior art keywords
sccm
etching
gas
flow rate
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2001529011A
Other languages
English (en)
Japanese (ja)
Other versions
JP2003511857A5 (https=
Inventor
タミー、ツェン
カルビン、ティー．ガブリエル
エドワード、ケイ．イェイ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Electronics NV filed Critical Philips Electronics NV
Publication of JP2003511857A publication Critical patent/JP2003511857A/ja
Publication of JP2003511857A5 publication Critical patent/JP2003511857A5/ja
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H10P76/405—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their composition, e.g. multilayer masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/69—Etching of wafers, substrates or parts of devices using masks for semiconductor materials
    • H10P50/691—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials
    • H10P50/692—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their composition, e.g. multilayer masks or materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H10W10/0145—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations of trenches having shapes other than rectangular or V-shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/17—Isolation regions comprising dielectric materials formed using trench refilling with dielectric materials, e.g. shallow trench isolations

Landscapes

  • Drying Of Semiconductors (AREA)
  • Element Separation (AREA)
JP2001529011A 1999-10-04 2000-09-27 一様な浅いトレンチ・エッチング・プロファイルのための方法 Withdrawn JP2003511857A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/411,758 1999-10-04
US09/411,758 US6342428B1 (en) 1999-10-04 1999-10-04 Method for a consistent shallow trench etch profile
PCT/EP2000/009507 WO2001026142A1 (en) 1999-10-04 2000-09-27 Method for a consistent shallow trench etch profile

Publications (2)

Publication Number Publication Date
JP2003511857A true JP2003511857A (ja) 2003-03-25
JP2003511857A5 JP2003511857A5 (https=) 2007-11-15

Family

ID=23630193

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001529011A Withdrawn JP2003511857A (ja) 1999-10-04 2000-09-27 一様な浅いトレンチ・エッチング・プロファイルのための方法

Country Status (4)

Country Link
US (1) US6342428B1 (https=)
EP (1) EP1157411A1 (https=)
JP (1) JP2003511857A (https=)
WO (1) WO2001026142A1 (https=)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7169682B2 (en) 2004-01-29 2007-01-30 Sharp Kabushiki Kaisha Method for manufacturing semiconductor device
JP2008192759A (ja) * 2007-02-02 2008-08-21 Tokyo Electron Ltd エッチング方法、エッチング装置及び記憶媒体

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6607984B1 (en) 2000-06-20 2003-08-19 International Business Machines Corporation Removable inorganic anti-reflection coating process
US6580170B2 (en) * 2000-06-22 2003-06-17 Texas Instruments Incorporated Semiconductor device protective overcoat with enhanced adhesion to polymeric materials
US6677242B1 (en) * 2000-08-12 2004-01-13 Applied Materials Inc. Integrated shallow trench isolation approach
US6830977B1 (en) * 2000-08-31 2004-12-14 Micron Technology, Inc. Methods of forming an isolation trench in a semiconductor, methods of forming an isolation trench in a surface of a silicon wafer, methods of forming an isolation trench-isolated transistor, trench-isolated transistor, trench isolation structures formed in a semiconductor, memory cells and drams
US6500728B1 (en) * 2002-05-24 2002-12-31 Taiwan Semiconductor Manufacturing Company Shallow trench isolation (STI) module to improve contact etch process window
US20030236004A1 (en) * 2002-06-24 2003-12-25 Applied Materials, Inc. Dechucking with N2/O2 plasma
JP2004221545A (ja) * 2002-12-26 2004-08-05 Tokyo Electron Ltd プラズマエッチング方法
US7354834B2 (en) * 2003-06-04 2008-04-08 Dongbu Electronics Co., Ltd. Semiconductor devices and methods to form trenches in semiconductor devices
US7339253B2 (en) * 2004-08-16 2008-03-04 Taiwan Semiconductor Manufacturing Company Retrograde trench isolation structures
US7427458B2 (en) * 2005-06-30 2008-09-23 Lam Research Corporation System and method for critical dimension reduction and pitch reduction
KR100649034B1 (ko) * 2005-09-21 2006-11-27 동부일렉트로닉스 주식회사 씨모스 이미지 센서의 제조방법
US8120094B2 (en) * 2007-08-14 2012-02-21 Taiwan Semiconductor Manufacturing Co., Ltd. Shallow trench isolation with improved structure and method of forming
US20090311868A1 (en) * 2008-06-16 2009-12-17 Nec Electronics Corporation Semiconductor device manufacturing method
US9917003B2 (en) * 2013-06-28 2018-03-13 Taiwan Semiconductor Manufacturing Co., Ltd. Trench liner passivation for dark current improvement

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4214946A (en) * 1979-02-21 1980-07-29 International Business Machines Corporation Selective reactive ion etching of polysilicon against SiO2 utilizing SF6 -Cl2 -inert gas etchant
JPS62286229A (ja) * 1986-06-04 1987-12-12 Matsushita Electric Ind Co Ltd ドライエツチング方法
US5616513A (en) * 1995-06-01 1997-04-01 International Business Machines Corporation Shallow trench isolation with self aligned PSG layer
US5792706A (en) * 1996-06-05 1998-08-11 Advanced Micro Devices, Inc. Interlevel dielectric with air gaps to reduce permitivity
US5843226A (en) * 1996-07-16 1998-12-01 Applied Materials, Inc. Etch process for single crystal silicon
US5882982A (en) 1997-01-16 1999-03-16 Vlsi Technology, Inc. Trench isolation method
US5948701A (en) * 1997-07-30 1999-09-07 Chartered Semiconductor Manufacturing, Ltd. Self-aligned contact (SAC) etching using polymer-building chemistry
US6020091A (en) * 1997-09-30 2000-02-01 Siemens Aktiengesellschaft Hard etch mask
US6190955B1 (en) * 1998-01-27 2001-02-20 International Business Machines Corporation Fabrication of trench capacitors using disposable hard mask
CN1219328C (zh) * 1998-02-19 2005-09-14 国际商业机器公司 具有改善了注入剂的场效应晶体管及其制造方法
EP0942330A1 (en) * 1998-03-11 1999-09-15 Applied Materials, Inc. Process for depositing and developing a plasma polymerized organosilicon photoresist film

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7169682B2 (en) 2004-01-29 2007-01-30 Sharp Kabushiki Kaisha Method for manufacturing semiconductor device
JP2008192759A (ja) * 2007-02-02 2008-08-21 Tokyo Electron Ltd エッチング方法、エッチング装置及び記憶媒体
US8187980B2 (en) 2007-02-02 2012-05-29 Tokyo Electron Limited Etching method, etching apparatus and storage medium

Also Published As

Publication number Publication date
WO2001026142A1 (en) 2001-04-12
US6342428B1 (en) 2002-01-29
EP1157411A1 (en) 2001-11-28

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