JP2003509783A5 - - Google Patents

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Publication number
JP2003509783A5
JP2003509783A5 JP2001524242A JP2001524242A JP2003509783A5 JP 2003509783 A5 JP2003509783 A5 JP 2003509783A5 JP 2001524242 A JP2001524242 A JP 2001524242A JP 2001524242 A JP2001524242 A JP 2001524242A JP 2003509783 A5 JP2003509783 A5 JP 2003509783A5
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001524242A
Other versions
JP2003509783A (ja
Filing date
Publication date
Application filed filed Critical
Priority claimed from PCT/US2000/025485 external-priority patent/WO2001020784A1/en
Publication of JP2003509783A publication Critical patent/JP2003509783A/ja
Publication of JP2003509783A5 publication Critical patent/JP2003509783A5/ja
Pending legal-status Critical Current

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JP2001524242A 1999-09-15 2000-09-15 クロック発生器および双方向クロック・ピン構成を有する多重クロック集積回路 Pending JP2003509783A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15409899P 1999-09-15 1999-09-15
US60/154,098 1999-09-15
PCT/US2000/025485 WO2001020784A1 (en) 1999-09-15 2000-09-15 Multi-clock integrated circuit with clock generator and bi-directional clock pin arrangement

Publications (2)

Publication Number Publication Date
JP2003509783A JP2003509783A (ja) 2003-03-11
JP2003509783A5 true JP2003509783A5 (ja) 2007-11-08

Family

ID=22549996

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001524242A Pending JP2003509783A (ja) 1999-09-15 2000-09-15 クロック発生器および双方向クロック・ピン構成を有する多重クロック集積回路

Country Status (9)

Country Link
US (1) US6639422B1 (ja)
EP (1) EP1212835B1 (ja)
JP (1) JP2003509783A (ja)
KR (1) KR100755247B1 (ja)
CN (1) CN1196266C (ja)
AU (1) AU7495600A (ja)
DE (1) DE60034581T2 (ja)
MX (1) MXPA02002581A (ja)
WO (1) WO2001020784A1 (ja)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100414867B1 (ko) * 2001-12-29 2004-01-13 주식회사 하이닉스반도체 저잡음 내장형 클럭생성기를 구비한 마이크로 컨트롤러 및그를 탑재한 시스템
US7676712B2 (en) 2002-01-18 2010-03-09 Mentor Graphics Corporation System and method of clocking an IP core during a debugging operation
US6650163B1 (en) * 2002-08-08 2003-11-18 International Business Machines Corporation Clock generator for integrated circuit
US7489362B2 (en) 2003-03-04 2009-02-10 Broadcom Corporation Television functionality on a chip
US7532648B2 (en) * 2003-08-14 2009-05-12 Broadcom Corporation System and method using an I/O multiplexer module
US7284170B2 (en) 2004-01-05 2007-10-16 Texas Instruments Incorporated JTAG circuit transferring data between devices on TMS terminals
CN100334521C (zh) * 2004-02-28 2007-08-29 鸿富锦精密工业（深圳）有限公司 时钟管理系统及方法
US7519111B2 (en) * 2004-03-15 2009-04-14 Texas Instruments Incorporated Apparatus and method for providing system and test clock signals to an integrated circuit on a single pin
US7555670B2 (en) * 2005-10-26 2009-06-30 Intel Corporation Clocking architecture using a bidirectional clock port
CN100397381C (zh) * 2006-07-12 2008-06-25 北京中星微电子有限公司 一种复用管脚工作模式的自动切换装置
EP2062064A1 (en) * 2006-08-31 2009-05-27 Nxp B.V. Multi-clock system-on-chip with universal clock control modules for transition fault test at speed multi-core
US8327199B1 (en) * 2010-03-05 2012-12-04 Altera Corporation Integrated circuit with configurable test pins
CN103246631B (zh) * 2013-05-16 2016-01-13 北京工业大学 一种用于提高管脚使用率的管脚复用方法及电路
US10318370B2 (en) * 2016-03-25 2019-06-11 Seiko Epson Corporation Circuit device, physical quantity detection device, oscillator, electronic apparatus, vehicle, and method of detecting failure of master clock signal

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4293870A (en) 1980-01-31 1981-10-06 Rca Corporation Circuit arrangement for multiplexing an input function and an output function at a single terminal
US4761567A (en) * 1987-05-20 1988-08-02 Advanced Micro Devices, Inc. Clock scheme for VLSI systems
JPH02119425A (ja) * 1988-10-28 1990-05-07 Nec Corp 双方向バッファ回路
JPH04123117A (ja) * 1990-09-13 1992-04-23 Nec Corp クロック切替回路
US5495422A (en) 1993-10-12 1996-02-27 Wang Laboratories, Inc. Method for combining a plurality of independently operating circuits within a single package
US5596765A (en) 1994-10-19 1997-01-21 Advanced Micro Devices, Inc. Integrated processor including a device for multiplexing external pin signals
US5752077A (en) 1995-05-15 1998-05-12 Motorola, Inc. Data processing system having a multi-function input/output port with individual pull-up and pull-down control
KR0146544B1 (ko) * 1995-05-25 1998-11-02 김광호 다수개의 스위칭 수단을 가지는 다용도 패드를 구비한 반도체 메모리장치
WO1997003444A1 (en) 1995-07-10 1997-01-30 Xilinx, Inc. System comprising field programmable gate array and intelligent memory
US5686844A (en) * 1996-05-24 1997-11-11 Microchip Technology Incorporated Integrated circuit pins configurable as a clock input pin and as a digital I/O pin or as a device reset pin and as a digital I/O pin and method therefor
IES80917B2 (en) * 1997-12-15 1999-06-30 Tellabs Research Limited Clocking in electronic circuits

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