JP2003347544A - Field effect semiconductor device and manufacturing method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To form a thick side wall oxide film in a state where thickness of a gate insulating film is suppressed on a field effect semiconductor device and a manufacturing method of the device. <P>SOLUTION: A gate electrode 3 is worked and at least one type of element selected from among fluorine, chlorine, bromine, iodine, phosphorus, arsenic, boron, indium, antimony, gallium, oxygen, silicon, germanium, BF<SB>2</SB>, argon, krypton and xenon is introduced to a sidewall of the gate electrode 3. Then, the side wall is oxidized. <P>COPYRIGHT: (C)2004,JPO

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect type semiconductor device and a method of manufacturing the same, and more particularly, to a polymetal (POLY-M) having a polycrystalline Si / WN / W structure.
The present invention relates to a field effect type semiconductor device characterized by a gate electrode side wall oxidation step having at least a polycrystalline Si layer such as an ETAL) structure as a component, and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, there has been a demand for miniaturization and high-speed operation of silicon semiconductor devices. In response to such demands, there has been a reduction in the resistance of a gate electrode, one of which is polycrystalline Si / WN. / DRAM (Dynamic Random Access Memory) using an FET having a gate electrode of a polymetal structure of / W has been studied. Here, a conventional polymetal gate FET will be described with reference to FIG. I do.

FIG. 4 is a schematic sectional view of a polymetal gate FET which has been studied in the past. A gate oxide film 33 is provided on a p-type silicon substrate 31 with an element isolation insulating film 32 interposed therebetween. On oxide film 33, n-type polycrystalline Si layer 35, WN layer 3
6, and a gate electrode 34 made of a W film 37 is formed;
On the gate electrode 34, an SiN film 38 serving as a protective film is provided. In the DRAM, a capacitor is connected to the n-type source region 41, and a drain bus line (both not shown) is connected to the n-type drain region 40.

In such an FET, the gate electrode 3
4, side wall oxidation is performed in an oxidizing atmosphere to oxidize the side wall of the polycrystalline Si layer 35 to form a side wall oxide film 39, and the polycrystalline S
The edge of the i-layer 35 is rounded.

[0005] If such side wall oxidation is not performed, an electric field concentration occurs between the polycrystalline Si layer 35 constituting the gate electrode 34 and the n-type drain region 40, and the GIDL (Gate I
nused Drain Leakage Curr
ent), a large amount of current flows, the off-state current of the transistor increases, and the problem of gate leakage tends to occur. Therefore, a certain amount of oxide film is formed on the side wall, and the edge of the polycrystalline Si layer 35 is rounded.
It is necessary to weaken the electric field.

[0006]

However, when the side walls are to be oxidized to be thick with the miniaturization of the element, the oxide film goes under the gate electrode, and the thickness of the gate oxide film 33 also increases. This phenomenon has become a serious problem in DRAMs, particularly DRAMs comprising polymetal gate FETs.

Therefore, an object of the present invention is to form a thick sidewall oxide film while suppressing an increase in the thickness of a gate insulating film.

[0008]

FIG. 1 is a block diagram showing the principle of the present invention. Referring to FIG. 1, means for solving the problem in the present invention will be described.
Reference numeral 5 denotes a semiconductor substrate and a barrier layer such as WN. Referring to FIG. 1, in order to achieve the above object, the present invention provides a method of manufacturing a field effect type semiconductor device, in which, after processing a gate electrode 3, fluorine, chlorine, bromine, iodine,
At least one element selected from the group consisting of phosphorus, arsenic, boron, indium, antimony, gallium, oxygen, silicon, germanium, BF ₂ , argon, krypton, and xenon is introduced, and then sidewall oxidation is performed.

As described above, by introducing the growth oxidizing element 9 which promotes oxidation to the side wall of the gate electrode 3, the introduced damage and / or the effect of accelerating the oxidation of the element itself are obtained.
Since the sidewall oxide film 8 can be formed in a short time, an increase in the thickness of the gate insulating film 2 in the oxidation step can be suppressed.

In this case, the step of introducing the multiplying oxidizing element 9 is as follows.
An ion implantation step, a step of exposing the gate electrode 3 to plasma containing the oxidizing element 9, or a step of exposing the gate electrode 3 to an atmosphere of the oxidizing element 9 ionized by ECR (electron cyclotron resonance) or an electron beam. In the case of ion implantation, 1 × 10 ¹³ to
It is desirable to introduce a 1 × 10 ¹⁵ dose element.

Further, according to the present invention, in the field effect type semiconductor device, at least one of chlorine, bromine, iodine, argon, krypton, and xenon is contained in the polycrystalline silicon layer 4 constituting the gate electrode 3. It is characterized by containing an element. In the case of chlorine, chlorine of 5 × 10 ¹⁸ cm ⁻³ or more is used in order to distinguish it from chlorine inevitably introduced in association with a hydrochloric acid treatment or an etching step using a chlorine-based gas.

As described above, in the polycrystalline Si constituting the gate electrode 3, chlorine, bromine, iodine, argon, krypton,
By including at least one element of xenon, an increase in the thickness of the gate insulating film 2 can be suppressed when the sidewall oxide film 8 is formed.

Further, according to the present invention, in a field effect type semiconductor device, a polycrystalline silicon layer 4 constituting a gate electrode 3 and a good conductor having better conductivity than silicon provided above the polycrystalline silicon layer 4 are provided. Layer 6, for example, both W, Ti silicide, Co silicide and other good conductor layers 6 are coated with chlorine, fluorine, bromine, iodine, phosphorus, arsenic, boron, indium, antimony, gallium, oxygen, silicon, germanium, argon. , Krypton, and xenon. In addition, in the case of chlorine, chlorine of 5 × 10 ¹⁸ cm ^-3 or more is used in order to distinguish it from chlorine inevitably introduced accompanying a hydrochloric acid treatment or an etching step using a chlorine-based gas, and silicon. In this case, in order to distinguish from the case where the good conductor layer 6 is a simple silicide, the silicon concentration in the good conductor layer 6 has a distribution that decreases from the side to the inside.

As described above, when the side wall oxide film 8 is formed by increasing the thickness of the gate insulating film 2 by including the above-described elements in the polycrystalline silicon layer 4 constituting the gate electrode 3, Can be suppressed, and in the resulting configuration:
The same element is also contained in the good conductor layer 6.

Further, according to the present invention, in a field effect type semiconductor device, a gate protection insulating film 7 formed on a gate electrode 3 and a polycrystalline silicon layer 4 forming the gate electrode 3 are provided.
Are characterized by containing at least one element of fluorine, chlorine, bromine, iodine, oxygen, silicon, germanium, argon, krypton, and xenon. In the case of oxygen or silicon, at least one of the oxygen concentration and the silicon concentration in the gate protection insulating film 7 is inward from the side to distinguish it from a simple gate protection insulating film 7 such as a SiN film or a SiO ₂ film. Have a distribution that decreases as one goes to.

As described above, by including the above-described elements in the polycrystalline Si constituting the gate electrode 3, an increase in the thickness of the gate insulating film 2 is suppressed when the sidewall oxide film 8 is formed. In the resulting structure, the same element is also contained in the gate protection insulating film 7.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring now to FIG. 2, a description will be given of a manufacturing process of a polymetal gate FET according to a first embodiment of the present invention. Referring to FIG. 2A, first, an element isolation insulating film 12 is formed on a p-type silicon substrate 11, and then the thickness is reduced by wet oxidation.
For example, a gate oxide film 13 having a thickness of 3.5 nm is formed, and then an amorphous Si layer 14 having a thickness of, for example, 70 nm is deposited by a CVD method, and then P is ion-implanted to be n-type. . In this case, for example, oxidation is performed in a 750 ° C. steam atmosphere generated by flowing and burning H ₂ gas and O ₂ gas at a flow ratio of 1: 1.

Next, the WN layer 15 having a thickness of, for example, 5 nm and the thickness of, for example, 40 n
After sequentially depositing a W layer 16 having a thickness of m, an SiN film 17 having a thickness of, for example, 200 nm is deposited using a plasma CVD method, and then the SiN film 17 to the gate oxide film 13 are etched by dry etching. The gate electrode 18 having a width of, for example, 0.13 μm is formed. In the deposition step of the SiN film 17 or the annealing step after the above-described ion implantation, the amorphous Si layer 14 is formed.
Is converted into a polycrystalline Si layer 22.

Next, as shown in FIG. 2B, F (fluorine) ions 19 are, for example, 5 keV
Is implanted into the side wall of the gate electrode 18 at a dose of 1 × 10 ¹³ to 1 × 10 ¹⁵ cm ⁻² with the acceleration energy of The dose is the dose actually introduced into the side wall of the gate electrode 18. At this time, since the ion implantation is performed while rotating the p-type silicon substrate 11, the F atoms are formed on both side surfaces of the gate electrode 18. 20 are injected.

The implantation angle in this case depends on the ion species, ie, F
Amorphous S in which ions 19 form gate electrode 18
It is sufficient that the angle is equal to or less than the angle α injected into the tip of the i-layer 14, but it is desirable that the angle be as large as possible from the viewpoint of the ion implantation efficiency.

Referring to FIG. 2C, RTA (Rapid Thermal Ann)
eal) method, in an oxidizing atmosphere of H ₂ O / H ₂ / N ₂ , at 800 to 1200 ° C., for example, 800 ° C.
Is performed to form a sidewall oxide film 21 of 10 nm or less, preferably 3 to 5 nm on the exposed side surface of the amorphous Si layer 14.

The upper limit of the oxidation temperature in this case is W layer 1
The lower limit is determined by the minimum temperature at which the oxidation reaction is completed in a practically possible time. The upper limit of the thickness of the sidewall oxide film 21 is a range in which the thickness of the gate oxide film 13 is not significantly increased, that is, a range that does not affect the transistor characteristics. Here, the film thickness is a film thickness on a Si wafer serving as a test piece.

Thereafter, as in the prior art, an ion implantation step for forming source / drain regions, a heat treatment step for activating the implanted ions, a step for forming a via for an ohmic electrode, and an n-type The basic configuration of the DRAM is completed through a process of forming a drain bus line connected to the drain region, a process of manufacturing a capacitor connected to the n-type source region via a via, and the like.

As described above, in the first embodiment of the present invention, prior to the side wall oxidation step for rounding the edge of the polycrystalline Si layer 22 forming the gate electrode 18, the side wall of the amorphous Si layer 14 is formed. Atom 20 that promotes oxidation
Is implanted, it is possible to perform the oxidation process under conditions that do not significantly increase the thickness of the gate oxide film 13. This is because the oxidation speed of the side wall of the amorphous Si layer 14 can be increased by the damage caused by the implantation of the F ions 19 and the oxidation promoting action of the F atoms 20 itself.

Next, with reference to FIG. 3, a description will be given of a manufacturing process of the polymetal gate FET according to the second embodiment of the present invention. First, as in the first embodiment, an element isolation insulating film 12 is formed on a p-type silicon substrate 11 and then wet-oxidized to reduce the thickness to, for example, 3 as in the first embodiment. .5
A gate oxide film 13 having a thickness of, for example, 70 nm is formed using a CVD method.
After the layer 14 is deposited, P is ion-implanted to be n-type.

Next, the WN layer 15 having a thickness of, for example, 5 nm and the thickness of, for example, 40 n
After sequentially depositing a W layer 16 having a thickness of m, an SiN film 17 having a thickness of, for example, 200 nm is deposited using a plasma CVD method, and then the SiN film 17 to the gate oxide film 13 are etched by dry etching. The gate electrode 18 having a width of, for example, 0.13 μm is formed.

Referring to FIG. 3B, after the p-type silicon substrate 11 is loaded into a vacuum apparatus for performing magnetron plasma processing, fluorine gas (F ₂ ) is introduced into the vacuum apparatus, and the pressure is set to 0.01 Pa to 0.01 Pa. 1
0 Pa, for example, 0.5 Pa, and a negative voltage within 1 kV from the back surface of the p-type silicon substrate 11, for example, -20.
Almost at the same time as applying the substrate bias so as to be 0 V, 200 to 2000 W, for example, between parallel plate electrodes,
Discharge is caused by applying 500 W RF (13.56 MHz) power, and F is applied for about 10 seconds to 3 minutes.
Exposure to the plasma 23 causes the side walls of the gate electrode 18 to be doped with 1 × 10 ¹⁹ to 1 × 10 ²² cm ⁻³ of F atoms 20. In this case, the doped F atoms 20 are distributed so that the concentration decreases from the side surfaces of the gate electrode 18 and the SiN film 17 to the depth of the gate structure, and the distribution width is 5 to 10 nm from the surface, and the maximum is 20 nm. About 30 nm.

Referring to FIG. 3 (c), after performing a wet or dry cleaning treatment, H ₂ O / H ₂ / H is again formed by the RTA method in the same manner as in the first embodiment. 8 in an oxidizing atmosphere consisting of N ₂
An oxidation treatment is performed at 00 to 1200 ° C., for example, 800 ° C., and a 10 nm
Hereinafter, the sidewall oxide film 21 of 3 to 5 nm is preferably formed.

Although the embodiments of the present invention have been described above, the present invention is not limited to the configurations and conditions described in the embodiments, and various changes can be made. For example, in the above-described first embodiment, F ions are implanted into the side wall of the gate electrode. However, the present invention is not limited to F ions. A halogen element such as chlorine, bromine or iodine, or oxygen may be used.

The elements to be implanted are not limited to halogen elements or oxygen, but boron, phosphorus, arsenic, indium, antimony, gallium, silicon, germanium, BF ₂ , and argon, which promote oxidation by causing implantation damage. , Krypton, xenon, etc., among them, argon, krypton,
A rare gas element of xenon is empirically desirable.

When these elements are implanted, if the light element is oxygen or less, 3-20 keV, for example, 5
With an acceleration energy of keV, for a relatively heavy element such as silicon, 5 to 50 keV, for example, 10 keV
V may be implanted.

Further, in the second embodiment described above, but is generating F plasma by introducing F ₂ gas, the gas to be introduced is not limited to the F ₂ gas,
ArF, KrF, and XeF may be used.

Further, the plasma is not limited to the F plasma, but includes fluorine, chlorine, bromine, iodine, phosphorus, arsenic, and the like.
It may be introduced by plasma irradiation containing the elements boron, indium, antimony, gallium, oxygen, silicon, germanium, BF ₂ , argon, krypton, and xenon.

Specifically, chlorine (Cl ₂ ), KrCl,
XeCl, bromine (Br ₂ ), ArBr, KrBr, Xe
A gas such as Br, iodine (I ₂ ), ArI, KrI, or XeI may be introduced.

Further, the introduced gas is not limited to one kind of element, and a mixed gas of a plurality of elements may be used. Further, if necessary, a mixed gas with a diluent gas may be used. Is also good. In this case, the concentration distribution of the element to be introduced can be changed by controlling the partial pressure of the introduced gas or mixed gas or controlling the discharge voltage, and typically, the concentration at the surface of the polycrystalline Si layer is reduced. 1
It can be changed from × 10 ¹⁹ to 1 × 10 ²² cm ⁻³ .

In the above-described second embodiment, the RF power is applied to generate plasma. However, the present invention is not limited to the RF power. Alternatively, a discharge may be caused to generate plasma.

Although not mentioned in the second embodiment, the amorphous Si layer may be etched during plasma irradiation.
It is desirable to appropriately perform a surface treatment of the amorphous Si layer such as forming a thin oxide film of about 2 to 3 nm by using an oxidation treatment or a sidewall formation step.

The method of introducing the element is not limited to the ion implantation method and the plasma treatment. The gate electrode may be irradiated with the ionized element using an ion source such as ECR, Irradiated elements may be irradiated using a beam.

In each of the above embodiments, the heat treatment for oxidation is performed by the RTA method.
Furnace (heating furnace), not limited to TA method
May be used. In the case of a furnace, 700
What is necessary is just to perform in the range of -900 degreeC.

In each of the above embodiments, W
Since the layer was exposed, an H ₂ O / H ₂ / N ₂ atmosphere in which only the amorphous Si layer could be selectively oxidized was used as the oxidizing atmosphere, but the exposed surface of the W layer was previously covered with a SiN film or the like. In this case, the oxidizing atmosphere may be at least a condition under which the amorphous Si layer is oxidized. When the side wall of the W layer is coated in advance, in the gate patterning step, after patterning up to the WN layer, a side wall made of a SiN film is formed on the side wall of the gate structure, and then the amorphous Si layer is etched. Just do it.

In each of the above embodiments, the polymetal gate having the polycrystalline Si / WN / W structure has been described. However, the high melting point metal constituting the polymetal gate electrode is not necessarily required to be W. Without Ti, Ta, Nb,
Mo, TiN, TaN, or NbN may be used. Further, as the polymetal gate, a polycrystalline Si / WSi / WN / high melting point metal structure or the like may be used.

Further, the gate electrode is not limited to a polymetal gate, but may be applied to a gate electrode having a polycide structure in which a TiSi layer or a CoSi layer is provided on a polycrystalline Si layer.

In each of the above embodiments, the
SiN film as a gate protection insulating film provided on a gate electrode
Is used, but is not limited to the SiN film.
iO _TwoA film may be used, or a SiN film
And SiO_TwoA stacked film of films may be used.

In each of the above embodiments, the semiconductor substrate is a p-type silicon substrate and the n-channel FE
Although the case where T is formed has been described, the same applies to the case where a p-channel FET is formed on an n-type silicon substrate. Further, the target on which the FET is formed does not need to be the substrate, and the well formed on the substrate is formed. It goes without saying that the area may be used.

In each of the above embodiments, D
Although the description has been made on the premise of the RAM, the present invention is not limited to the DRAM, but is applied to FETs for various uses.

In each of the above embodiments, a silicon semiconductor device has been described. However, the present invention is not limited to a silicon semiconductor device, and may be applied to a semiconductor device containing at least Si as a main component such as a SiGe semiconductor device. Applicable.

Here, the detailed features of the present invention will be described again with reference to FIG. 1 again (Appendix 1) After processing the gate electrode 3, fluorine, chlorine, bromine, iodine, phosphorus, arsenic, boron, indium, antimony, gallium, oxygen, silicon, germanium, BF ₂ , argon, krypton,
A method for manufacturing a field-effect semiconductor device, comprising introducing at least one element of xenon, and thereafter performing sidewall oxidation. (Supplementary Note 2) The method of manufacturing a field-effect semiconductor device according to Supplementary Note 1, wherein the step of introducing the element is an ion implantation step, and the element is introduced at a dose of 1 × 10 ¹³ to 1 × 10 ^15. . (Supplementary Note 3) The method for manufacturing a field-effect semiconductor device according to Supplementary Note 1, wherein the step of introducing the element is a step of exposing the gate electrode 3 to plasma containing the element. (Supplementary Note 4) The method for manufacturing a field-effect semiconductor device according to Supplementary Note 1, wherein the step of introducing the element is a step of exposing the gate electrode 3 to the ionized elemental atmosphere. (Supplementary Note 5) A field-effect-type semiconductor device characterized in that the polycrystalline silicon layer 4 constituting the gate electrode 3 contains at least one element of bromine, iodine, argon, krypton, and xenon. (Supplementary Note 6) A field-effect-type semiconductor device characterized in that at least a side surface of the polycrystalline silicon layer 4 constituting the gate electrode 3 contains chlorine of 5 × 10 ¹⁸ cm ⁻³ or more. (Supplementary Note 7) The polycrystalline silicon layer 4 constituting the gate electrode 3 and the Si provided above the polycrystalline silicon layer 4
Fluorine, bromine,
Iodine, phosphorus, arsenic, boron, indium, antimony,
A field-effect semiconductor device comprising at least one of gallium, oxygen, germanium, argon, krypton, and xenon. (Supplementary Note 8) Polycrystalline silicon layer 4 constituting gate electrode 3 and Si provided above polycrystalline silicon layer 4
5 × 10 ¹⁸ cm for both the better conductive layer 6 having better conductivity
A field-effect semiconductor device comprising ^-3 or more chlorine. (Supplementary Note 9) Polycrystalline silicon layer 4 forming gate electrode 3 and Si provided above polycrystalline silicon layer 4
A field effect type wherein both the good conductive layers 6 having higher conductivity contain silicon and the silicon concentration in the good conductive layers 6 decreases from the side to the inside. Semiconductor device. (Supplementary Note 10) Fluorine, chlorine, bromine, iodine, germanium, argon, krypton, xenon are formed on both the gate protection insulating film 7 formed on the gate electrode 3 and the polycrystalline silicon layer 4 forming the gate electrode 3. A field-effect semiconductor device comprising at least one of the following elements: (Supplementary Note 11) Both the gate protective insulating film 7 formed on the gate electrode 3 and the polycrystalline silicon layer 4 forming the gate electrode 3 contain oxygen or silicon, and
A field effect semiconductor device, wherein the concentration of at least one of oxygen and silicon in the gate insulating film 2 decreases from the side to the inside.

[0048]

According to the present invention, when oxidizing to make the edge of the polycrystalline Si layer constituting the gate electrode round,
Since ions are implanted in advance in the sidewalls of the gate electrode in order to increase oxidation, the thickness of the gate insulating film does not become so large as to affect the device characteristics in the oxidation step, whereby the GIDL and the off-state current are reduced. This greatly contributes to higher speed and higher performance of highly integrated semiconductor devices such as DRAMs.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a basic configuration of the present invention.

FIG. 2 is an explanatory diagram of a manufacturing process according to the first embodiment of the present invention.

FIG. 3 is an explanatory diagram of a manufacturing process according to a second embodiment of the present invention.

FIG. 4 is a schematic sectional view of a conventional polymetal gate FET.

FIG. 5 is a schematic cross-sectional view of a conventional polymetal gate FET when a sidewall oxide film is thickened.

[Explanation of symbols]

1 semiconductor substrate 2 Gate insulating film 3 Gate electrode 4 Polycrystalline silicon film 5 Barrier layer 6 Good conductor film 7 Gate protective insulating film 8 Side wall oxide film 9 Proliferating oxidation elements 11 p-type silicon substrate 12 Element isolation insulating film 13 Gate oxide film 14 Amorphous Si layer 15 WN layer 16 W layer 17 SiN film 18 Gate electrode 19 F ion 20 F atom 21 Side wall oxide film 22 Polycrystalline Si layer 23 F plasma 31 p-type silicon substrate 32 Element isolation insulating film 33 Gate oxide film 34 Gate electrode 35 Polycrystalline Si layer 36 WN layer 37 W layer 38 SiN film 39 Side wall oxide film 40 n-type drain region 41 n-type source region

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI theme coat ゛ (Reference) H01L 27/088 H01L 29/58 G 27/108 29/44 S 29/41 29/423 29/49 F term (Reference) 4M104 AA01 AA03 BB01 BB13 BB29 BB39 BB40 CC05 DD37 DD43 DD56 DD65 DD74 DD78 DD80 DD83 DD86 DD89 EE05 EE14 EE17 FF06 FF13 FF14 GG16 HH14 HH20 5F048 AA07 AB01 AC01 AC03 BB01 BA05 BB01 BA05 BB05 BB01 BF56 BF63 BJ07 5F083 AD01 GA06 JA39 JA40 PR12 PR36 PR37 5F140 AA00 AA24 AC32 BA01 BA05 BD05 BE07 BF04 BF11 BF18 BF20 BF21 BF22 BF25 BF27 BF30 BF38 BG08 BG12 BG20 BG22 BG28 BG31 BG32 BG30 BG30 BG30

Claims (5)

[Claims] After the gate electrode is processed, fluorine, chlorine, bromine, iodine, phosphorus, arsenic, boron, indium, antimony, gallium, oxygen, silicon, germanium, BF ₂ , argon, krypton, A method for manufacturing a field-effect semiconductor device, comprising introducing at least one element of xenon, and thereafter performing sidewall oxidation. 2. A field-effect semiconductor device, wherein a polycrystalline silicon layer forming a gate electrode contains at least one element selected from bromine, iodine, argon, krypton, and xenon. 3. A field-effect-type semiconductor device characterized in that at least a side surface of a polycrystalline silicon layer forming a gate electrode contains chlorine of 5 × 10 ¹⁸ cm ⁻³ or more. 4. A method of manufacturing a semiconductor device comprising: a polycrystalline silicon layer constituting a gate electrode; and a good conductor layer having a higher conductivity than silicon provided above the polycrystalline silicon layer, wherein fluorine, bromine, iodine, phosphorus, and arsenic are provided. , Boron, indium, antimony, gallium, oxygen, germanium, argon, krypton,
A field-effect-type semiconductor device comprising at least one element of xenon. 5. A semiconductor device comprising: a gate protection insulating film formed on a gate electrode; and a polycrystalline silicon layer forming the gate electrode, wherein fluorine, chlorine, bromine, iodine, germanium, argon, krypton, and xenon are formed. A field-effect semiconductor device comprising at least one kind of element.