JP2003338755A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To perform a connection confirming check for multi-bit in an A/D converter circuit, with high accuracy and at low cost. <P>SOLUTION: The connection confirming test for the multibit in the A/D converter circuit can be performed with high accuracy and at low cost using logic tester, by inputting a digital expected value control signal from outside to the input of a latch circuit on the output side of an A/D converter circuit, and inputting this expected value control signal from the latch circuit into an internal system circuit so as to perform a connection test. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a test circuit used for a connection confirmation test in an A / D converter circuit.

[0002]

2. Description of the Related Art Conventionally, in a semiconductor integrated circuit 1 shown in FIG. 9 having a built-in A / D converter circuit, the connection between the digital output 100 of the A / D converter circuit 11 and the system circuit 12 inside the chip is checked. The test is conducted. When performing this test, a test is provided that has an expensive mixed-signal tester (performs a digital test while setting analog settings) and that propagates a highly accurate analog level to the input 200 of the A / D converter circuit 11 faithfully. You need a jig.

The reason is that the A / D converter circuit 11
This is because the high-speed operation of the analog part is essential in order to set the analog level of the analog input 200 with the logic part of the system circuit 12 accurately. Further, when the digital output 100 has a large number of bits, the analog level must be extremely accurate in order to check the connection of all bits including the lower bits, so considering noise and errors in measuring equipment and jigs, etc. This is because it is extremely difficult. The digital output 100 of the A / D converter circuit 11 is output from the encoder / successive approximation circuit / latch circuit unit 111 in the A / D converter circuit 11.

[0004]

Since the above-mentioned mixed signal tester is expensive, when constructing a mass production plant as a line, enormous equipment funds are required and it is extremely difficult to recover the equipment funds. Therefore, it is possible to adopt a method that does not use a mixed signal tester. In this method, analog input is performed by the driver of the logic tester. In this case, the error of the analog input is larger than that of the mixed signal tester, and it is hopeless to check the all digital output. In order to avoid this, analog input may be performed using an analog tester, but this has the problem that the logic part cannot be tested.

Therefore, it is common to measure the analog part and the logic part separately, but in this case, the digital output 100 of the A / D converter circuit 11 uses a plurality of external terminals 13 as shown in FIG. Monitor. In this case, there is a problem that it is not possible to check the connection connection confirmation between the digital output 100 and the system circuit 12 from the output branch to the external terminal 13 to the input of the system 12 inside the chip. In order to avoid this, as shown in FIG. 11, the digital output 100 may be branched from the inside of the system circuit 12 and output to a plurality of external terminals 14 without being branched midway. There is a problem that you cannot check everything.

The present invention has been made to solve the above-mentioned conventional problems, and an object thereof is to perform a multi-bit connection confirmation test in an A / D converter circuit with high accuracy and at low cost. It is to provide a semiconductor integrated circuit.

[0007]

Means for solving the problems are as follows. In a semiconductor integrated circuit having an A / D converter circuit built-in, a digital circuit is provided in a latch circuit of an output stage which constitutes the A / D converter circuit at the time of a test. It is characterized by comprising a signal input means for inputting an expected value control signal.

According to the above means, for example, if the digital expected value control signal is generated by a logic tester and is input to the latch circuit of the output stage constituting the A / D converter circuit, the expected value is expected from the latch circuit. A value control signal is output, and these expected value control signals are input to the internal system circuit to perform a connection confirmation test in the A / D converter circuit.

[0009]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration example of a semiconductor integrated circuit according to the first embodiment of the present invention. However, the same parts as those of the conventional example will be described with the same reference numerals. The semiconductor integrated circuit 1 is an A / D converter circuit 1
1 and a system circuit 1 inside the chip for inputting and processing the digital output 100 of the A / D converter circuit 11.
2, the A / D converter circuit 11 is provided with a test circuit 112.

FIG. 2 is a circuit diagram showing a detailed example of the test circuit 112 shown in FIG. In the test circuit 112, the switching circuit 23 is inserted in the connection line for each bit that connects the output of the encoder / successive approximation circuit 21 and the input of the latch circuit 22, and the input of this switching circuit 23 is output to the encoder / successive comparison circuit 21. A test signal 400 for switching between the side and the side for inputting the expected value control signal 300 is input.

Next, the operation of this embodiment will be described.
In the case of this example, for example, a high-level test signal 400 is input to the switching circuit 23 at the time of testing, the input of the switching circuit 23 is switched to the input side of the expected value control signal 300, and then the expected value is output from a logic tester (not shown). A control signal, in this example, a 4-bit expected value that does not change with time is generated and input to the switching circuit 23. These expected values are input to the latch circuit 22 through the switching circuit 23, which is latched by the latch circuit 22, and the digital output 201,
It is output to the system circuit 12 as 202, 203 and 204.

The system circuit 12 processes and outputs the input digital outputs 201, 202, 203, 204. These output values are monitored by the logic tester, and the expected value corresponding to the initially generated expected value control signal is calculated. A / D is determined by determining whether or not is output.
A connection test between the converter circuit 11 and the system circuit 12 is performed.

When the test signal 400 is low level,
The switching circuit 23 is adapted to input the output side of the encoder / successive approximation circuit 21, and performs a normal operation of converting an analog signal into a digital signal.

According to the present embodiment, the digital expected value control signal 300 generated from the logic tester is input to the latch circuit 22 instead of using the digital output output from the encoder / successive approximation circuit 21 during the test.
Since it is possible to directly input the signal, it is not necessary to use an analog signal as a test signal, and a connection test between the A / D converter circuit 11 and the system circuit 12 can be performed by a logic tester. Therefore, even if the connection test has a large number of bits, the test signal input to the lower bits is the digital expected value control signal 300. Therefore, the connection test of all bits including the lower bits can be performed with high accuracy using only the logic tester. It can be done easily. Therefore, it is possible to easily confirm the connection between the A / D converter circuit 11 and the internal system circuit 12 without introducing an expensive mixed signal tester into the mass production factory. Further, the connection test between all the output bits of the A / D converter circuit 11 and the system circuit 12 can be easily performed only with the logic tester. Due to the above various effects, the quality of the semiconductor integrated circuit 1 can be improved at low cost. Furthermore, since the logic tester is used, the system circuit 1
It is also possible to test logic parts such as 2.

FIG. 3 is a block diagram showing a configuration example of a semiconductor integrated circuit according to the second embodiment of the present invention. However, the same parts as those of the conventional example will be described with the same reference numerals. The semiconductor integrated circuit 1 of this example includes a test circuit 113, and a test signal 400 and a clock signal 500 are input to the test circuit 113.

FIG. 4 is a block diagram showing a detailed example of the test circuit 113 shown in FIG. Test circuit 11 of this example
3 also includes a switching circuit 2 in the connection line for each bit that connects the output of the encoder / successive approximation circuit 21 and the input of the latch circuit 22.
3 is inserted, and the input of the switching circuit 23 is set to the encoder /
A test signal 400 for switching between the output side of the successive approximation circuit 21 and the expected value control signal 600 output by the output bit switching circuit 24 is input. The output bit switching circuit 24 inputs the clock signal 500, and the signal waveform charts (C) to (C) of FIG.
An expected value control signal 600 having the same shape as that shown in (F) and changing in time series is output.

Next, the operation of this embodiment will be described.
In the case of this example, at the time of testing, for example, a clock signal 50 as shown in FIG.
0 is input to the output bit switching circuit 24 of the test circuit 113. After that, a high-level test signal 400 as shown in FIG. 5A is input to the switching circuit 23, and the input of the switching circuit 23 is switched to the expected value control signal 600 side.

As a result, the expected value control signal 600 that changes in time series is latched by the latch circuit 22 through the switching circuit 23, and this latch signal is output by the digital output 301 as shown in FIGS. 302, 303, 304
Is output to the system circuit 12. System circuit 1
2 is the input digital output 301, 302, 303,
304 is processed and outputted, but these output values are monitored by the logic tester, and it is judged whether or not the expected value control signal 600 initially generated changes as expected, whereby the A / D converter circuit is obtained. A connection test between 11 and the system circuit 12 is performed.

When the test signal 400 is at low level, the switching circuit 23 inputs the output side of the encoder / successive approximation circuit 21, and the normal operation of converting an analog signal into a digital signal is performed. .

According to this embodiment, the clock signal 500
, The expected value control signal 60 that changes in time series is input.
Since the output bit switching circuit 24 that generates 0 is provided, the test signal 400 and the clock signal 5
The connection test between the A / D converter circuit 11 and the system circuit 12 can be performed only by inputting two kinds of signals of 00 to the test circuit 113, and it suffices to provide two test terminals on the chip. The test terminals can be minimized. In addition, the expected value control signal 600
Since the value of changes, it is possible to reliably check for problems such as short circuits and open connections. Other effects are similar to those of the first embodiment shown in FIG.

FIG. 6 is a block diagram showing a configuration example of a semiconductor integrated circuit according to the third embodiment of the present invention. However, the same parts as those of the conventional example will be described with the same reference numerals. The semiconductor integrated circuit 1 includes an A / D converter circuit 11
And the digital output 1 of this A / D converter circuit 11
System circuit 12 inside the chip for processing by inputting 00
In particular, the A / D converter circuit 11 includes a test circuit 114.

FIG. 7 is a block diagram showing a configuration example of the test circuit 114 shown in FIG. However, the same parts as those of the conventional example will be described with the same reference numerals. Also in the test circuit 114 of this example, the switching circuit 23 is inserted in the connection line for each bit that connects the output of the encoder / successive approximation circuit 21 and the input of the latch circuit 22, and the input of the switching circuit 23 is input to the encoder / successive comparison circuit. The test signal 400 for switching between the output side of 21 or the expected value control signal 600 output by the expected value setting circuit 25 is input. The expected value setting circuit 25 receives the output bit switching signals 801 and 802 as shown in (B) and (C) of the signal waveform chart of FIG. 8 and inputs (D) to (G) of the signal waveform chart of FIG. The expected value control signal 600 having the same shape as that shown in () and changing in time series is output.

Next, the operation of this embodiment will be described.
In the case of this example, at the time of testing, for example, from a logic tester (not shown), as shown in FIGS. 8 (B) and 8 (C),
The output bit switching signals 801 and 802 of the type are input to the expected value setting circuit 25 of the test circuit 114. After that, FIG.
A high-level test signal 400 as shown in (A) is input to the switching circuit 23, and the input of the switching circuit 23 is switched to the expected value control signal 600 side.

As a result, the expected value control signal 600 that changes in time series is latched by the latch circuit 22 through the switching circuit 23, and this latch signal is output by the digital output 301 as shown in FIGS. 302, 303, 304
Is output to the system circuit 12. System circuit 1
2 is the input digital output 301, 302, 303,
Although 304 is processed and output, these output values are monitored by the logic tester, and it is determined whether or not the expected value control signal 600 originally generated changes the value as expected, whereby the A / D converter circuit is obtained. A connection test between 11 and the system circuit 12 is performed.

According to this embodiment, the test signal 400 and the two kinds of output bit switching signals 801, 80 are tested at the time of testing.
By simply inputting 2 to the test circuit 114, a connection test between the A / D converter circuit 11 and the system circuit 12 can be performed, the number of test terminals can be reduced, and other effects are shown in FIG. It is similar to the second embodiment.

The present invention is not limited to the above-described embodiments, and can be implemented in various other modes in specific configurations, functions, actions, and effects without departing from the scope of the invention. .

[0027]

As described above in detail, according to the present invention, the digital expected value control signal is directly input to the input of the latch circuit constituting the output section of the A / D converter circuit without performing the analog input. By inputting, a multi-bit connection confirmation test in the A / D converter circuit can be performed with high accuracy and at low cost.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration example of a semiconductor integrated circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a detailed example of the test circuit shown in FIG.

FIG. 3 is a block diagram showing a configuration example of a semiconductor integrated circuit according to a second embodiment of the present invention.

FIG. 4 is a block diagram showing a detailed example of the test circuit shown in FIG.

5 is a time chart showing a waveform of an expected value control signal output from the output bit switching circuit shown in FIG.

FIG. 6 is a block diagram showing a configuration example of a semiconductor integrated circuit according to a third embodiment of the present invention.

7 is a block diagram showing a detailed example of the test circuit shown in FIG.

8 is a time chart showing a waveform of an expected value control signal output from the expected value setting circuit shown in FIG.

FIG. 9 is a block diagram showing a configuration example of a semiconductor integrated circuit incorporating a conventional A / D converter circuit.

FIG. 10 is a diagram illustrating a connection test example of a semiconductor integrated circuit including a conventional A / D converter circuit.

FIG. 11 is a diagram illustrating another wiring connection test example of a semiconductor integrated circuit including a conventional A / D converter circuit.

[Explanation of symbols]

1 Semiconductor integrated circuit 11 A / D converter circuit 12 system circuit 21 Encoder / Successive approximation circuit 22 Latch circuit 23 Switching circuit 24 output bit switching circuit 25 Expected value setting circuit 112, 113, 114 test circuit

─────────────────────────────────────────────────── ─── Continued Front Page (51) Int.Cl. ⁷ Identification Code FI Theme Coat (Reference) H01L 27/04 F Term (Reference) 2G132 AA00 AA11 AD01 AD06 AE14 AG01 AG08 AH04 AK07 AK15 AK22 AL11 5F038 DF03 DF17 DT04 DT10 DT17 EZ20 5J022 AA02 AC04 BA01 CE08

Claims (6)

[Claims] 1. A semiconductor integrated circuit having a built-in A / D converter circuit, comprising signal input means for inputting a digital expected value control signal to a latch circuit at an output stage which constitutes the A / D converter circuit during a test. A semiconductor integrated circuit comprising: 2. The signal input means has a signal switching circuit inserted between connection lines for each bit connecting the encoder / successive approximation circuit of the A / D converter circuit and the latch circuit of the subsequent stage, When the test signal is input from the outside, the signal switching circuit switches the input from the output side of the encoder / successive approximation circuit to the terminal side to which the expected value control signal is input. The semiconductor integrated circuit described. 3. The signal input means includes, from the outside, a signal switching circuit inserted between connection lines for each bit connecting the encoder / successive approximation circuit of the A / D converter circuit and a latch circuit at the subsequent stage. A signal generation circuit that generates the expected value control signal based on an input clock signal, and the signal switching circuit outputs the input to an encoder / successive comparison circuit when a test signal is input from the outside. 2. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is switched from a side to a terminal side to which the expected value control signal is input. 4. The semiconductor integrated circuit according to claim 3, wherein the expected value control signal generated from the signal generating circuit changes its level in time series. 5. The signal input means includes a signal switching circuit inserted between connection lines for each bit connecting the encoder / successive approximation circuit of the A / D converter circuit and a latch circuit of a subsequent stage, and an external signal switching circuit. A bit conversion circuit for converting a small number of bit signals to be input into the expected value control signal of multiple bits, and the signal switching circuit, when a test signal is input from the outside, inputs the encoder / sequential signal 2. The semiconductor integrated circuit according to claim 1, wherein the output side of the comparison circuit is switched to the terminal side to which the expected value control signal is input. 6. The semiconductor integrated circuit according to claim 5, wherein the expected value control signal generated from the bit conversion circuit changes its level in time series.