JPH07225260A - Semiconductor device with inspection function - Google Patents

Abstract

PURPOSE:To clarify the generation mechanism of pseudorandom inspection data which inspects a circuit to be inspected and to execute an inspection efficiently by a method wherein the pseudorandom inspection data is generated by using output data of the circuit to be inspected. CONSTITUTION:An inspection control circuit 11 starts an inspection by a TEST signal 13, a CLK signal 9 is given to an inspection circuit 7, and initial-value data is output to a timing adjustment circuit 3 by an initial-value input 5. The initialvalue data is input to an inspection-data generation circuit 4 from the circuit 3 by a signal 9, and it is output to a circuit 1, to be inspected, through an internal bus 2 as first inspection data. The circuit 1 outputs an operated result to the bus 2, and the circuit 3 takes into the operated result as next inspection data again by the signal 9. After that, inspection data which is generated automatically according to the signal 9 in the same manner is given to the circuit 1, and the inspection is repeated by the set number of times required to detect a fault. Then, final data of the circuit 3 is input to a judgment circuit 8 from an inspection result output 6, it is compared with a criterion value, 0 is output in a normal state, and 1 is output in an abnormal state.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device with an inspection function having a function of self-inspecting (self-testing) the semiconductor device itself such as a large-scale integrated circuit. The present invention relates to a semiconductor device with an inspection function having a function of performing a self-inspection or connecting an inspection circuit body to the periphery of the semiconductor device to inspect.

[0002]

2. Description of the Related Art Recently, semiconductor devices such as VLSI have been scaled up,
Higher densities have progressed, and functions have been enhanced and high functionality has been realized, but on the other hand, circuits have become complicated and
The amount of inspections for judging a manufactured semiconductor device as normal has become enormous, which requires a considerable amount of time and effort.
For example, a binary 32-bit output multiplier is a 16-bit x 2-input, 32-bit output combinational logic circuit, which includes an AND gate, an OR gate, an inverter (NOT gate), a buffer,
Although it is a functional LSI with a total number of gates of about 6500 such as switches, the inspection of such a multiplier is not a functional inspection that inputs sample data, and all data must be checked. In this case, since it becomes data the total number of the 2 ^32, also it takes inspection time of approximately 85.9 seconds as executing one data at 50 MHz, also be previously hold this much data is realistic uneconomical the Absent. Therefore, in order to solve this kind of problem, JP-A-60-6
Built-in test circuit with built-in test circuit with various configurations including 8824
A so-called self-test type semiconductor device called st, BIST) has been proposed and has been implemented by each company since the latter half of the 1980s. The basic idea is to provide circuit inspection, not functional inspection, that is, inspection data for detecting an abnormality in the circuit pattern. These are, for a semiconductor device to be inspected, given a combination of input data as an inspection data pattern, and compare the result obtained by the inspection with a normal result to judge the pass / fail of the device. However, the additional circuit for testing is 5-10% of the chip area.
, And the problem of increased test time causes a high chip cost.

Therefore, if the inspection data pattern of the semiconductor device is a pseudo-random pattern, it is effective for circuit inspection (Yuzo K .: Research trends in VLSI testability design technology; Information Processing, No. 12, Vol. 30, PP.1451 to 1460 (1989)), it is also proposed to generate a pseudo-random pattern as the inspection data pattern and use the pseudo-random pattern as the inspection data for inspection. . In this case, the test circuit outputs a series of test results according to the test signal (test data) through each output line, and if there is a failure in the test circuit,
Since the inspection result also has a signal different from the expected value, a judgment circuit is used to compare and judge normality / abnormality. In a large-scale logic combination circuit, the inspection result is several hundred kbits,
Since a huge amount of memory is required to sequentially compare these with the expected value, the inspection result is compressed to several bits using a compression circuit and then compared. In the conventional self-test, the test mechanism is built into the chip, so how compact the additional circuit for testing can be is an important point. However, it is still necessary to incorporate both the pseudo random number generation circuit for generating the inspection data pattern and the circuit for compressing / determining the inspection result (see, for example, FIG.
5) The area occupied by the inspection circuit is still large, the inspection data amount is large, and the inspection time is long, which is still insufficient to solve this problem.

[0004]

Therefore, it is an object of the present invention to improve the productivity of the semiconductor device by minimizing the area occupied by the inspection circuit in the semiconductor device and efficiently performing the self-test of the semiconductor device. is there. Therefore, the inventors consider that it is possible to compensate for the above-mentioned drawbacks of the semiconductor device only by providing a simple test data generating means for generating pseudo-random test data for performing a more complete test of the circuit to be tested, Attention was paid to the fact that this inspection data is generated by the inspection data generating means using the output data of the circuit to be inspected. This is very advantageous in that the semiconductor device can be self-inspected without providing a complicated inspection circuit inside the semiconductor device.

Therefore, an object of the present invention is to provide a semiconductor device with an inspection function which clarifies a mechanism for generating pseudo-random inspection data and can inspect the semiconductor device more efficiently.

[0006]

According to the present invention, in order to generate test data (test signal) for a circuit under test, the test result of the circuit under test is used as feedback input (feedback), and data conversion is performed with a simple configuration. To generate inspection data. That is, the output (c) of the circuit to be inspected in FIG. 1 is input to the inspection data generating means (inspection circuit).
(d), and the inspection data for the next step from this signal (d)
Generate (a). With such a configuration, the inspection data generating means (inspection circuit) also serves as the test result compression circuit required in the conventional self-test, and it is possible to reduce the test hardware. Become.

Therefore, in order to solve the above-mentioned problems, the configuration of the present invention is such that in a semiconductor device with an inspection function, which comprises an inspection circuit for self-inspecting an inspected circuit, all output data of the inspected circuit The inspection circuit is provided with an inspection data generating means for automatically generating an output pattern, which is used as an input pattern and becomes inspection data for the circuit to be inspected, from the input pattern, and is different for each input pattern of the inspection circuit. The output patterns correspond to each other one by one, and the time-series correlation coefficient of the inspection data repeatedly generated is sufficiently small.

According to the second aspect of the invention, in a semiconductor device with an inspection function, which comprises an inspection circuit for self-inspecting an inspected circuit, all the output data y of the inspected circuit are used to obtain the inspection data z. The inspection circuit is provided with inspection data generating means for automatically generating and feedback-inputting to the inspected circuit, wherein the output data y of the inspected circuit is mapped to the initial or previous input data x. The function when it is regarded as a conversion is within the range of possible values of x and y.

[Mathematical formula-see original document] y = f (x), which is a one-to-one correspondence function or an upward function, and a function for generating inspection data by the inspection circuit is

[Mathematical formula-see original document] A one-to-one correspondence function represented by z = g (y) or an upward function, and a composite function,

## EQU00003 ## z = g (f (x)) = h (x) has discontinuity, and two points x _{1 that} are very close to each other in the interval of x
And at x ₂ ,

## EQU4 ## It is characterized in that it has a property of | h (x ₁ ) −h (x ₂ ) |> | x ₁ −x ₂ | and is a function on z.

According to the configuration of the invention related to the above invention, the inspection circuit is a wiring in which the arrangement of the input signal line for inputting the input pattern and the output signal line for outputting the output pattern is rearranged. As a characteristic or another configuration, an inverter is provided in a part or all of the wiring and the output side of the inspection circuit.

According to another aspect of the invention, the inspection circuit has a data expansion means or a data compression means when the number of output signal lines of the inspection circuit is different from the number of input signal lines. Further, the data expansion means is a wiring that double-connects a part of the input data signal line to one of the output signal lines, and the data compression means includes a part or all of the input data signal line. Input
It is a logical circuit that reduces the number of output signal lines, such as an AND circuit, OR circuit with multiple inputs, EX-OR circuit, or NOT circuit.

Another characteristic configuration is that the inspection circuit has the inspection data generating means, a first selector for selecting any one of the output lines, and a second selector for selecting the connection of the inverter. Selecting means for selecting the circuit to be inspected between a plurality of circuits to be inspected, and switching the circuit to be inspected by the selecting means to inspect; and the inspection circuit is a part of the semiconductor device. As an example, it may be formed with a monolithic structure.

Further, the inspection data generating means is
The semiconductor device is characterized in that it has a timing circuit which is connected as an external device of the semiconductor device at the time of inspection and is responsible for the timing of transmission / reception of inspection data and inspection result data inside the semiconductor device. In addition, when it is clear that the inspection data to be output has a circuit configuration in which it converges to at least one specific value, any two signal lines of the inspection circuit are exchanged or any one of the signal lines is replaced. One of the characteristic configurations is that an inverter is provided in the configuration to reduce the correlation coefficient. In addition, the connection of the wiring has a function of shifting the output data by 1 bit and shifting the least significant bit to the most significant bit or the most significant bit to the least significant bit, and the self-check is performed. A characteristic configuration is also provided with means for comparing the output data after execution n times (n> 0) with a predetermined reference value to determine whether the circuit under test is correct or not.

As described above, the means for achieving the object of the present invention has various characteristic configurations.

[0014]

When the output data of the circuit to be inspected, which is the inspection target, is directly input to the inspection data generating means and a non-periodic function conversion is performed, the output inspection data becomes a pseudo random pattern. This pseudo-random data is fed back to the circuit to be inspected to continue the self-test, and the test is performed up to the number of times that it is known that all the tests are completed in advance to check for any abnormality. A function with an aperiodic solution can be realized by simply changing various wiring connections, inverters, etc.
The aperiodicity is also supported by chaos theory. Since the output of the circuit under test is fed back to the test input and used, it is not necessary to prepare the test data pattern in advance.

If the feedback system as a whole maintains aperiodic conversion, pseudo-random is guaranteed, so that the input / output relationship of the circuit under test is usually nonlinear and pseudo-random. It is possible to achieve the object even if the function conversion on the side is a simple non-linear conversion or a linear conversion in some cases. Since the input / output relationship of the circuit under test is known in advance, the function conversion on the test circuit side can be selected in advance, and it is possible to use a simple circuit such as wiring reconnection and an inverter to achieve the function conversion suitable for the purpose. carry out.

If the number of input and output data signal lines of the target circuit under test does not match the number of test signal lines, and if the number of output signal lines decreases, use a logic circuit to match the number of signal lines. If the inspection information is not lost and the number of bits is large, one input signal line is made to correspond to a plurality of output signal lines and the number of signal lines is expanded to keep the inspection data random. Alternatively, in the case where one test circuit cannot handle it, a configuration is added in which the connection to the output is switched by the selector to support different test circuits.

Since these inspection circuits are formed on the same chip, the inspection for each semiconductor device can be performed without delay. Further, when the inspection circuit is provided outside, the chip area is further reduced and the chip cost is reduced.

[0018]

EXAMPLES The present invention will be described below based on specific examples. The self-test of the present invention is hereinafter referred to as a feedback type self-embedded test (FB-BIST). (First Embodiment) FIG. 1 is a block diagram showing the concept of a basic configuration of the present invention. For one circuit under test 1 of a semiconductor device, a test circuit 7 is connected to an internal bus (input / output data bus). 2 shows a configuration in which the inspection data is generated by the inspection data generation circuit 4 via the timing adjustment circuit 3 using the output data of the circuit to be inspected and is again input to the circuit to be inspected from the internal bus 2. The inspection circuit 7 is composed of a timing adjustment circuit 3 that takes in the output data of the circuit to be inspected and an inspection data generation circuit 4 that converts the output of the circuit into a function. The timing adjustment circuit 3 uses the initial value input (S
The first data is generated by the CAN-IN) 5, thereafter the inspection data is automatically generated by the output data from the circuit to be inspected, and the inspection is sequentially repeated according to the clock signal 9. The inspection result output 6 is output to the determination circuit 8 for each inspection.

As a concrete example of the circuit under test 1, a binary 16-bit, 2-input, 32-bit output multiplier 200 shown in FIG. 2 is shown. Even in the case of normal operation and inspection, enable circuits 210, 211, ..., 2 which perform a latch function from the internal bus 2 (shown as a 32-bit bus as an input side 202 and an output side 201) to the multiplier 200 are provided.
Data is input to 25, 226, 227, ..., 241 and is taken into the multiplier 200 by the signal of the input side control line MUL. The input terminals of the multiplier 200 are AI _{00 to} AI ₁₅ and BI _00.
~ BI ₁₅ has 16-bit a and b inputs, and the inputs a and b are multiplied (a × b), and the result is binary 32.
Bit output Outputs as OUT _{00 to} OUT ₃₁ . This output is also enable circuits 250, 251, 252, ..., 2
At 81, it is latched by the instruction of the output side signal line MUL and is output to the 32-bit internal bus 201 (also 202).

The inspection circuit 7 generates inspection data based on the operation result data output from the multiplier 200.
First, the timing adjustment circuit 3 of the inspection circuit 7 has selectors 300, 301, ..., 331 and flip-flops (hereinafter referred to as FFs) 350 connected in series as shown in FIG. 351 ... 3
80, 381, and signal line (SCAN-IN) for introducing clock signal (CLK), control signal (SEL) and initial value from the outside
And the signal lines D _{00 to} D ₃₁ are connected to the input / output data bus 202, from which the output of the multiplier 200 is taken. Selectors 300 to 331 are signal lines SE
When L is Lo, the value of D _{00 to} D ₃₁ is output to FF, and when it is Hi, the value of FF is output as it is. Further, the output terminal Q of the FF is directly supplied to the lines E _{00 to} E to the inspection data generating circuit 4.
₃₁ is output. This signal line SEL is used to input data from SCAN-IN when setting the initial value.

The original data for inspection data generation output from the timing adjustment circuit 3 is input to the inspection data generation circuit and the original data is function-converted. In this case, in order to realize the aperiodic and upward function conversion of the inspection circuit, the function used for the conversion is realized by the circuit configuration including the wiring and the inverter shown in FIG. In FIG. 4, EI _{00 to} EI ₃₁ are input from the timing adjustment circuit 3, and A _{00 to} B ₁₅ are output as inspection data and connected to the multiplier 200. Out of output bits A ₀₀
Inverters 450 to 480 are provided in B ₁₄ to B ₁₄ .

The meaning of the conversion of the circuit of FIG. 4 is as follows. Since the original data input to this circuit is the output value of the previous multiplier 200 except for the initial value, as can be seen from the configuration of the multiplier in FIG. 2, the input a and the input b are input in parallel. Therefore, the output becomes complicated. Then, the arrangement of the original data bits is sorted and rearranged as B ₀₀ , A ₀₀ , ..., B ₁₅ ,, A ₁₅ , and the inspection result output obtained when the multiplier is regarded as a mapping (function) is shown in FIG. The function after array as shown is y
= X (output = input) is replaced to approximate a function, and the result is converted by -2 times (y = -2x-1 [-1 <x <0], y = -2x +1 [0 <x <1
], X and y are normalized expressions to [-1,1] (shown in FIG. 6), and the signals other than B ₁₅ bits are inverted and converted by the inverter as a disturbance.

The following is a description of what should be considered because the above circuit is a circuit that realizes an aperiodic function. First, in order to perform the inspection by this feedback input (feedback) system algorithm, the inspection mechanism must satisfy the following three conditions (see FIG. 1). Condition The inspection data (c) of the next step generated by using the inspection output (a) is a random pattern. If the condition check output (a) is abnormal, that is, if a result different from normal is output, the check signal (c) of the next step generated using (a) is also normal. Have different values. Condition Once a different inspection output (a) is output, the correct signal must not be returned until the inspection is completed in the process of repeating feedback. The condition is a condition that the abnormality detected in the middle is not overlooked in the process of passing through the inspection circuit many times thereafter, that is, a condition that the error oversight probability is low enough to pass the inspection. The condition is a condition that the inspection data generating circuit and the circuit to be inspected are regarded as one combined feedback system.

That is, the inspection data generating circuit may be constructed so as to satisfy this condition. Then, to solve this problem, we apply mathematical chaos theory. Chaos originally represents a state of chaos, and is a general term for complicated and unpredictable time fluctuations produced by nonlinear and deterministic systems. The features of the chaotic system are as follows: Feature (1) The trajectory of the solution is completely different for a slight change in the initial value. (Orbital instability) Features (2) Long-term prediction is impossible. (Long-term unpredictability) Features (3) There is no clear periodicity of solution. (Aperiodicity of solution) (Hideki Takayasu: Chaos and Fractals; Journal of Acoustical Society of Japan, No.49, Vol.1, pp.40-44 (1993)).

Therefore, by utilizing these characteristics of chaos,
The feedback system obtained by synthesizing the circuit under test and the test data generating circuit constitutes a test data generating circuit that becomes a chaotic system as a whole, and if the initial value is appropriately selected, the circuit under test is selected. The input of becomes a random pattern and satisfies the conditions of the previous section. In addition, the condition is satisfied because the slight difference in the output increases as the step progresses. Furthermore, since long-term prediction is impossible, it can be considered that the autocorrelation of the test data will be lost as the test step progresses, and once different test data is output, it will return to a normal signal again. The probability that it will happen is very low. For the above reasons, it is effective for circuit inspection that the feedback system inspection mechanism constitutes a chaotic system.

The means for forming a circuit for generating inspection data based on the chaos theory will be described below by taking the Lorenz equation as an example. The Lorentz equation is

(5) dx / dt = σ (y−x) dy / dt = ρx−y−xz dz / dt = −βz + xy (σ, ρ, β are positive constants) (Thomas S. Park and Leon O. Chua: Prac
tical Numerical Algorithms for Chaotics Systems;
Springer Verlag) found that this equation is chaotic. Here, the parameters are σ = 10, β = 3 /
Fig. 7 shows the numerical solution when 8 and ρ = 28. It can be seen that the trajectory of the numerical solution has a complicated solution that circulates around two unstable equilibrium points + q and -q without diverging according to the transition of time (feature (3)). This orbital solution is very unstable, and the trajectory of the solution becomes completely different with only slight disturbance (feature (1)). Due to the rounding error in the numerical solution of the computer, the variables x, y, and z can be obtained only with finite accuracy, so it is impossible to predict the trajectory after a long time in the continuous time system (feature (2)).

In FIG. 7, the point x _n on the orbit that traverses the plane S parallel to the plane z = 0 for the nth time including the straight line connecting the two equilibrium points + q and -q is the plane S (the straight line Neighborhood)
_Let x _{n + 1 be a} point that crosses x _n (n = 1, 2, ...)
Is projected on a straight line connecting + q and −q. The thus obtained mapping to x _n → x _{n + 1} is the Lorentz map f shown in FIG. 8 (a). The Lorentz map is an example of Poincaré cross section in the chaos theory of mathematics. 8 (a) is a completely non-linear function, and since it is difficult to realize this in an actual circuit, consider a simplified one as shown in FIG. 8 (b). This function is a non-linear mapping by dividing a linear function with a slope of 2.

FIG. 8 (b), which is a simplified mapping of FIG. 8 (a).
In, if the initial value x _{0 is} slightly different, then n =
FIG. 9 shows x _n when increased to 1, 2, .... Considering that the Lorentz map was originally obtained from the solution of the Lorentz equation, this map preserves the features (1), (2), (3). Therefore, when the initial value x ₀ is slightly changed, f ⁿ after the mapping f is repeated n times
(x) becomes completely different as n increases. Ie x
_{If 0} is ₀ and two points that are very close are x ₁ and x ₂ , | f (x
₁ ) −f (x ₂ ) | >> | x ₁ −x ₂ | Of course, in the case of FIG. 8 (b), the features are approximately stored.

From the viewpoint of feedback in FIG. 9, the repetition of the mapping f forms the curved spiral shown in FIG. 10 (a). The vertical axis f (x) -horizontal axis n has a random pattern (FIG. 10 (b)).
That is, as shown in FIG. 11 (a), f ⁿ (x ₀ ) is represented by a straight line y =
It means that you are feeding back to x again at x. Comparing this with FIG. 1, when there is a relation of y = x between the input and output of the circuit to be inspected, the inspection circuit having the mapping f as the input / output characteristic is constructed and the feedback system (that is, FB-BIST) It can be seen that a chaotic system can be generated approximately by constructing it. As shown in FIG. 12, such an inspection circuit can be connected by shifting the output by 1 bit (that is, doubled) with respect to the input of the inspection circuit and inserting the upper bit of the input into the lower bit of the output. The test circuit is easily configurable.

However, in a general logic circuit, it is not always possible to form the proportional relationship y = x between the input and output of the circuit under test. Rather, there is no such function as proportionality alone. In such a case, the input / output of the circuit under test can be regarded as having a kind of randomness. Even in this case, if the following conditions are established, the feedback system can be a chaotic system and the inspection can be performed. (1) The feedback system including the inspection circuit and the circuit under inspection has at least one aperiodic solution.
(Corresponding to the condition) (2) Input-output mapping x → y of the circuit under test has a one-to-one correspondence,
Alternatively, there is a many-to-one correspondence within a range in which the probability of missing an error is low enough to pass the inspection. (Corresponding to the condition) (3) The mapping x → y of the input and output of the circuit under test is the mapping onto y. (Corresponding to the condition) Even if the conditions (4) and (3) are not established, the value of each signal line of the output y changes to such an extent that the inspection can be sufficiently used. (Corresponding to the condition)

This means that, as shown in FIG. 11B, the integrated configuration of the circuit under test and the inspection circuit is regarded as one integrated conversion, and this integrated conversion is a chaotic system. In other words, if the inspection data is input to the circuit under test and the inspection result is output and converted by the inspection data generation circuit to generate new inspection data, if the new inspection data is a pseudo random pattern, the inspection is performed. Is possible.

The fact that such an inspection circuit has a pseudo-random pattern is confirmed as follows. That is, the correlation coefficient C between one inspection data and the next inspection data (this is the output data of the circuit to be inspected by the previous inspection data) is obtained and compared as follows.

[Equation 6] However,

## EQU00007 ## r = x ₁ x ₂ + x ₂ x ₃ + ... + x _n-1 x _n + x _n x ₁

S ₁ = x ₁ + x ₂ + ... + x _n

S ₂ = x ₁ ² + x ₂ ² + ... + x _n ²

Here, n is the number of check stages and x _i is the multiplier 20.
Input 0 and a are regarded as one logical value and displayed in hexadecimal.
It is a value obtained by normalizing x 0 to Hex FFFFFFFF to 0 to 1.

If the correlation coefficient C is almost 0, it can be said that these data are random. When the inspection data generating circuit shown in FIG. 4 is used for the multiplier 200 shown in FIG. 2 and the correlation coefficient is obtained at n = 500, C = 0.08≈0.0.
Therefore, the inspection data generated based on the output data of the multiplier 200 is sufficiently random, and it is possible to sufficiently cope with the required number of times of repeated input of inspection data (the number of inspection stages).

As described above, pseudo random is realized by making the configuration of the FB-BIST inspection circuit chaotic. That is, in the configuration according to the present invention, the randomness of the inspection data is guaranteed by the proof of the chaos theory and the correlation coefficient.

The data used in the above correlation coefficient is obtained in the following procedure. That is, the initial data is appropriately determined and given by the configurations of FIGS. 1, 2, and 4, and repeated until all stack (stuck-at) faults and open faults of the binary 16-bit two-input multiplier 200 are detected. This multiplier 20
The relationship between the number of inspection steps (the number of times inspection data is applied) and the number of undetected faults at 0 is as shown in FIG. In the configuration of the multiplier 200 of FIG. 2 and the inspection data generating circuit of FIGS. 2 and 4, it is known in advance that all the failures are detected at the 26th inspection stage, so the actual FB- At the time of BIST, after the clock signal of the 26th stage rises, the inspection result (If the circuit is normal, Hex of Out at the end of Fig. 15)
118D9E1C) is taken into FF and the inspection result output (SCA
From N-OUT) 6, the judgment circuit 8 in FIG.

The multiplier 200 is a 32-bit input 32-bit output combination logic circuit having a function of outputting the multiplication result of the binary 16-bit inputs a and b from the binary 32-bit output Out, and an AND gate. The total number of gates such as gates, OR gates, and inverters is 6500. Naturally, the relationship between input data and output data can be regarded as a complex conversion rather than a proportional relationship. Therefore, the input of the multiplier is b ₀ , a ₀ ,
When the outputs Out ₀ , Out ₁ , ... when inputs 0, 1, ... are input side by side like b ₁ , a ₁ , ... are obtained, the input / output relationship shown in Fig. 5 is obtained. obtain. By doing this, the complicated input-output relationship of the multiplier 200 that is difficult to see becomes clear,
The inspection data generating circuit can be easily formed.

The mapping for generating inspection data is briefly shown in FIG.
1 to provide the inspection data generation circuit 4 of FIG.
Configure as follows. This is a conversion of slope -2, so
As for the circuit configuration, it can be realized by a simple wiring reconnection and an inverter circuit that only shifts one bit higher and passes the NOT gate.

Next, based on the configuration of FIG. 1, the self-test (FB-BIST in the embodiment) of the circuit under test is performed by the multiplier 20 of FIG.
0, the operation performed by the timing adjustment circuit 3 of FIG. 3 will be described. Since the circuit configuration of the circuit under test is known at the design stage as in the conventional self-test, what kind of initial test data should be given to the circuit under test as described above? Whether the output data can be obtained can be obtained by simulation, and it can be known in advance how many times FB-BIST is repeated in the configuration of the present invention to complete all the inspections. In this case, it is known what kind of initial value is given to obtain a result with small correlation, and the characteristics of the inspection circuit are also judged. Therefore, the number of repetitions and the final output data obtained from this simulation become the inspection result of the circuit under test when the circuit under test is normal. Therefore, the data is stored in the inspection control memory (ROM) 12 shown in FIG. In the case of the multiplier 200, the initial value FFFFFFFF, the inspection stage number 26, and the final output 118d9e1c shown in FIG. 15 are stored in the memory 12.

The self-inspection is carried out in the following order. [1] Instruct the TEST signal (13 in Fig. 1) from the outside (Lo → H
By i), the inspection control circuit 11 of the semiconductor device calls the inspection program stored in the inspection control memory 12 to start the inspection. [2] The inspection control circuit 11 controls the following signal lines to set initial values in the inspection circuit 7. (a) SEL ......... The timing adjustment circuit functions as a shift register in the Hi state. Connected to internal bus 2 in Lo state F
F becomes a register. (b) SCAN-IN ... Initial value data is clock signal (CLK) 9
Then, it is sent to the timing adjusting circuit 3. (c) CLK: Generates a pulse clock for the required bits to send data. First, SEL is set to Hi, CLK is supplied, and the initial value data in the inspection control memory 12 is sent to the timing adjustment circuit 3 through SCAN-IN. [3] When the initial value data is set in the timing circuit 3 of the inspection circuit 7, the state of SEL is set to Lo and CLK is input, the inspection data generation circuit 4 and the internal bus 2 are connected, Initial value data from FF (FFFF in the case of the first embodiment)
FFFF) is input to the inspection data generation circuit 4 of FIG. 4 and immediately input to the internal bus 2 as the first inspection data to the multiplier 200 that is the circuit to be inspected. The result is output. [4] When CLK is input to the inspection circuit 7 again, the previous calculation result is taken in the timing adjustment circuit 3 as the next data. Thereafter, second and third inspection data are generated in the same manner, and the inspection data is automatically given to the circuit under test 1 in accordance with the CLK signal 9. [5] CLK signal 9 a predetermined number of times (26 test stages here) sufficient to detect a failure in the circuit under test.
After inputting, the SEL is set to Hi and the final data of the timing adjustment circuit 3 is sent from the inspection result output (SCAN-OUT) 6 to the determination circuit 8 (the final data is not sent from FF.
This can be done by sending some data from SCAN-IN). [6] In response to a judgment execution instruction from the inspection control circuit (not shown), compare with a pre-stored reference value and L if normal
If it is abnormal, Hi is output from the judgment circuit 8.

The above flow is summarized as a flow chart shown in FIG. In this inspection flow, the part that generates the inspection data is not calculated but is immediately obtained by the wiring and the inverter, and the inspection is repeatedly executed by the clock signal, so that the self-inspection can be performed rapidly.
The inspection time can be shortened in the manufacturing process. If the inspection circuit is configured monolithically, an expensive LSI tester is not necessary, and even if the LSI tester is used, the inspection circuit is configured on the evaluation adapter so that the inspection can be performed quickly.

A result of simulating how the inspection is actually performed by the inspection data generating circuit of FIG. 13 is shown. The experimental conditions for the multiplier 200 are as follows: (1) A power supply short fault, a ground short fault, and a disconnection fault are assumed for all gates. Simulated 5650 faults excluding potential equivalent faults out of 13888 total faults
To. (2) Initial value inspection data value of FB-BIST of the present invention x ₀ Experiment 1: Hex 00010001 Experiment 2: Hex 00010002 (3) Conventional 16-bit self-inspection method Initial value Experiment 3: Hex FFFF Experiment 4: Hex 0001 (4 ) Conventional 32-bit self-check method Initial value Experiment 5: Hex FFFFFFFF Experiment 6: Hex 00000001.

The experimental results of the above experiment are shown in FIG. The FB-BIST of the present invention (Experiments 1 and 2) achieved a fault detection rate of 100% considerably faster than the conventional method. In addition, Experiment 3
In Experiment 6, in addition to the inspection data generating circuit, a 32-bit compression circuit is required in each of the additional circuits for testing, and the hardware becomes large. On the other hand, in the FB-BIST of the present invention, since the inspection data can be generated only by the wiring and the inverter, the hardware configuration can be reduced in layout area to about 40% of the conventional method.

(Second Embodiment) Next, the inspection data generating circuit is not limited to the inspection circuit shown in FIG. For example, in FIG.
Indicated by the

The function j = −2i ± 1 can be applied to the multiplier 200 as a check circuit because it can maintain aperiodicity as shown in the first embodiment. In this case, when data arrives at the intersection with the line of j = i, it becomes an infinite loop and loses randomness. Therefore, select an appropriate initial value and keep randomness until this value occurs. , It is applied to the inspection target whose self-test ends during that period. Similarly, even if it has an intersection with the line of j = i, if the correlation coefficient is sufficiently small within the required number of inspection steps, it is effective as an inspection circuit. Therefore, the wiring reconnection shown in FIG. In some cases, the inverter circuit is used as the inspection data generation circuit 4. In FIG. 16, the NOT gate is simply passed through all the bits. This is because if the randomness of the target circuit to be inspected is sufficiently recognized, even if the inspection circuit used has a linear relationship (gradient -1), the inspection circuit and the circuit under inspection shown in Fig. 11 (b) This is because the correlation of the obtained inspection data is similarly sufficiently small because the relationship of 1 is replaced. This slope -1 is simply N for all bits.
It is the easiest to configure because it only has an OT gate.
However, since it cannot be applied to all the inspection objects, it is possible to adopt a configuration in which some bit operations are added as a disturbance if necessary. In any case, if the correlation is obtained and the relationship is sufficiently small, the inspection circuit can handle it. In addition,
It has been found that the inspection circuit configuration according to FIG. 16 can sufficiently deal with the correlation coefficient with respect to the multiplier 200.

(Third Embodiment) The C1355 logic circuit (C1355 bench mark circuit) is a benchmark circuit proposed by IEEE ISCAS '85, which is a combinational logic of 512 total gates, 41 bits input, and 32 bits output. Circuit (F.Brgez an
d H. Fujiwara: A NEUTRAL NETLIST OF 10 Proc. 1985 I
EEE Int.Symp.Circuits and Systems. Kyoto, June 5-7
(1985)). This circuit obtains the input / output relationship of FIG. 17 by arranging the input / output bits in an appropriate order and ranking from Hex0 to Hex 1FFFFFFFFFFFFFFFFFF.

Therefore, by utilizing this characteristic, the inspection data generating circuit outputs y [31: 1] and inputs x as shown in FIG.
It is configured such that y = 2x between [31: 0]. The output side LSBy [0] is connected as a disturbance to x [29] via an inverter. The output y [40:32] was connected to the lower bits x [7: 0] of the input to give a random change. The result of simulating the inspection by this configuration will be shown. The experimental conditions are shown below. (1) It is assumed that all gates have a power supply fault and a ground fault. Simulation of 846 faults out of 1174 total faults excluding potential equivalent faults. (2) Initial inspection data value of FB-BIST of the present invention x ₀ Experiment 1: Hex 1FFFFFFFFFFFFFFFFF1 Experiment 2: Hex 0000000000000000001 (3) Conventional 32-bit self-inspection method initial value Experiment 3: Hex 1FFFFFFFFFFFFFFFFF1 Experiment 4: Hex 0000000000000000001

The experimental results are shown in FIG. From this result, when inspected by the FB-BIST of the present invention, 95% of failures are detected with 400 times of feedback, but the conventional method is
95% failure detection rate is not reached even after 1400 inspection steps. Actually, the experiment was conducted up to about 20,000 times, but the detection rate was 95
% Was not obtained.

(Fourth Embodiment) Although the third embodiment is an example in which the number of input bits is small with respect to the output, the present invention can be similarly applied to the case where the number of input bits is large. However, as a result of the inspection at any stage, if there is a circuit abnormality and different data occurs, the result must be reflected in the input bit, so simply thin out the input bit to determine the number of output bits. It is not possible to configure just to match.
Therefore, as shown in FIG. 20, an appropriate logic circuit 110 such as a decoder is provided for some or all of the input bits to form an output according to the number of output bits. In FIG. 20, the wiring that simply connects the LSBs after passing through the logic circuit 110 is shown, but it goes without saying that a connection that reduces the correlation coefficient may be selected.

(Fifth Embodiment) Further, as shown in FIG. 21, if the selectors 600 and 610 are provided with the required number of bits for the output bits and the output bits have flexibility and are of a general-purpose type, what will happen? It is also applicable to various semiconductor integrated circuits, and a semiconductor device as shown in FIG. 22 can be configured. Figure 2
Since the number of elements increases and the chip area occupies increases with the configuration of 1 as it is, it is not necessary to provide selectors for all bits, and at least the functional unit included in the target semiconductor device is inspected. It is sufficient if the correlation coefficient is small for all the circuits. Therefore, the inspection circuit can be configured as an inspection circuit for a very large scale integrated circuit such as VLSI by adding a few selector circuits. Further, in some cases, it is more effective if a circuit having a small correlation coefficient can be formed in all the target semiconductor devices only by reconnecting the wirings and the circuit configuration by the inverter as shown in FIG. 4 or FIGS. is there.

(Sixth Embodiment) Further, even if such an inspection circuit is not originally provided inside the semiconductor device but provided outside, the same effect can be obtained. That is, L that has been conventionally used
In the SI tester, a probe (evaluation board) with detection terminals is attached to the semiconductor device to be inspected, the inspection data pattern is input from the outside, and the result is also taken out by the probe, and the external device is used. Although the inspection is judged, if the inspection circuit of the present invention is provided on the evaluation board 84 as shown in FIG. 23 or in the form of an adapter (not shown) in the middle of the probe, the circuit inspection is performed.
The inspection can be performed smoothly without the need to give the inspection pattern from the outside. Further, in this case, it is not necessary to provide an inspection circuit inside the semiconductor device, only a circuit for timing with the outside is sufficient, and the purpose can be sufficiently achieved.

By the way, the pattern referred to in this specification refers to a sequence of a series of inspection data, and since it is just like the pattern of image data, the original meaning of the pattern is diverted and used. Does not mean the pattern. Further, in the claims, an upward function is a term in a set theory of mathematics, and a relation (function) between an input x and an output y.
On the other hand, it means a relationship in which any of the values of y can be represented by any x, and in that case, a relationship in which a plurality of x may correspond to one value of y.

Further, the term "chaotic system" does not necessarily mean that it is a chaos or a chaotic state in mathematical theory. That is, when it is completely chaotic, it is guaranteed to be completely random, but it is difficult to realize a circuit that reflects perfect chaos, and in actual use, use an approximate circuit that can be easily realized. Is normal. Since the information is digitized in semiconductor devices and the use range of data is limited, when all the data is exhausted, the original data will always come out, so a completely chaotic state is You can see that it is impossible. Therefore, the meaning of pseudo-random means the same relationship.

[0053]

According to the present invention, a semiconductor device with an inspection function is realized which realizes a self-inspection system as an inspection function of a semiconductor device such as an LSI to which the chaos theory is applied. This method is a method of generating inspection data by automatically setting a feedback system composed of a circuit to be inspected and a inspection data generating circuit as a chaotic system, and executing the inspection automatically. It is a test method based on a completely different concept from the inspection method.
As a result of the failure detection experiment of the 16-bit multiplier using this method, the inspection time is about 25% compared with the conventional method.
Shortened, the additional circuit for testing is about 60 transistors.
% Could be reduced. As described above, the self-inspection of the semiconductor device having the configuration of the present invention is suitable for a semiconductor device such as a large-scale theoretical circuit which is difficult to test.

[Brief description of drawings]

FIG. 1 is a structural explanatory view of a semiconductor device with an inspection function of the present invention.

FIG. 2 is a configuration diagram of a multiplier as an example of a circuit to be inspected that is an inspection target.

FIG. 3 is a block diagram of the timing adjustment circuit of FIG.

4 is a configuration diagram showing an example of a test data generation circuit for the multiplier of FIG.

5 is an explanatory diagram of characteristics when the input / output relations of the multiplier of FIG. 2 are rearranged.

FIG. 6 is an explanatory diagram of a feedback map showing the inspection data generation circuit of FIG.

FIG. 7 is an explanatory diagram showing an example of a numerical solution of the Lorentz equation.

FIG. 8 is an explanatory diagram of a Lorentz map and a simplified Lorenz map.

FIG. 9 is an explanatory diagram of aperiodicity of the map shown in FIG.

FIG. 10 is an explanatory diagram of the concept of FIG. 9.

FIG. 11 is an explanatory diagram illustrating the correspondence between the FB-BIST and the Lorentz map of the present invention.

FIG. 12 is a configuration diagram of a conversion circuit that realizes a simplified Lorentz map.

FIG. 13 is a configuration diagram of an inspection data generation circuit having another configuration for the multiplier of FIG.

FIG. 14 is a simulation result diagram of a multiplier inspection (fault detection rate).

FIG. 15 is a list view of inspection data generation by the inspection circuit of FIG. 4, targeting FIG. 2;

FIG. 16 is a configuration diagram of an inspection data generation circuit according to a second embodiment.

FIG. 17 is an input / output characteristic diagram of the C1355 circuit.

FIG. 18 is a configuration diagram of a test data generation circuit for the C1355 circuit.

FIG. 19 is a simulation result diagram of inspection (fault detection rate) on the C1355 circuit.

FIG. 20 is a configuration diagram of an inspection data generation circuit according to a fourth embodiment.

FIG. 21 is a configuration diagram of an inspection data generation circuit according to a fifth embodiment.

22 is a configuration diagram of a semiconductor device to which the inspection data generation circuit of FIG. 21 is applied.

FIG. 23 is a configuration diagram of a sixth embodiment.

FIG. 24 is a flow chart diagram of self-inspection according to the present invention.

FIG. 25 is an explanatory diagram of a configuration example of a conventional self-inspection method.

[Explanation of symbols]

 1 circuit to be inspected 2 internal bus (input / output data bus) 3 timing adjustment circuit (inspection data generation means) 4 inspection data generation circuit (inspection data generation means) 5 initial value input (SCAN-IN) 6 inspection result output (SCAN- OUT) 7 inspection circuit (inspection data generation means) 8 determination circuit 9 CLK (clock signal) 10 comparator (in determination circuit) 11 inspection control circuit 12 inspection control memory (ROM) 13 TEST signal 21 to 23 selector (selection means) 82 LSI (including an object to be inspected) 83 LSI tester 84 Evaluation board (probe) 110 Logic circuit 200 Multiplier 210-281 Enable circuit 300-331 Selector 350-381 Flip-flop circuit (FF) 400-431 Inspection data generation circuit Output signal line 450-480 Inverter (NOT gate) 511-513 Tested Circuit (different units) 600 selector (first selector) 610 Selector (Second selector)

Claims (15)

[Claims] 1. A semiconductor device with an inspection function, which comprises an inspection circuit for self-inspecting an inspected circuit, wherein all output data of the inspected circuit are input patterns,
The inspection circuit is provided with inspection data generating means for automatically generating an output pattern which is inspection data for the circuit to be inspected from the input pattern, and different output patterns are provided for respective input patterns of the inspection circuit. A semiconductor device with an inspection function, which corresponds to each other and has a sufficiently small time series correlation coefficient of the inspection data generated repeatedly. 2. A semiconductor device with an inspection function comprising an inspection circuit for self-inspecting a circuit to be inspected, wherein inspection data z is automatically generated by using all output data y of the circuit to be inspected. When the inspection circuit is provided with inspection data generating means for feedback-inputting to the inspected circuit, when the output data y of the inspected circuit with respect to the initial or previous input data x is regarded as mapping conversion. Function of
Within the range of possible values of x and y, it is a one-to-one correspondence function represented by y = f (x) or an upward function, and the function of the inspection data generation by the inspection circuit is ## EQU2 ## A one-to-one correspondence function or an upward function represented by z = g (y), and a composite function z = g (f (x)) = h (x) Two points x ₁ that have discontinuity and are very close within the section of x
And x ₂ have a property of | h (x ₁ ) −h (x ₂ ) |> | x ₁ −x ₂ |, which is a function on z. Semiconductor device with inspection function. 3. The inspection circuit is a wiring in which an arrangement of an input signal line for inputting an input pattern to the inspection circuit and an output signal line for outputting an output pattern is rearranged. Semiconductor device with the described inspection function. 4. The semiconductor device with an inspection function according to claim 3, wherein an inverter is provided in a part or all of the wiring and the output side of the inspection circuit. 5. The inspection circuit includes data expansion means when the number m of output signal lines of the inspection circuit is m> n with respect to the number n of input signal lines. 4. A semiconductor device method with an inspection function according to item 4. 6. The inspection circuit has a data compression means when the number m of output signal lines of the inspection circuit is m <n with respect to the number n of input signal lines. 4. A semiconductor device method with an inspection function according to item 4. 7. The semiconductor device with an inspection function according to claim 5, wherein the data expansion means is a wiring that double-connects a part of the input data bit to any one of the output bits. 8. The inspection function according to claim 6, wherein the data compressing means is a logic circuit for inputting a part or all of input data bits and a logic circuit for reducing output bits. Semiconductor device method. 9. The inspection circuit according to claim 3, wherein the inspection data generating means, a first selector for selecting any output line, and a second selector for selecting connection of the inverter are included in the inspection circuit. Semiconductor device with inspection function. 10. Between a plurality of circuits to be inspected and the inspection circuit,
10. The semiconductor device method with an inspection function according to claim 1, further comprising a selection unit for selecting the circuit to be inspected, and switching the circuit to be inspected by the selection unit. 11. The semiconductor device method with an inspection function according to claim 1, wherein the inspection circuit is formed as a part of the semiconductor device in a monolithic structure. 12. The inspection data generating means is connected as an external device of the semiconductor device at the time of inspection, and has a timing circuit in the semiconductor device, which is responsible for the timing of transmission and reception of inspection data and inspection result data. Item 12. A semiconductor device method with an inspection function according to any one of items 1 to 11. 13. When it is clear that the inspection data to be output has a circuit configuration in which it converges to at least one specific value, any two signal lines of the inspection circuit are exchanged or any signal is exchanged. 12. A configuration in which an inverter is provided on the line to reduce the correlation coefficient is set.
A semiconductor device method with an inspection function according to 1. 14. The wired logic circuit has a function of shifting the output data by 1 bit and shifting the least significant bit to the most significant bit or the most significant bit to the least significant bit. The semiconductor device method with an inspection function according to claim 3. 15. A means for comparing the output data after performing the self-inspection n times (n> 0) with a predetermined reference value to determine the correctness of the circuit under test. The semiconductor device method with an inspection function according to claim 1.