JP2003337741A - Data transfer system, its method, and access monitoring device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To monitor a FIFO memory arranged between a memory bus and a memory controller for securing latency within a predetermined time. <P>SOLUTION: When a header is inputted, a byte count of the header is read to be added to a summation counter 54. When reading of the FIFO memory 23 is detected by means of a FIFO reading determination part 58, the byte count of the header is read from a packet data retaining register 55 if a word is a header, and the read value is subtracted from a byte count summation counter 54. In the byte count summation counter 54, a total of the access counter number of requests accumulated in the FIFO memory 23 is monitored. Memory access is restricted so that the value does not exceed a predetermined threshold value. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention comprises a plurality of client devices, a memory shared by the plurality of client devices, and a memory controller for controlling the memory. TECHNICAL FIELD The present invention relates to a data transfer system and method for connecting via a memory, and an access monitor device suitable for use in such a system, and more particularly to a FIFO provided between a memory bus and a memory controller.
Monitor memory and read or write
It relates to the one that can guarantee the latency within a predetermined time.

[0002]

2. Description of the Related Art For example, MPEG (Moving Picture Cod)
ing Experts Group) 2 transport stream is input, video packets and audio packets are separated from this transport stream, image processing is performed on the decoded video data, and OSD (On
Screen Display) Development of image processing chips for superimposing images is in progress. Such an image processing chip has a BitBLT (Bit Blo) for copying an image of an arbitrary source rectangular area to a destination area.
ck Transfer) engine and JPEG (Joint Photographic Experts Group) that processes background images.
Engines etc. are arranged. A large amount of memory is required for processing by these client devices, and the memory is shared by each client device. As a memory for such an image processing chip, an SDRAM (Synchr
onous Dynamic Random Access Memory) is used.

FIG. 13 is a block diagram showing the configuration of a memory control system usable in such an image processing client device.

In FIG. 13, the client device 1
Reference numerals 11, 112, and 113 are devices that access the memory 115, which is a shared resource. For example, in the system that constitutes the image processing chip, the client devices 111, 112, and 113 are processors such as BitBLT engine and JPEG engine. These client devices 111, 112, 113 are
IFO (First-In First-Out) memory 121A, 121
B, 121C and FIFO memories 122A, 122B,
It is connected to the memory bus 110 via 122C, respectively. The memory bus 110 also includes a FIFO memory 1
The memory controller 114 is connected via 23 and 124. The memory controller 114 uses the memory 11
5 is a resource control circuit for controlling read / write of No. 5.

The memory 115 is a resource that can be commonly used by a plurality of client devices 111, 112, 113. As the memory 115, for example, SDRAM
Is used. The SDRAM is capable of continuous data transfer in synchronization with a clock, and when burst transfer is designated, data transfer of a designated number of data can be continuously performed in units of one clock. Here, the memory 115 configured as an SDRAM can transfer 64-bit data in one clock.

The memory bus 110 includes a client device 111, 112, 113 and a memory controller 11.
4 is a bus for transferring data to and from the bus. The memory bus 110 includes client devices 111, 112, 1
A transmission bus 110A for sending data from the 13 side to the memory controller 114 side and client devices 111, 112, 11 for transmitting the data from the memory controller 114 side.
It is composed of a reception bus 110B which receives data on the third side.

Each client device 111, 112,
Between the 113 and the memory bus 110, the FIFO memories 121A, 121B, 121C and the FIFO memory 12 are provided.
2A, 122B, 122C are provided. These FI
The FO memories 121A, 121B, 121C and the FIFO memories 122A, 122B, 122C are provided as buffers. Each client device 111, 112,
Between the 113 and the memory bus 110, the FIFO memories 121A, 121B, 121C and the FIFO memory 12 are provided.
Since 2A, 122B, 122C are provided, each client device 111, 112, 113 can transmit a request and receive data asynchronously with the transfer clock of the memory bus 110.

Further, a FIFO memory 123 and a FI are provided between the memory controller 114 and the memory bus 110.
An FO memory 124 is provided. Memory controller 1
14 and the memory bus 110 between the FIFO memory 1
23 and the FIFO memory 124 are provided,
The memory controller 114 can receive requests and send data asynchronously with the transfer clock of the memory bus 110.

Each client device 111, 112,
A unique device ID is assigned to 113.
Each client device 111, 112, 113 accesses the memory 115 when accessing the memory 115.
The request is transmitted via the transmission bus 110A.
This request has a packet structure.

Client devices 111, 112, 1
All 13 can access the common memory 115. Therefore, a plurality of client devices 111, 112, 113 may simultaneously make requests to the memory 115. Therefore, an arbiter 116 is provided to prevent contention of requests from the client devices 111, 112, 113.

Client devices 111, 112, 1
When the memory 13 accesses the memory 115, first, a request for obtaining the right to use the bus is sent to the arbiter 116. When there are requests from a plurality of client devices, the arbiter 116 arbitrates the requests and returns the grant only to one client device that permits the use of the memory bus 110. Of the plurality of client devices 111, 112, 113,
Only the client device for which the grant has been returned can access the memory 15.

In the case of a memory write request,
A write request is transmitted from the client device 111, 112, 113. This write request is sent to the memory controller 1 via the transmission bus 110A.
Sent to 14. The memory controller 114 causes the client device 11 to respond to the write request.
The write data sent from 1, 112, 113 is written in a desired address of the memory 115.

In the case of a memory read request,
Read requests are transmitted from the client devices 111, 112, and 113. This read request is sent to the memory controller 1 via the transmission bus 110A.
Sent to 14. The memory controller 114 reads data from a desired address of the memory 115 in response to a read request. This read data is transferred from the memory controller 114 via the reception bus 110B, and is received by the client device 111, 112, 113 that transmitted the read request.

As described above, in this system, the client devices 111 and 11 are transmitted via the transmission bus 110A.
Requests are transmitted from 2, 113, and the words of this request are accumulated in the FIFO memory 123 via the memory bus 110.

Here, the clock of the word transferred to the memory bus 110 and the clock of the word to which the memory 115 is accessed by the memory controller 114 are asynchronous, and the FOFO 122 and the FIFO memory 1 are connected.
Reference numeral 23 is a buffer for a word clock transferred to the memory bus 110 and a word clock for accessing the memory 115 by the memory controller 114.

However, if the clock frequency of the word transferred to the memory bus 110 is higher than the clock frequency of the word accessed by the memory controller 114 to the memory 115, the client devices 110, 111, 112. To memory bus 1
Words sent via 10 buses 110A are FI
It is stored in the FO memory 123, and the FIFO memory 123 overflows.

Therefore, as shown in FIG. 14, a FIFO memory remaining amount monitor circuit 125 is provided. This FIFO
The memory remaining monitor circuit 125 allows the FIFO memory 1
The remaining amount of 23 is monitored. Then, the FIFO memory 12
If 3 is about to overflow, FIFO
A stop signal is sent from the memory remaining amount monitor circuit 125 to the arbiter 116 to stop the bus arbitration. As a result, the transmission of the request for accessing the memory 115 from the client devices 111, 112, 113 is stopped, and overflow of the FIFO memory 123 is prevented.

The FIFO memory remaining amount monitor circuit 125 can guarantee the latency of the bus.

That is, the client device 111,
When the requests 112, 113 send the request to the bus and the processing is not guaranteed to be completed within a predetermined latency, the client devices 111, 112, 11
No. 3 cannot move to the next process. Therefore, when the client device 111, 112, 113 sends a request to the memory bus 110, the processing is guaranteed to be completed within a predetermined latency time.

In the case of a write request, a write header word is followed by a write data word, and the write time corresponds to the write data word following the write header word. Therefore,
When the free capacity of the FIFO memory 123 is large, the processing for the request stored in the FIFO memory 123 before that immediately ends, so that the memory access for the request is immediately performed. FIFO memory 1
If the free space of 23 is small, the FIFO memory 2
Since the next process cannot be started until the process for the request stored in 3 is completed, it takes time to access the sent request.

For example, when writing data of 5 words, the client device 111, 112, 113 sends data of 5 words following the word of the header via the transmission bus 110A, and the FIFO memory. It is stored in 123. For accessing the memory 115, one word (64 bits) is accessed in one clock, for example. So to handle this request,
The clock between the memory controller 114 and the memory 115 requires time for 5 clocks.

On the other hand, when writing data of 10 words, the client devices 111, 112, 113 send 10 words of data following the header word via the transmission bus 110A. , FI
It is stored in the FO memory 123. In order to process this request, the memory controller 114 and the memory 11
A clock between 5 and 5 requires 10 clocks.

Thus, in the case of writing, the FIFO
The storage amount of the memory 123 and the processing time have a corresponding relationship. Therefore, from the remaining amount of the FIFO memory 123,
The processing time can be estimated, the remaining amount of the FIFO memory 123 is monitored, and when the FIFO memory 123 is about to overflow, a stop signal is sent to the arbiter 116 to guarantee the latency within a predetermined time.

[0024]

However, as described above, the remaining amount of the FIFO memory 123 is constantly monitored, and the FI
When the remaining amount of the FO memory 123 becomes less than or equal to a predetermined value, it is sufficient to simply send a stop signal to the arbiter 116.
The latency of the memory bus 110 cannot always be guaranteed. This is because the number of words in the write request corresponds to the processing time, but the number of words in the read request is constant regardless of the processing time.

That is, the client devices 111, 1
In the case of a write request sent from 12, 113 to the memory controller 114 side, a word of write data to be written in the memory 115 is sent after the word of the header indicating the write. The FIFO memory 123 stores a write header word and a write data word. Therefore, as the amount of data written to the memory increases, the number of words of data sent after the word of the header also increases, the amount of data stored in the FIFO memory 123 also increases, and the storage amount of the FIFO memory 123 corresponds to the processing time. To do.

On the other hand, at the time of reading, only the word of the header indicating the reading is sent. Therefore, FI
The processing time cannot be known from the accumulated amount in the FO memory 123.

For example, when reading data of 5 words and reading data of 10 words, only one word of the header is sent. On the other hand, the processing time depends on the number of words of data to be read. If the data of 5 words is read, the clock for the clock between the memory controller 114 and the memory 115 requires time of 5 clocks, and if the data of 10 words is read, the memory controller 114 and The clock for the memory 115 requires 10 clocks.

Therefore, for example, the FIFO memory 12
Even if there is a read request for 3 words in 3, if all the requests for 3 words in the FIFO memory 123 are for reading out 5 words, the processing time is (3 × 5 = 15) clocks. On the other hand, if all of these 3 words are for reading out 10 words, the processing takes (3 × 10 = 30) clocks. As described above, in the case of a read request, the processing time is significantly different even if the number of words in the request stored in the FIFO memory 123 is the same.

As described above, in the case of a write request, the storage amount of the FIFO memory 123 and the processing time have a corresponding relationship, but in the case of a read request, F
There is no relationship between the storage amount of the IFO memory 123 and the processing time. Therefore, the latency of the memory bus 110 cannot always be guaranteed only by constantly monitoring the remaining amount of the FIFO memory 123 and sending a stop signal to the arbiter 116 when the FIFO memory 123 is about to overflow. Become.

Therefore, as a method for managing the number of clocks required to process the packet existing in the FIFO memory 123, the access count number in the request packet is constantly monitored on the input side and the output side of the FIFO memory 123, and When a packet is input, the access count is added and the request packet is FIFO
When it is read from the memory 123 to the memory controller 114, the access count number is subtracted and the FIFO
It is conceivable to determine the total number of access counts in the request packet in the memory 123.

Whether the read request or the write request is the total number of access counts,
It corresponds to the total processing time of all request packets in the O memory 123. Therefore, the latency of the memory bus can be guaranteed by generating a stop signal when this count value exceeds a certain threshold value.

However, in order to realize such a counter that obtains the sum of the access counts, the FI
It is necessary to have monitor circuits on the input side and the output side of the FO memory 123, and to increase or decrease the counter according to the outputs of these circuits. If the input side and the output side of the FIFO memory 123 have the same clock, such a circuit can be realized. However, in this circuit, the frequency is different between the input side and the output side, and therefore such a circuit is realized. Is not easy.

That is, such a counter is set to FIFO.
If it is provided on the input side of the memory 123, it is necessary to transfer the signal indicating that the packet is output from the FIFO memory 123 and the number of access words thereof on the output side to the input side by changing the clock. Here, it cannot be said that which of the clock of the memory bus 110 and the clock of the memory controller 114 is faster. As described above, it is difficult to transfer the clocks whose size relationship between the two clocks is unknown.

Therefore, an object of the present invention is to monitor a FIFO memory provided between a memory bus and a memory controller so as to guarantee a latency within a predetermined time in both reading and writing. A transfer system and method, and an access monitor device.

[0035]

SUMMARY OF THE INVENTION The present invention is directed to a plurality of client devices, resources shared by the plurality of client devices, resource control means for controlling the resources, and data between the plurality of client devices and the resources. A bus for transmitting and receiving, and a buffer means for temporarily accumulating requests transferred from each client device via the bus and reading them to the resource control means, and extracting access count information included in the requests accumulated in the buffer means. , A total of access count number calculating means for obtaining the sum of access count information contained in the requests accumulated in the buffer means, and a sum of access count information contained in the requests accumulated in the buffer means have a predetermined threshold value. If you exceed it, the client device A data transfer system which is adapted and means so as to limit the process.

The present invention comprises a plurality of client devices, resources shared by the plurality of client devices, resource control means for controlling the resources, and a bus for transmitting and receiving data between the plurality of client devices and the resources. The data transfer method of the system, wherein the request transferred from each client device via the bus is temporarily accumulated in the buffer means and read out by the resource control means, and the access count included in the request accumulated in the buffer means is provided. Extract the information,
When the sum of the access count information contained in the requests accumulated in the buffer means is obtained and the sum of the access count information contained in the requests accumulated in the buffer means exceeds a predetermined threshold value, the client device is accessed. Is a data transfer method that is designed to limit the above.

The present invention comprises a plurality of client devices, resources shared by the plurality of client devices, resource control means for controlling the resources, and a bus for transmitting and receiving data between the plurality of client devices and the resources. In the system, an access monitor device for monitoring the sum total of the number of access of resources, the sum counter for counting the sum total of access count information of requests accumulated in the buffer means between the resource control means and the bus, When a request is input from the bus to the buffer means, a means for detecting the access count value from the request and adding the access count value to the value of the total counter so far, and a request word when the request is input from the bus Detect the access count value from Data holding means for holding the value of the access count, and the estimated value of the remaining amount of the buffer estimated from the count value of the amount of data input from the bus and the actual remaining amount of the buffer means are compared. Buffer read determination means for determining that the data has been read, and when it is determined that the request word has been read from the buffer means, it corresponds to the access count value of the request word read from the buffer means. A value is read from the data holding means, means for subtracting the value read from the data holding means from the value of the total sum counter is compared with the total value of the access counts counted by the total sum counter and a predetermined threshold value, When the sum total value of the sum counter access exceeds the specified threshold,
An access monitor device is provided with means for outputting a stop signal.

In the present invention, there is provided an access sum total count monitor circuit for monitoring the sum total of the access count numbers of the requests accumulated in the buffer means between the resource control means and the bus.

That is, the word of the header includes a byte count. The value of this byte count reflects the number of accesses to the memory, which is a resource shared by each client. The total access count monitor circuit determines the total byte count of the header. Then, when the sum of byte counts of this header exceeds a predetermined threshold value,
A stop signal is output from the access sum count monitor circuit. This stop signal is supplied from the access sum count monitor circuit to the arbiter. Arbiter is FI
When a stop signal is sent from the FO memory remaining amount monitor, arbitration of the request is stopped. This limits access to the memory of the client device.

As described above, the access sum total count monitor circuit for monitoring the sum total of the access count numbers of the requests accumulated in the FIFO memory is provided, and when the sum total of the access count becomes equal to or more than a predetermined threshold value, the access sum total count is Since the monitor circuit sends a stop signal to the arbiter to stop the arbitration of the request, the latency of the memory bus can be guaranteed.

Further, according to the present invention, the remaining amount of the FIFO memory estimated from the count value of the input word and F
The actual remaining amount of the IFO memory is compared, and it is detected from this comparison value that the FIFO memory has been read. With such a configuration, it is possible to adopt a configuration that does not depend on the frequency relationship between the word clock sent from the memory bus to the FIFO memory and the word clock used when the memory is accessed from the memory controller.

[0042]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 illustrates the overall configuration of a system to which the present invention is applied.

In FIG. 1, the client device 1
Reference numerals 1, 12, and 13 are devices that access the memory 15, which is a shared resource. For example, in a system that constitutes a signal processing chip, the client devices 11, 12, and 13 are BitBLT (Bit Block Transfe
r) engine, JPEG (Joint Photographic Experts Gr
oup) A processor such as an engine. These client devices 11, 12, 13 have a FIFO memory (Fir memory).
st-In First-Out) 21A, 21B, 21C and FIFO
It is connected to the memory bus 10 via the memories 22A, 22B and 22C, respectively. In addition, the memory bus 10
The memory controller 14 is connected via the FIFO memories 23 and 24. The memory controller 14 is a resource control circuit that controls reading / writing of the memory 15.

The memory 15 is a resource that can be commonly used by a plurality of client devices 11, 12, 13. As the memory 15, for example, SDRAM (Synchro
nous Dynamic Random Access Memory) is used. S
The DRAM is capable of continuous data transfer in synchronization with a clock, and when burst transfer is designated, data transfer of a designated number of data can be continuously performed in units of one clock. Here, the memory 15 having the SDRAM configuration can transfer 64-bit data in one clock. SDRAM is SDR (Dingle Data Rate)
However, DDR (Double Data Rate) may be used.

The memory bus 10 is a bus for transferring data between the client devices 11, 12, 13 and the memory controller 14. Memory bus 10
Is a transmission bus 10A that sends data from the client device 11, 12, 13 side to the memory controller 14 side.
And a receiving bus 1 for receiving data from the memory controller 14 side on the client device 11, 12, 13 side.
It consists of 0B.

Each client device 11, 12, 13
And a memory bus 10 between the FIFO memory 21A,
21B, 21C and FIFO memories 22A, 22B, 2
2C is provided. These FIFO memories 21A, 2
1B, 21C, FIFO memory 22A, 22B, 22C
Is provided as a buffer. Between each client device 11, 12, 13 and the memory bus 10, a FI
Since the FO memories 21A, 21B and 21C and the FIFO memories 22A, 22B and 22C are provided, the client devices 11, 12 and 13 are connected to the memory bus 10 respectively.
It is possible to send requests and receive data asynchronously with the transfer clock.

A FIFO memory 23 and a FIFO memory 24 are provided between the memory controller 14 and the memory bus 10. A FIFO memory 23 and a FIFO are provided between the memory controller 14 and the memory bus 10.
Since the O memory 24 is provided, the memory controller 14 can receive requests and send data asynchronously with the transfer clock of the memory bus 10.

Each client device 11, 12, 13
Is assigned a unique device ID. When accessing the memory 15, each of the client devices 11, 12, 13 has a transmission bus 10A of the memory bus 10.
Send the request via. This request is
It has a packet structure.

Client device 11, 12, 13
Can access the common memory 15. Therefore, a plurality of client devices 11,
At 12, 13, it is possible that requests to memory 15 will occur simultaneously. Therefore, an arbiter 16 is provided to prevent contention of requests from the client devices 11, 12, and 13.

When the client devices 11, 12, 13 access the memory 15, first, the arbiter 1
A request is sent to 6 for the right to use the bus.
When there are requests from a plurality of client devices, the arbiter 16 arbitrates the requests,
The grant is returned to only one client device that permits the use of the memory bus 10. Of the plurality of client devices 11, 12 and 13, only the client device for which the grant has been returned can access the memory 15.

In the case of a memory write request,
Write requests are transmitted from the client devices 11, 12, and 13. This write request is sent to the memory controller 14 via the transmission bus 10A. The memory controller 14 causes the client devices 11, 12, 13 to respond to the write request.
The write data sent from is written in a desired address of the memory 15.

In the case of a memory read request,
Read requests are transmitted from the client devices 11, 12, and 13. This read request is sent to the memory controller 14 via the transmission bus 10A. The memory controller 14 reads data from a desired address of the memory 15 in response to a read request. This read data is the memory controller 1
4, the client device 11, 12, which has been transferred via the reception bus 10B and transmitted the read request,
It is received at 13.

FIG. 2 shows the structure of a packet transferred to the memory bus 10. As shown in FIG. 2, the data transferred to the memory bus 10 has a packet structure including a header word, a data word, and an end of packet word. These header, data, and end-of-packet word are 72 bits in which 64-bit data and a control signal such as a flag are added.

2A, 2B, and 2C show the bit assignments of the header, data, and words of the end of packet, respectively.

As shown in FIGS. 2A to 2C, a 2-bit flag is provided at the beginning of each word. The flag is
The word identifies the header, data, or end of packet. This flag is, for example, "0
"1" is a header, "10" is data,
If it is “11”, it is an end of packet.

In the header word of FIG. 2A, the 6 bits following the 2 bits of the flag are definable on the client side.

The next 6 bits are the device ID. A unique device number is assigned to each client device, and this device ID indicates the ID of the target client device.

The next 6 bits are the mode. The mode indicates the address mode together with the addressing format. As the address mode, a linear mode, a 2D mode, a circular mode, etc. are prepared.

The next 1 bit of the mode indicates read or write. If this bit is, for example, "1", it is a write, and if it is "0", it is a read.

The next 2 bits of the addressing format are reserved for future expansion.

The next 30 bits are the start address. The start address is the start address of the memory to read or write, and this address is set in byte units.

As shown in FIGS. 2B and 2C, in the data word and the end of packet word, the 2-bit flag is followed by the 8-bit byte enable.
Next, 64-bit data is arranged. The byte enable indicates whether the corresponding data is valid or invalid.

That is, the transfer data of one word may be less than 64 bits. Transfer data of 1 word is 6
If it is less than 4 bits, 1 word of data is 64
As shown in FIG. 3, a stuffing byte is inserted so that it becomes a bit.

FIG. 3A shows a case where the lower 3 bytes of 64 bits (8 bytes) are data and the upper 5 bytes are stuffing bytes. In this case, FIG.
As shown in, the lower 3 bits of the 8 bytes of the byte enable are "1" indicating that they are valid, and the upper 5 bits thereof are "0" indicating that they are invalid data.

FIG. 3B shows a case where the upper 2 bytes of 64 bits (8 bytes) are data and the lower 6 bytes are stuffing bytes. In this case, FIG.
As shown in (4), among the 8 bits of the byte enable, the upper 2 bits are “1” indicating that they are valid and the lower 6 bits are “0” indicating that they are invalid data.

As shown in FIG. 4A, the header word (FIG.
In A), a mode and an addressing format are provided, and the mode and the addressing format indicate the address mode. As the address mode, a linear mode, a 2D mode, a circular mode, etc. are prepared.

4B to 4D show each address mode. In the linear mode, as shown in FIG. 4B, the 4 bits of the mode are “0000”. In the linear mode, jump (Jump) and byte count (Byte Count) are specified as parameters. The linear mode is the most standard addressing mode, in which the data of the number of accesses specified by the byte count is accessed sequentially from the position specified by the start address.

The jump (Jump) specifies a word (64 bits) to be jumped by a numerical value of 2's complement. Jumps are made at word boundaries. For example, if jump (Jump = 2 words) is set, the address is advanced by jumping two words at the word boundary. Reverse addressing is also possible by specifying a negative value.

Byte Count sets the required number of bytes. In addition, the byte count (Byte Count-1) is actually used, and is the number obtained by subtracting 1 from the required number of bytes. In other words, when 1 byte of data is needed, the byte count (Byte Cou
nt) is set to 0. Here, in order to simplify the explanation, it is assumed that the byte count (Byte Count) sets the required number of access sebytes.

In the 2D mode, as shown in FIG. 4C, the 4 bits of the mode are "0001". In 2D mode, as parameters, Jump (Jump) and Height (Hig
ht), column (Col), and row (Row) can be specified. Two
The D mode enables two-dimensional block-based access, and addresses can be specified by rows and columns.

In the circular mode, as shown in FIG. 4D, 4 bits of the mode are "0010". In circular mode, the byte count (By
te Count) is specified. The circular mode cyclically accesses the data of the access number designated by the byte count. That is, in the circular mode, cyclic addressing is performed so that the end address returns to the start address within the range where the byte count is specified.

FIG. 5 shows access in the linear mode when the start address is "05h (h is a hexadecimal number)", the jump is "2 words", and the byte count is "31". This shows an access such that 31 bytes are accessed from the address "5h" on the memory and two words are jumped at the boundary between words.

As shown in FIG. 5, first, 3-byte data "05h" to "07h" is sequentially accessed. From "07h", which is the boundary between words, 2
Word jump, 1 word from “10h” to “17h” is accessed, 2 words are jumped at a word boundary, 1 word from “20h” to “27h” is accessed, 2 words are jumped at a word boundary, "30
One word from "h" to "37h" is accessed, two words are jumped at the word boundary, and "40h" to "43" are accessed.
The 4-byte data of "h" is accessed. As a result, 31 bytes of data are accessed in order from the address "5h".

When the data thus accessed is read, as shown in FIG. 6, the word H1 of the header,
The packet is composed of the words D1 to D4 of the data and the word D5 of the end of packet.

As shown in FIG. 7A, word H1 in the header
Is a flag "01" indicating that it is a word in the header.
Is added. Various information as shown in FIG. 2A is described in the header.

As shown in FIGS. 7B-7E, word D
A flag "10" indicating that it is a word of data is added to 1 to D4. In the word D1, 3-byte data of addresses "05h" to "07h" are arranged. Since the 3-byte data is less than 64 bits, a stuffing byte is inserted here.
64-bit data of addresses "10h" to "17h" are arranged in the word D2. 64-bit data of addresses "20h" to "27h" are arranged in the word D3. 64-bit data of addresses "30h" to "37h" are arranged in the word D4. A flag “11” indicating that it is an end-of-packet word is added to the word D5. In the word D5, 4-byte data of addresses "40h" to "47h" is arranged. Since 4-byte data is less than 64 bits, stuffing bytes are inserted here.

As described above, in the system shown in FIG. 1, the data transferred to the memory bus 10 has a packet structure. Client device 11, 12, 1
As shown in FIG. 8, the types of packets sent from the memory controller 3 to the memory controller 14 are write request packets (FIG. 8A) and read request packets (FIG. 8B)
It is divided into two.

As shown in FIG. 8A, the write request packet consists of a header word and several words of write data, and the end of packet word comes at the end.

As shown in FIG. 8B, the read request packet is one word of the read header, and there is no data word or end of packet word.

Whether the request is a read request or a write request is R / of the word of the header added to the beginning of the packet.
It can be identified by the W bit (see FIG. 2A).

The packet sent from the memory controller 14 to the client device 11, 12, 13 is a read data packet read from the memory 15 in response to the read request from the client device 11, 12, 13. Is. As shown in FIG. 9, this read data packet is composed of a header word and several words of write data, and the end of packet word comes at the end.

As shown in FIG. 10, a unique device ID is assigned to each client device 11, 12, 13. For example, as shown in FIG. 10, the client device 11 has a device ID (ID = 0).
1h) is assigned, the client device 12 is assigned a device ID (ID = 02h), and the client device 13 is assigned a device ID (ID = 03h) (Byte Count = 16).

FIG. 11A shows words transferred to the transmission bus 10A, and FIG. 11B shows words transferred to the reception bus 10B. As shown in FIG. 11A, for example, if the client device 11 makes a request to read 16-byte data from the memory 15, the client device 11 sends a read request packet P1 via the transmission bus 10A. The packet P1 of this read request has only a header, and this header has a device ID (ID = 01h) and a byte count (Byte Cou
nt = 16) is described.

Next, if the client device 12 makes a request to read 8-byte data from the memory 15, the client device 12 sends a read request packet P2 via the transmission bus 10A. The packet of this read request has only the header, and the device ID (ID = 02h) and the byte count (Byte Count = 8) are described in this header.

Next, if the client device 13 makes a request to write 24 bytes of data to the memory 15, the client device 13 sends a write request packet P3 via the transmission bus 10A. This write request packet P3 is composed of a word of the header, a word of data of 2 bytes following this, and a word of the end of packet of 1 word. In this header, the device ID (ID = 03h) and the byte count (Byte Count = 24) are described.

As described above, the transmission bus 1 of the memory bus 10
0A includes packets P1 and P for requesting read or write from the client devices 11, 12 and 13.
2, P3, P3 ... Are sent one after another. Each word of the read or write request is once read into the FIFO memory 23 from the transmission bus 10A.

The words read into the FIFO memory 23 are sequentially sent to the memory controller 14. In the memory controller 14, in response to each request, the memory 1
5 is accessed.

That is, in FIG. 11, in response to the read request packet P1 from the client device 11, the data of the desired address is 1 from the memory 15.
6 bytes are read. This read data is packetized into a packet P11 consisting of a header, a data word of 1 word following the header, and an end of packet of 1 word. This read data packet P11 is sent from the memory controller 14 via the reception bus 10B, as shown in FIG. 11B. In the header of this read data packet, the device ID (ID = 01
h) is described. Since the device ID of the client device 11 is (ID = 01h), it is known that the read data is addressed to itself, and the client device 11 receives this read data packet P11.

In response to the read request packet P2 from the client device 12, eight bytes of data at a desired address are read from the memory 15. This read data is packetized into a packet P12 consisting of a header and the end of packet of one word following the header. This read data packet P12 is shown in FIG. 11B.
As shown in (4), it is sent from the memory controller 14 via the reception bus 10B. In the header of this read data packet, the device ID (ID = 02h) is set.
Is described. Since the device ID of the client device 12 is (ID = 02h), it is known that the read data is addressed to itself, and the client device 12 receives this read data packet P12.

In response to the read request packet P3 from the client device 13, the 24-byte data transferred from the client device 13 as write data is written in a desired address of the memory 15.

As described above, in the system shown in FIG. 1, a read or write request is sent in a packet structure from the client devices 11, 12, 13 via the transmission bus 10A of the memory bus 10. The word of this request is written in the FIFO memory 23.

The words stored in the FIFO memory 23 are read by the memory controller 14. Then, the memory 15 is accessed by the memory controller 14.

If the request sent to the memory controller 14 is a write, according to the addressing mode,
Data corresponding to the data designated by the byte count is written in the memory 15 from the address designated by the start address.

If the request sent to the memory controller 14 is a read, according to the addressing mode,
Data corresponding to the data specified by the byte count is read from the memory 15 from the address specified by the start address.

The data read from the memory 15 is sent to the memory controller 14. Then, this data is packetized by the memory controller 14 into a packet including a word of the header, write data of several words, and an end of packet, and is stored in the FIFO memory 24. The output of the FIFO memory 24 is the memory bus 1
0 through the bus 10B, the client device 11,
It is sent to 12, 13.

The word clock transferred to the memory bus 10 and the word clock accessed by the memory controller 14 to the memory 15 are asynchronous with each other. FIFO memory 23 and FIFO memory 24
Is a buffer that absorbs the difference in frequency between the word clock transferred to the memory bus 10 and the word clock accessed by the memory controller 14 to the memory 15.

However, if the frequency of the clock of the word transferred to the memory bus 10 is higher than the frequency of the clock of the word accessed by the memory controller 14 to the memory 15, the client devices 11, 12, 13 are assumed. The word sent from the memory bus 10 via the transmission bus 10A is the FIFO memory 2
3, and the FIFO memory 23 overflows.

Therefore, the remaining amount of the FIFO memory 23 is constantly monitored, and when the FIFO memory 23 is about to overflow, a stop signal is sent to the arbiter 16 to stop bus arbitration, and the client device 1
It is necessary to prevent requests from 1, 12, and 13 from being sent.

Therefore, a FIFO memory remaining amount monitor 25 is provided. With the FIFO memory remaining amount monitor 25, F
The remaining amount of the IFO memory 23 is compared with a predetermined threshold value. When the FIFO memory remaining amount monitor 25 detects that the remaining amount of the FIFO memory 23 becomes less than or equal to a predetermined threshold value, the FIFO memory remaining amount monitor 25 outputs a stop signal. This stop signal is sent to the arbiter 16. The arbiter 16 is a FIFO memory remaining amount monitor 2
When a stop signal is sent from 5, the request arbitration is stopped. Thereby, the client device 1
The access request to the memory 15 of 1, 12, 13 is stopped.

However, as described above, the remaining amount of the FIFO memory 23 is constantly monitored, and when the FIFO memory 23 is about to overflow, the latency of the memory bus is reduced only by sending a stop signal to the arbiter 16. I cannot guarantee.

That is, the client devices 11, 1
When 2 and 13 send a read request to the memory bus 10, the read data corresponding to this read request is read from the memory 15, and the client device 1
It will be returned to 1, 12, and 13. In FIG. 11, when the client device 11 transmits the read request packet P1, the read data packet P1 corresponding to the read request packet P1 is slightly delayed.
1 is returned. Further, when the client device 12 transmits the read request packet P2, a read data packet P12 corresponding to the read request packet P2 is returned after a slight delay.
It is necessary to guarantee that the processing at this time is completed within a predetermined latency.

In the case of a write request, the write header word is followed by the write data word (see FIG. 8A), and the write time is the write data word following the write header word. Correspond.

However, in the case of a write request, only the header word is sent (see FIG. 8B), and this header word is written in the FIFO memory 23.
Whether reading large data or small data, the request sent is only the word in the header. Therefore, in the case of a read request, there is no relation between the storage amount of the FIFO memory 123 and the processing time. . Therefore, the latency of the bus cannot always be guaranteed only by the remaining amount of the FIFO memory 123.

Therefore, in the embodiment of the present invention, FI
An access count sum count monitor circuit 26 for monitoring the sum of the access count counts of the requests stored in the FO memory 23 is provided.

That is, as shown in FIG. 4, the word of the header includes a byte count (ByteCount). The value of this byte count reflects the number of accesses to the memory 15.

Access count total count monitor circuit 26
Then, the sum of the byte counts of the headers stored in the FIFO memory 23 is obtained. Then, when the sum of byte counts of this header exceeds a predetermined threshold value,
A stop signal is output from the total access count monitor circuit 26.

This stop signal is supplied from the total access count monitor circuit 26 to the arbiter 16. When the stop signal is sent from the FIFO memory remaining amount monitor 25, the arbiter 16 stops the arbitration of the request. As a result, the client devices 11, 12, 1
Access to the memory 15 of No. 3 is restricted.

As described above, in the embodiment of the present invention,
An access count sum count monitor circuit 26 for monitoring the sum of access count counts of requests accumulated in the FIFO memory 23 is provided. When the access count sum exceeds a predetermined threshold value, the access count sum count monitor circuit 26 is provided. Since the stop signal is sent from the arbiter 16 to the arbiter 16 and the arbitration of the request is stopped, the latency of the memory bus 10 can be guaranteed.

Although the sum of the number of accesses is the sum of the byte counts of the header here, it is not limited to the sum of the byte counts. In a system in which the number of accesses is designated by word count, the sum of word counts is obtained.

FIG. 12 shows the configuration of the total access count monitor circuit 26. In FIG. 12, the word of the request sent via the transmission bus 10A is written in the FIFO memory 23, and at the same time, the byte count detection unit 51, the flag detection unit 52, and the FIFO memory remaining amount of the access count total count monitor circuit 26. It is supplied to the counter 53.

The byte count detector 51 detects the byte count value of this header (see FIG. 4) when the word of the request is a header. This byte count value is the byte count sum counter 5
4 and packet data holding register 5
5 is supplied.

The packet data holding register 55 has a shift register configuration. When the byte count detection unit 51 detects the byte count values C0, C1, ... Of the header in the request word, the detected byte count values C0, C1, ... Of each header are stored in the packet data holding register 55. It is accumulated in order.

The byte count sum counter 54 calculates the sum of the byte count values of the header of the request word. This byte count sum counter 5
In step 4, when the byte count detection unit 51 detects the byte count value of the header of the request word, the detected byte count value of the header is added to the values up to that point.

Further, as will be described later, when the word of the header is read from the FIFO memory 23, the packet data holding register 55 configured as a shift register.
Is shifted to the right, and the value C0, which has been stored first among the byte count values of each header, is read from the packet data holding register 55. When the byte count value is read from the packet data holding register 55, the byte count sum counter 54 value is subtracted by the byte count value C0 read from the packet data holding register 55.

The flag detecting section 52 uses the leading two bits of each word.
The bit flag (see FIG. 2) is detected to determine whether the input word is a header, data or end of packet. The output of the flag detector 52 is supplied to the FIFO memory image register 56.

The FIFO memory image register 56 is
The shift register has the number of stages corresponding to the capacity of the FIFO memory 23. In the FIFO memory image register 56, "1" is written when the input word is a header, and "0" is written when the input word is data or end of packet.

The FIFO memory remaining capacity counter 53 estimates the remaining capacity of the FIFO memory 23 from the number of input words.

That is, the FIFO memory remaining amount counter 5
Reference numeral 3 counts the number of words input via the transmission bus 10A, and estimates the remaining amount of the FIFO memory 23 by subtracting the counted number of words from the total capacity of the FIFO memory 23. . In addition, from the output of the FIFO memory read determination unit 58, 1 of the FIFO memory 23
When the word read is determined, the estimated value of the remaining capacity of the FIFO memory is increased by one word.

The output of the FIFO memory remaining amount counter 53 is supplied to the FIFO memory remaining amount comparing unit 57. Also, F
The IFO memory remaining amount comparison unit 57 includes the FIFO memory 23.
From, the actual remaining amount of the FIFO memory 23 is supplied.

In the FIFO memory remaining amount comparison unit 57, the FIFO
The estimated value of the remaining amount of the FIFO memory 23 detected by the O memory remaining amount counter 53 is compared with the actual remaining amount of the FIFO memory 23 output from the FIFO memory 23.
The output of the FIFO memory remaining amount comparison unit 57 is supplied to the FIFO memory read determination unit 58. The FIFO memory read determination unit 58 determines from the output of the FIFO memory remaining amount comparison unit 57 whether the FIFO memory 23 has been read.

That is, the client devices 11, 1 are stored in the FIFO memory 23 via the transmission bus 10A.
The words of the request sent from 2 and 13 are accumulated. The FIFO memory remaining amount counter 53 counts the number of words of the request input via the transmission bus 10A and subtracts it from the total capacity of the FIFO memory 23. Therefore, if the reading of the FIFO memory 23 has not occurred, the estimated value of the remaining amount of the FIFO memory 23 detected by the FIFO memory remaining amount counter 53 and the FI
It should match the actual remaining amount of the FIFO memory 23 output from the FO memory 23.

On the other hand, when the reading of the FIFO memory 23 occurs and the output of the FIFO memory 23 is sent to the memory controller 14, the actual remaining amount of the FIFO memory 23 is large as much as the data is read. But F
The estimated value of the remaining amount of the FIFO memory 23 detected by the IFO memory remaining amount counter 53 remains unchanged.

From this, the estimated value of the remaining amount of the FIFO memory 23 detected by the FIFO memory remaining amount counter 53 and the actual remaining amount of the FIFO memory 23 output from the FIFO memory 23 are compared, and the FIFO memory The actual remaining amount of the FIFO memory 23 output from the
If it is larger than the estimated value of the remaining amount of the FIFO memory 23 detected by the IFO memory remaining amount counter 53, the FIFO
It can be determined that the reading of the O memory 23 has occurred. FI
The FO memory read determination unit 58 uses the estimated value of the remaining amount of the FIFO memory 23 detected by the FIFO memory remaining amount counter 53 and the FIFO output from the FIFO memory 23.
From the comparison result with the actual remaining amount of the memory 23, it is determined that the reading of the FIFO memory 23 has occurred.

The output of the FIFO memory read determination unit 58 is supplied to the FIFO memory remaining amount counter 53 and the FIFO memory image register 56.

If it is determined from the output of the FIFO memory read determination unit 58 that one word has been read from the FIFO memory 23, the FIFO memory remaining amount counter 5
The count value of 3 is decreased by 1 word, the estimated value of the remaining amount of the FIFO memory 23 is increased by 1 word, the estimated value of the FIFO memory 23 obtained by the FIFO memory remaining amount counter 53, and the FIFO output from the FIFO memory 23. The actual remaining amount in the memory 23 is matched.

Further, the FIFO memory read determination unit 58
If it is determined from the output of 1 that one word has been read from the FIFO memory 23, the FIFO memory image register 56 configured as a shift register is shifted to the right by 1 bit. Then, the earliest stored value is read from the FIFO memory image register 56. The output of the FIFO memory image register 56 is supplied to the header / data determination unit 59.

As described above, "1" is written in the FIFO memory image register 56 when the input word is the header, and "0" is written when it is the data or the end of packet. When it is detected from the output of the FIFO memory read determination unit 58 that one word has been read from the FIFO memory 23,
The earliest stored value is read from the FIFO memory image register 56. This value indicates whether the word read from the FIFO memory 23 is a header, data, or end of packet.

The header / data determination unit 59 outputs the output from the FIFO memory image register 56 to "0" or "1".
Depending on whether or not the word read from the FIFO memory 23 is a header, data or end of packet. The output of the header / data determination unit 59 is supplied to the packet data holding register 55.

When the output of the FIFO memory image register 56 is "1" and it is determined that the word read from the FIFO memory 23 is the header, the packet data holding register 55 is shifted to the right by 1 bit, From the packet data holding register 55, the value C0 stored first among the byte count values of each header is read. This value C0 indicates the value of the byte count of the header when the word read from the FIFO memory 23 is the header. When the byte count value C0 is read from the packet data holding register 55, the byte count value C0 read from the packet data holding register 55 is subtracted from the previous values of the byte count sum counter 54.

Thus, when the word of the header is input via the transmission bus 10A of the memory bus 10, the value of the byte count sum counter 54 is added by the value of the byte count of the header, and the value is read from the FIFO memory 23. When the word of the header is read by the memory controller 14, the value of the byte count of the read header is subtracted. Therefore, the value of the byte count sum counter 54 becomes equal to the sum of the byte count values in the header of the data stored in the FIFO memory 23.

The output of the byte count sum counter 54 is supplied to the stop signal generator 60. A predetermined threshold value is given to the stop signal generator 60. The stop signal generator 60 compares the output of the byte count sum counter 54 with a predetermined threshold value, and when the output of the byte count sum counter 54 exceeds the predetermined threshold, the stop signal generator 60 outputs a stop signal. Is output.

As described above, in the embodiment of the present invention, the total access count counter monitor circuit 26 for monitoring the total access count (byte count) of the requests stored in the FIFO memory 23 is provided. Then, when the total number of accesses included in the words of the header stored in the FIFO memory 23 becomes equal to or more than the threshold value, a stop signal is sent to the arbiter 16 and the memory from the client devices 11, 12, 13 is sent. Access to 15 is restricted. As a result, it is possible to guarantee the latency from when the device sends the request to when the processing is performed, regardless of whether it is a read or a write.

Further, in the embodiment of the present invention, the comparison unit 57 compares the remaining amount of the FIFO memory 23 estimated from the count value of the input word with the actual remaining amount of the FIFO memory 23. From the comparison value to the FIFO memory 23
It has detected that there was a read. In such a configuration, the word clock (input clock of the FIFO memory 23) sent from the memory bus 10 to the FIFO memory 23 and the memory controller 14 to the memory 15 are used.
Can be configured to be independent of the frequency relationship with the word clock (the output clock of the FIFO memory 23) when accessing.

That is, as a method of managing the number of clocks required to process the packets existing in the FIFO memory 23, the number of accesses included in the word of the header is constantly monitored on the input side and the output side of the FIFO memory 12. Then, when the header is input, the access count is added, and when the header is output, the access count is subtracted so as to obtain the total access count.
For that purpose, it is necessary to have a monitor circuit on each of the input side and the output side of the FIFO memory 23 and increase or decrease the counter according to the output of these circuits. FI
If the input side and the output side of the FO memory 23 have the same clock, such a circuit can be realized.

However, if the input side and the output side of the FIFO memory 23 have different frequencies, if the input side has a counter for calculating the total number of accesses, the word is output from the FIFO memory 23 at the output side. It is necessary to change the clock signal and the value of the number of accesses thereof to the input side. Here, the frequency relationship between the input clock of the FIFO memory 23 and the output clock of the FIFO memory 23 cannot be said to be higher. As described above, it is difficult to replace clocks whose size relationship between the two clocks is unknown.

In the present embodiment, since such clock replacement is unnecessary, it is possible to adopt a configuration that does not depend on the frequency relationship between the input clock of the FIFO memory 23 and the output clock of the FIFO memory 23.

In the above example, the case of configuring the image processing chip system has been described, but the present invention can be similarly applied to a system in which a plurality of clients share one resource. Is.

Further, in the above-described embodiment, the access number total count monitor circuit 26 for monitoring the total access count number of the requests accumulated in the FIFO memory 23 and the F number for monitoring the remaining amount of the FIFO memory 23.
Although the IFO memory remaining amount monitor 25 is provided, in the access count total count monitor circuit 26, the FI
Since the remaining amount of the FO memory 23 is monitored,
It is not necessary to specifically provide the O memory remaining amount monitor 25. The access count sum count monitor circuit 26 may be configured to output a stop signal in accordance with the sum of the access count counts of the requests accumulated in the FIFO memory 23 and the remaining capacity of the FIFO memory 23. .

[0139]

According to the present invention, the sum of the byte counts of the header is obtained by the access sum total count monitor circuit. Then, when the sum of the byte counts of this header exceeds a predetermined threshold value, a stop signal is output from the access sum total count monitor circuit. This stop signal is supplied from the access sum count monitor circuit to the arbiter. The arbiter stops the arbitration of the request when the stop signal is sent from the FIFO memory remaining amount monitor. This limits access to the memory of the client device.

As described above, the access sum total count monitor circuit for monitoring the sum total of the access count numbers of the requests stored in the FIFO memory is provided, and when the sum total of the access counts becomes equal to or more than a predetermined threshold value, the access sum total count is counted. Since the monitor circuit sends a stop signal to the arbiter to stop the arbitration of the request, the latency of the memory bus can be guaranteed.

Further, according to the present invention, the remaining amount of the FIFO memory estimated from the count value of the input word and the F
The actual remaining amount of the IFO memory is compared, and it is detected from this comparison value that the FIFO memory has been read. With such a configuration, it is possible to adopt a configuration that does not depend on the frequency relationship between the word clock sent from the memory bus to the FIFO memory and the word clock used when the memory is accessed from the memory controller.

[Brief description of drawings]

FIG. 1 is a block diagram of an example of a system including a plurality of client devices and resources to which the present invention is applied.

FIG. 2 is a schematic diagram used for explaining each word of a packet transferred to a bus.

FIG. 3 is a schematic diagram used to describe packet data transferred to a bus.

FIG. 4 is a schematic diagram used to describe a header of a packet transferred to a bus.

FIG. 5 is a schematic diagram used to describe an example of an addressing mode.

FIG. 6 is a timing diagram used to describe an example of an addressing mode.

FIG. 7 is a schematic diagram used to describe an example of an addressing mode.

FIG. 8 is a schematic diagram used to describe a packet sent to a transmission bus.

FIG. 9 is a schematic diagram used to describe a packet sent to a reception bus.

FIG. 10 is a block diagram used for explaining an example of a system including a plurality of client devices and resources to which the present invention is applied.

FIG. 11 is a timing diagram used for explaining an example of a system including a plurality of client devices and resources to which the present invention is applied.

FIG. 12 is a block diagram of an example of an access count sum count monitor circuit.

FIG. 13 is a block diagram of an example of a conventional system including a plurality of client devices and resources.

FIG. 14 is a block diagram of another example of a conventional system including a plurality of client devices and resources.

[Explanation of symbols]

10 ... Memory bus, 10A ... Transmission bus, 10B
... Reception bus, 11, 12, 13 ... Client device, 14 ... Memory controller, 15 ...
・ Memory, 16 ... Arbiter, 21A-21C, 22
A to 22C, 23, 24 ... FIFO memory, 25 ...
..FIFO memory remaining amount monitor, 26 ... Total number of access count monitor circuit, 51 ... Byte count detecting unit, 52 ... Flag detecting unit, 53 ... FIFO memory remaining amount counter, 54 ... Byte count sum counter, 55 ... Packet data holding register, 56.
..FIFO memory image register, 57 ... Remaining amount comparing section, 60 ... Stop signal generating section

Claims (10)

[Claims] 1. A plurality of client devices, resources shared by the plurality of client devices, resource control means for controlling the resources, and a bus for transmitting and receiving data between the plurality of client devices and the resources. And buffer means for temporarily storing the request transferred from each of the client devices via the bus and reading it to the resource control means, and extracting access count information included in the request stored in the buffer means Then, the sum of the access count number total calculation means for obtaining the sum of the access count information contained in the request stored in the buffer means and the sum of the access count information contained in the request stored in the buffer means is predetermined. Exceeded the threshold of And a means for restricting access to the client device. 2. The access count number total sum calculating means counts the total sum of access count information of requests accumulated in the buffer means, and the request when the request is input from the bus to the buffer means. Means for detecting the access count value from the access count value and adding the access count value to the sum counter value up to that time, and when a request is input from the bus, the access count value is detected from the word of the request. Comparing the estimated value of the remaining amount of the buffer estimated from the count value of the amount of data input from the bus with the actual remaining amount of the buffer unit. To determine that the data has been read from the buffer means. A read determination means, and when it is determined that the request word has been read from the buffer means, a value corresponding to the access count value of the request word read from the buffer means is read from the data holding means, The data transfer system according to claim 1, comprising means for subtracting the value read from the data holding means from the value of the sum counter. 3. The data transfer system according to claim 1, wherein data is transferred between the plurality of client devices and the resource in a packet structure. 4. The data transfer system according to claim 1, wherein the access count information is a byte count added to the request. 5. The data transfer system according to claim 1, wherein the access count information is a word count added to the request. 6. A plurality of client devices, resources shared by the plurality of client devices, resource control means for controlling the resources, and a bus for transmitting and receiving data between the plurality of client devices and the resources. And a request transferred from each client device via the bus is temporarily stored in a buffer means, read out by the resource control means, and stored in the buffer means. The access count information contained in the request is extracted, the sum of the access count information contained in the request stored in the buffer means is obtained, and the access count information contained in the request stored in the buffer means is calculated. Sum exceeds a certain threshold Then, the data transfer method that is designed to restrict the access of the client device. 7. The data transfer method according to claim 6, wherein data is transferred in a packet structure between the plurality of client devices and the resource. 8. The data transfer method according to claim 6, wherein the access count information is a byte count added to the request. 9. The data transfer method according to claim 6, wherein the access count information is a word count added to the request. 10. A plurality of client devices and resources shared by the plurality of client devices,
A resource control means for controlling the resource, a system consisting of a bus for transmitting and receiving data between the plurality of client devices and the resource, an access monitor device for monitoring the total number of access of the resource, A sum counter for counting the sum of access count information of requests accumulated in the buffer means between the resource control means and the bus, and an access count from the request when the request is input from the bus to the buffer means Means for detecting the value of the access count and adding the value of the access count to the value of the sum counter up to that time, and when a request is input from the bus, the access count value is detected from the word of the request and the access Data holding means for holding the count value It is determined that data is read from the buffer means by comparing the estimated value of the remaining capacity of the buffer estimated from the count value of the amount of data input from the bus with the actual remaining capacity of the buffer means. And a data reading means for determining the access count value of the request word read from the buffer means when it is determined that the request word is read from the buffer means. Means for subtracting the value read from the data holding means from the value of the sum total counter and the sum value of the access counts counted by the sum counter and a predetermined threshold value for comparison, And means for outputting a stop signal when the total value of counter access exceeds a predetermined threshold value. Access monitor device.