JP2003332430A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To restrain such a problem concerning skew in a clock signal which is widely used inside a semiconductor integrated circuit that has a tendency that coping with the problem becomes difficult in accordance with micronization in manufacturing technique of a semiconductor integrated circuit. <P>SOLUTION: In a clock signal distribution circuit constituted of a plurality of buffering stages, a wiring layer which is formed on an upper layer side out of a plurality of wiring layers and whose film thickness is large is used as at least a part of a clock signal line of a signal source side, so that increase of wiring resistance can be restrained. At least one out of a power source line and a ground line is made to run in parallel to the clock signal line, so that adverse effect on other wirings can be restrained. A wiring layer which is formed on a lower layer side out of the plurality of wiring layers and whose film thickness is small is used as at least a part of a clock signal line on an end side of the clock signal distribution circuit, so that deterioration of the level of integration can be restrained. <P>COPYRIGHT: (C)2004,JPO

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a common clock signal comprising a plurality of wiring layers having different thicknesses, and a thicker one formed on an upper layer side. The present invention relates to a semiconductor integrated circuit in which a synchronous circuit operated by a wide range exists, and in particular, a clock signal widely used inside a semiconductor integrated circuit, which tends to be difficult to cope with as the manufacturing technology of the semiconductor integrated circuit becomes finer. The present invention relates to a semiconductor integrated circuit that can suppress the problem of skew. 2. Description of the Related Art Some semiconductor integrated circuits have a wide range of synchronous circuits which operate by a common clock signal. Especially recent LSI (Large Scale Integrated)
circuit), the load of the clock signal is large and large. Such a clock signal must be distributed over a long distance to every corner of the chip in a short time while minimizing timing variations. Here, the variation in timing is generally called skew. FIG. 6 is a circuit diagram of a basic clock signal distribution circuit using a large number of buffers in a tree shape. In this and other figures, a buffer B11
To B15 are also referred to as buffers B. The number of buffer stages from the clock signal distribution source is hereinafter referred to as a buffering stage. For example, each of the buffers B11 to B15 is sequentially assigned to the first buffer.
The stage becomes the buffering stage from the fifth stage to the fifth stage. [0005] The clock signal distribution circuit of FIG. 6 is a technique also called a clock tree. In this method, a load is branched in a tree shape and the load at the end is shared by a plurality of buffers B.
Driving a distributed load in a semiconductor integrated circuit. For example, in FIG. 6, a clock signal is distributed to a synchronous circuit existing in a semiconductor integrated circuit like a flip-flop FF. The clock signal distribution circuit has another method called a clock mesh. In this method, a mesh wiring of a clock signal is provided on a chip, and such a wiring is collectively driven by a huge buffer. Next, in a technique called "H" tree, wiring of clock signals branching at equal lengths is provided on a chip. or,
In some cases, a buffer is appropriately provided at the branch point. In any of the above methods, in order to reduce the skew and the delay time until the clock signal arrives, the driving capability of the transistor for distributing and outputting the clock signal is increased, or the on-chip It is necessary to arrange buffers as appropriate everywhere. In the clock signal distribution, values of process parameters such as wiring capacitance and resistance of a clock signal, which depend on a manufacturing technique to be used, have a great influence. In recent years, the wiring pitch has been reduced along with the miniaturization of semiconductor integrated circuit manufacturing technology. Due to the wiring pitch, the film thickness of the wiring layer is simultaneously reduced and scaled. Further, when the thickness is reduced, the wiring cross-sectional area is reduced, so that the wiring resistance generally increases. When driving a small load capacitance, the on-resistance of the driving transistor is relatively large, so that the wiring resistance does not matter. However, when driving a relatively large load capacitance such as a clock signal, the drive transistor is large and therefore has a low on-resistance. Therefore, an increase in wiring resistance leads to an increase in signal delay time, which poses a problem. In order to suppress the wiring resistance, a thick wiring layer is used only for the clock signal wiring. However, a thick wiring layer has looser design rules and cannot be designed in a fine layout. Therefore, if a thick wiring layer is used up to the clock signal distribution terminal of the clock signal distribution circuit, the layout area is wasted. Out. In addition, transistor switching speeds up due to miniaturization, and signal waveforms are becoming steep. If a thick wiring layer is used up to the clock signal distribution end of the clock signal distribution circuit, a clock signal that is strongly driven with a steep waveform is distributed to the end. Then, it becomes easy to cause interference due to crosstalk via the coupling capacitance in the same layer to parallel wirings driven by relatively weak driving ability in the vicinity. Further, when the signal waveform is made steeper to reduce the resistance by increasing the wiring cross-sectional area by increasing the film thickness or the wiring width, the effect of the wiring inductance becomes remarkable. As a result, there is a problem that the clock signal is reflected and the waveform is distorted. Normally, since a thick wiring layer is formed in an upper layer, the distance from the semiconductor substrate supplying the return current of the inductance is long, and therefore, there is a problem that the influence of the inductance is more likely to occur. In addition, the influence of the inductance greatly differs at the ends, resulting in a large skew. The present invention has been made to solve the above-mentioned conventional problems, and is widely used in a semiconductor integrated circuit, which tends to be difficult to cope with as the manufacturing technology of the semiconductor integrated circuit becomes finer. An object of the present invention is to provide a semiconductor integrated circuit that can suppress a problem of skew regarding a clock signal. First, the invention of the present application operates by a common clock signal having a plurality of wiring layers having different thicknesses and the thicker one being formed on an upper layer side. In a semiconductor integrated circuit having a wide range of synchronous circuits, a clock signal distribution circuit composed of a plurality of buffering stages has at least a part of a clock signal line on a signal source side which has a thicker wiring. Using a layer, and at least a part of the clock signal line on the signal source side, at least one of a power supply line and a ground line is run in parallel at least on one side near the laying, and further,
This problem has been solved by using the thinner wiring layer for at least a part of the clock signal lines on the terminal side in the clock signal distribution circuit. Hereinafter, the operation of the present invention will be briefly described. FIG. 1 is a circuit diagram showing a buffer used in a clock signal distribution circuit and its output wiring. On the output side of the buffer B, there is a capacitance C such as a load or a floating capacitance of a wiring. For this reason, the drive capability of the output transistor of the buffer B is required to reduce the skew and the delay time until the clock signal arrives, and the wiring resistance on the output side of the buffer B also needs to be suppressed. . Further, on the output side of the buffer B, there is an inductance component in the wiring. For this reason, in the clock signal distributed as shown in the time chart of FIG. 2, ideally, a waveform like a solid line rising at the time ta should be formed, but it becomes like a dashed line.
Further, if there is a reflected wave on the wiring, the waveform of the signal output from the buffer B and the reflected wave interfere with each other, as shown by the two-dot chain line. In the waveform of the two-dot chain line, the reflected wave arrives at the time tb, interferes with the waveform of the signal output from the buffer B, and a peak of the waveform occurs. According to the present invention, there is provided a semiconductor integrated circuit having a wide range of synchronous circuits having a plurality of wiring layers having different thicknesses and having a thicker thickness formed on an upper layer side and operated by a common clock signal. In the clock signal distribution circuit comprising a plurality of buffering stages,
At least some of the clock signal lines on the signal source side use the thicker wiring layer. Therefore, the wiring resistance of the clock signal can be suppressed, the skew can be reduced, and the delay time until the clock signal arrives can be reduced. Further, in the present invention, as shown in FIG. 3, at least one of a power supply line and a ground line runs in parallel on at least one side of at least a part of the clock signal line close to the laying thereof. . As a result, the return current of the inductance can be supplied very close, and the adverse effect of the inductance as described with reference to FIG. 2 can be suppressed. In addition, it is possible to suppress interference in the nearby parallel wiring driven by relatively weak driving capability due to crosstalk via the same layer of coupling capacitance, thereby suppressing adverse effects on other wirings. Note that, in FIG. 3, the broken lines are the power supply lines and the ground lines running parallel to at least one side near the clock signal laying as described above. Further, in the present invention, the wiring layer having a smaller thickness is used for at least a part of the clock signal lines on the terminal side in the clock signal distribution circuit. This makes it possible to improve the degree of integration by effectively utilizing the chip layout. In addition, since the clock signal can be prevented from becoming excessively sharp at the end of the clock signal distribution, the same layer can be connected to the neighboring parallel wiring driven by relatively weak driving capability. Interference due to crosstalk via the coupling capacitor can be suppressed. As described above, according to the present invention, the problem of skew relating to a clock signal widely used in a semiconductor integrated circuit, which tends to be difficult to cope with with the miniaturization of the semiconductor integrated circuit manufacturing technology, is suppressed. be able to. Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 4 is a sectional view of a semiconductor integrated circuit according to an embodiment to which the present invention is applied. In this figure, the cross-sectional structure of the present embodiment is schematically shown, and the diagonally lower right lines indicate the cross-section of the wiring with a thin wiring layer. The oblique line rising to the right indicates the cross section of the wiring by the wiring layer having a large film thickness. In this embodiment,
As an example, the first to sixth wiring layers are thin wiring layers. The seventh and eighth wiring layers are thicker wiring layers above the first to sixth wiring layers. Below these wiring layers, there are a transistor provided with a gate 2 above a channel portion formed on a substrate and a transistor provided with a gate 3 above a channel portion formed in a well 1. It is built in. Vias are connected between the gates, sources and drains of these transistors, wirings of a thin wiring layer, and wirings of a thick wiring layer. Or
They may be connected by stacked vias. The stack
A via is a via that extends over multiple wiring layers,
This is a via connecting between wirings formed in a wiring layer having no relation with a lower layer. FIG. 5 is a circuit diagram of the clock signal distribution circuit of the present embodiment. In this figure, the signal source of the clock signal of the clock signal distribution circuit is on the left side, and the terminal side of the clock signal of the clock signal distribution circuit is on the right side. In the clock signal distribution circuit, the buffer B is configured in a tree shape. Here, in the buffer B, the code B11
Is the first stage, B12 is the second stage, B13 is the third stage, B14 is the fourth stage, and B15 is the fifth stage. It is.
In FIG. 5, broken lines are power lines and ground lines laid in accordance with the present invention and run in parallel to at least one side of the clock signal laid. In this embodiment, a thick wiring layer is used for the clock signal wiring on the signal source side. Specifically, it is a portion of the clock signal in which the power supply line and the ground line are run in parallel, which is illustrated by the broken line as described above. As described above, in the present embodiment, the present invention can be effectively applied. Therefore, it is possible to suppress a problem of a skew relating to a clock signal widely used in the semiconductor integrated circuit, which tends to be difficult to cope with with the miniaturization of the manufacturing technology of the semiconductor integrated circuit. According to the present invention, the problem of skew relating to a clock signal widely used inside a semiconductor integrated circuit, which tends to be difficult to cope with with the miniaturization of the manufacturing technology of the semiconductor integrated circuit, is solved. Can be suppressed.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram showing a buffer used in a clock signal distribution circuit and its output wiring. FIG. 2 is a time chart showing a waveform of a clock signal. FIG. 3 is a clock signal distribution circuit of the present invention. FIG. 4 is a cross-sectional view of a semiconductor integrated circuit according to an embodiment to which the present invention is applied. FIG. 5 is a circuit diagram of a clock signal distribution circuit according to the embodiment. Circuit diagram of a basic clock signal distribution circuit using a large number of buffers in a tree shape [Description of References] 1 ... Well 2, 3 ... Gate B, B11-B15 ... Buffer C ... Capacitance FF ... Flip-flop GND ... Ground

Continuation of front page    F term (reference) 5B079 BC03 CC20 DD08 DD13                 5F038 CD02 CD06 CD08 CD09 CD12                       CD13 EZ20                 5F064 BB26 EE09 EE19 EE23 EE42                       EE43 EE46 EE47 EE52 EE54                 5J039 EE10 EE13 KK09 KK13 MM16

Claims (1)

Claims: 1. A wide range of synchronous circuits having a plurality of wiring layers having different thicknesses and having a thicker thickness formed on an upper layer side and operated by a common clock signal. In a semiconductor integrated circuit, a thicker wiring layer is used for at least a part of a clock signal line on a signal source side in a clock signal distribution circuit including a plurality of buffering stages; At least one of a power supply line and a ground line is run in parallel to at least one side of the clock signal line on at least one side thereof near the laying, and further, at least a part of a terminal side in the clock signal distribution circuit. Wherein the wiring layer having a smaller thickness is used for the clock signal line.