JP2000216263A - Semiconductor circuit using field effect transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve operation speed of a semiconductor circuit and to make the design of the circuit easier by providing a layout which can reduce the parasitic capacitance and wiring resistance of the circuit. SOLUTION: A plurality of gate poly-wirings 5 are drawn in a semiconductor circuit from one sides of rectangular fields 4, and drain wires 6 are drawn in the circuit from the opposite sides of the fields 4. Then source wiring is connected to third wiring through through-holes 7. In addition, the parasitic capacitance of a semiconductor circuit is further lowered by only forming the drain wires 6 near the end sections of the rectangular fields 4.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor circuit using a MOS transistor, and more particularly, to a semiconductor circuit which can cope with a high speed operation and can reduce a parasitic capacitance.
It relates to the layout of S transistors.

[0002]

2. Description of the Related Art Generally, in a semiconductor circuit including a plurality of field effect transistors, the wiring width and the wiring interval of an integrated circuit are being reduced with the advance of fine processing technology, and the demand for high-speed operation as a product is rapidly increasing. . Many solutions to such a request have been proposed in the past.
A first conventional example as one type of this solution will be described with reference to FIG. The layout of the CMOS transistor element of the semiconductor logic circuit is such that the PMOS region and the NMOS region are opposed to each other as shown in the figure, and the gate poly wiring and the drain metal wiring are drawn in a direction perpendicular to the PN separation line.
They are arranged for each of the MOS and NMOS elements. VCC input to the PMOS is pulled in by metal from the opposite side of the PN separation, and GN input to the NMOS
D is also drawn in with metal from the opposite side of the PN separation. The reason for adopting such a basic layout is that a plurality of similar logic blocks are arranged side by side (in the direction parallel to the PN separation) so that the input signal and the output signal of the logic gate are PMO.
This is because the connection is easily performed between the S and the NMOS. In addition, a power supply line (VC
C, GND) is located on the opposite side of this area, so that it does not interfere with input / output signals.

Since the adjustment of the transistor size is usually performed with the gate width (W), it can be realized by simply extending the field of the MOS transistor in the VCC or GND direction while maintaining this basic configuration. This is because PMOS or NM is connected from VCC or GND common wiring.
If the source metal wiring to the OS region is set with a relatively long margin, the adjustment of W becomes very easy. This can be easily incorporated even in recent automatic design (CAD), and in fact, design efficiency has been improved. Next, a second conventional example is shown in FIG.
Explanation will be made using 0. M as a high-speed switching element
There is a high-frequency device in an environment where an OS transistor is used, and in such a product design, a layout of a MOS transistor element as shown in the figure has been proposed in order to emphasize high-frequency characteristics (Japanese Patent Laid-Open No. 2-54540). In this example, if the distance between the power supply line and the source lead line becomes long, the wiring resistance of this part cannot be ignored and the frequency characteristics deteriorate, so the layout configuration is such that the source lead line and the drain output line are drawn from the opposite side of the gate input side. ing. However, this configuration is considered as a single device, and PMOS and NM using such a transistor element are used.
No consideration is given to a layout configuration as a logic circuit combining OSs or an integrated circuit combining many of them.

[0004]

The disadvantages of these prior arts are as follows. In the first conventional example,
Due to an increase in the resistance of the gate poly wiring, the wiring delay in the transistor region cannot be ignored. This is because the maximum allowable length (Wmax) of the poly wiring is smaller than the transistor size which is usually used frequently. However, the layout is divided into several gates as shown in FIG. ing. However, at present W
As the extreme reduction of max progresses, as another adverse effect, speeding up has been hindered. The first problem is a wiring resistance delay due to an increase in the drawing distance of the gate poly wiring. This is because the drain output metal is drawn out from the gate input side, so that the poly wiring distance is increased to pass under this metal.

The second conventional example provides a layout for minimizing the gate poly lead distance.
When considering an OS logic circuit, there is no problem as a single transistor because the drain output side goes out to the power supply side that is farthest away, but as a logic integrated circuit, an area increase and a speed delay due to an increase in wiring distance occur. It cannot be a realistic measure. The second problem is an increase in parasitic capacitance generated between the gate poly wiring and the source and drain wirings. In particular, an increase in the capacitance between the gate and the drain causes a potential change in the positive and negative directions with respect to a change in the potential on the input side (mirror effect). A third problem is a speed delay due to an increase in the source-drain wiring capacitance. The increase in resistance due to the routing of the source wiring, which is shown in the second conventional example for a high-frequency device, has a smaller effect on speed due to advances in multilayer wiring and its connection technology (through-hole). Even if the increase in capacitance between wirings is several tens
Even if the wiring is not as long as 0 μm or more, it cannot be ignored as a factor that hinders high speed operation in a logic integrated circuit. In other words, if the capacitance can be reduced even for a short wiring in a functional block, the load on the preceding logic gate that drives it can be reduced, and the transistor size can be reduced.
Further, the load on the circuit at the preceding stage can be reduced, and the speed can be increased. In recent manufacturing processes of 0.3 μm or less, about 20% of the actual logic gate delay time is due to these effects.

[0006] The reason why the above-mentioned problem occurs is as follows. The first problem is that it is necessary to shorten the distance of the gate poly wiring in the transistor to prevent a speed delay, and at the same time, to shorten the pull-in distance of the gate poly wiring. For this purpose, the drain output is taken from another side from the gate input. Means are required (an example is the second conventional example). However, this example does not have a basic element layout suitable for forming a logic circuit by combining PMOS and NMOS. The second problem is that the distance between the gate metal or gate poly wiring and the drain metal wiring is reduced due to the progress of fine processing technology, and furthermore, the parasitic capacitance is increased because a part of the layout is close or overlapped. The resulting speed delay. The third problem is that the spacing between the source metal wiring and the drain metal wiring is reduced due to the progress of microfabrication technology and the parasitic capacitance is increasing. This is the speed delay that occurs. In other words, in order to solve the above-mentioned problems, the layout area is increased, or the ease of design such as the ease of adjusting the transistor size shown in the first conventional example is sacrificed. It is the current situation.

[0007]

According to the present invention, a plurality of gate poly wirings are drawn from a first wiring extending along one side of a field quadrilateral into the field quadrilateral. A plurality of drain (or source) wirings connected to a second wiring disposed in a space between the adjacent gate poly wirings and extending along another side of the field quadrilateral in parallel with the first wiring and the adjacent wirings; The drain (or source) in the space between gate poly wirings
And a third wiring connected through a through hole to a source (drain) layer in a space where no wiring exists. In addition, the present invention includes a mode in which both the drain layer and the source layer are connected to the third wiring through the through holes. In the present invention, by appropriately laying out and connecting the gate, source and drain wirings as described above, the drawing distance of the gate poly wiring is minimized, the parasitic capacitance between the gate, the source and the drain is reduced, and the inside of the transistor is reduced. There is provided a semiconductor circuit in which a PMOS and an NMOS are laid out in a layout in which a poly wiring length is standardized within an allowable range of delay due to wiring resistance. Higher speed can be realized by using the layout means in which the resistance and the capacitance are reduced, and at the same time, the area is reduced and the continuity of the current layout design style, that is, the design easiness is excellent. In the present invention, a wiring connected to a gate poly is a first wiring, and a wiring connected to a drain or a source extending along another side opposite to one side of the field quadrilateral extending along the first wiring is a second wiring. The wiring connected to the drain or source through the through hole is referred to as a third wiring.

[0008]

BEST MODE FOR CARRYING OUT THE INVENTION Preferred embodiments of the present invention will be described below, but these embodiments are illustrative of the present invention and do not limit the present invention. FIG. 1 is a circuit diagram showing a first embodiment of the present invention. P-type MOS transistor (PMOS) 2 and N-type MOS transistor (NMOS) on both sides of the PN element isolation line 1
A field quadrilateral 4 which is an active region of No. 3 is set. The gate input signal runs from a first layer aluminum (1AL) wiring which runs perpendicular to the PN separation line and is arranged at the side of each field, and a plurality of the wirings are provided therefrom in a direction parallel to the PN separation. The gate poly wiring 5 is drawn into the transistor. A drain line 6 for extracting a signal through a drain contact is formed from the side of the field quadrilateral 4 on the opposite side to which the gate is input, toward the field quadrilateral side. Here, the drain line 6 is extracted. It is formed only in a part of the portion near the field side, in other words, the tip of the drain wiring 6 is located in the field quadrilateral 4 near the end of the field quadrilateral. This arrangement can be achieved by using a technique (salicide structure) of silicidizing the silicon surface forming the source and drain diffusion layers. This is because the drain diffusion layer resistance is reduced by several orders of magnitude, so that even if the contact is not made over the entire distance of the gate width W, the effect of the increase in resistance can be ignored.

A portion in which similar drain lead lines from the PMOS transistor 2 and the NMOS transistor 3 are vertically connected to the PN separation by a second wiring (2AL) is defined as a drain output. The highest power supply potential (VCC), which is the source terminal on the PMOS2 side, is pulled up by one or several contacts to a part of the source diffusion layer, and further through-hole contacts (TH) connected to the third-layer aluminum wiring (3AL) )
Power is supplied to 3AL through 7. Similarly, the power supply connected to the source terminal is the lowest power supply potential (G
ND), but this wiring is separated from VCC by a PN separation region. In such a layout, P
Since neither the input pull-in signal nor the output signal is output between the MOS2 and the NMOS3, the distance between the PN transistors can be reduced.

The field length in the direction parallel to the PN separation line is a maximum distance Wmax which can be ignored as the gate poly delay time in the transistor. This distance is originally different between the PMOS 2 and the NMOS 3, but in this example, it is assumed that the distance is the same for the sake of simplicity.
If there is no large difference between N, the values will be almost the same, but since L of the PMOS is usually set to be relatively large, P
The Wmax of the MOS is slightly larger). Depending on the transistor size adjustment at the time of design, PMOS2 and NMO
Although the gate widths Wp and Wn of S3 increase, in this case, the size is increased by separating the gate into a plurality of gates in units of Wmax and alternately arranging the source and drain diffusion layers. FIG. 2 shows a layout means accompanying an increase in W. When W <3Wmax, the same as in the first conventional example, the gate poly is arranged in the vertical direction with the PN separation.
However, when W> 3Wmax, as shown in FIG. 1, the gate poly is arranged in the direction parallel to the PN separation as in the present embodiment.

In the first embodiment shown in FIG. 1, the leading portion of the gate poly wiring to the transistor activation region is divided into a plurality of lines from one side of the field quadrilateral 4 perpendicular to the PN separation line and input. . When the drain output is from the opposite side of this field and the source power line is 2AL
, The layout configuration is inputted from the side opposite to the PN separation side. For this reason, the length of the gate poly wiring can be drawn with the minimum distance, so that the resistance rise in this portion can be reduced to a ratio that can be almost ignored. In addition, the parasitic capacitance of the source and drain AL contacts with respect to the gate poly wiring and the parasitic capacitance of the wiring portion can be reduced because the area of the contact and the AL wiring is reduced. Further, since the source AL region is provided between the gate AL wiring and the drain AL wiring, the gate-to-AL wiring between the AL wirings is provided.
The Miller effect of the drain-to-drain capacitance does not occur completely or hardly occurs. Further, since the positions of the source side and drain side contacts are shifted with the gate poly interposed therebetween, there is also an effect of reducing the source-drain capacitance. Also, PMOS2 and NMOS
Since there are no other elements between the three separations, the distance between them can be reduced to a minimum, and in particular, a CMOS having a small W size is used.
In the case of a logic circuit, the reduction of the AL wiring distance also has the effect of increasing the speed. In such a layout based on the salicide transistor structure, the resistance of the diffusion layer is so small as to be negligible. Therefore, it is more advantageous to reduce the parasitic capacitance than to increase the resistance slightly, in order to increase the speed. With this layout, the speed of the logic circuit stage can be increased by 10 to 15% as compared with the conventional example.

On the other hand, with respect to the effect of the W size on the layout, the layout is formed by the conventional format when the size is smaller than the boundary of three gate poly divisions (W = 3 Wmax), and by the layout of the present embodiment when the size is larger. . As a result, even when the size of a transistor having a large W is changed, a significant change in the horizontal distance (block size in the PN separation direction) does not occur. FIG. 2 shows an example of the conventional method due to the variation in W size. However, since the width increases sharply with an increase in W, a large number of signals connecting between logic gates also increase with this, and the parasitic capacitance and resistance increase. Invite an increase. In addition to such deterioration in characteristics, changing the W of one transistor changes the physical positions of many logic gates, which requires a lot of time and effort to correct changes in layout design. On the other hand, when W shown in FIG. 3 has a large size and extends in the vertical direction (PN separation and vertical direction) in units of the number of gates, it is similar to the conventional method in the case where there is a margin in Wmax, and attention was paid to it. Only the transistors are changed, and the distance between many other logic blocks is not changed. Therefore, the trouble of changing the layout is minimized, and the speed is not degraded due to the extension of a large number of wiring lengths at the same time.

Here, the switching point in the gate poly direction in this embodiment is set to 3 Wmax. This is because the field distance in the vertical direction of the gate poly overtakes the field distance in the parallel direction when the number is four or more. Wma
Since the x value varies depending on the process conditions and device design standards, the optimum number of switches may be set for each condition. However, since it is expected that Wmax will be further reduced in the future, the number of switching will be reduced, and the ratio of the layout method of the present invention will be increased. By incorporating an algorithm that incorporates this rule in layout design automation, the degree of freedom is close to the feel of the current automatic layout design, and the block area does not fluctuate significantly with each modification. It is possible to build an environment.

Next, a second embodiment of the present invention will be described with reference to FIG. 4. This embodiment and the following third to sixth embodiments relate to improvements of the first embodiment. The same elements as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted. In this example, the source power supply wiring 6a is drawn from the opposite side of the field side where the gate signal is drawn in the first embodiment. This is because several contacts and AL wiring regions are provided in a portion of the source diffusion layer region close to the side opposite to the gate wiring, the AL wiring is extended outside the field from there, and a plurality of these leads are collectively connected to the power supply wiring. ing. In the region between the field edge on the gate input side and the source contact, a contact with the drain diffusion layer and an AL wiring region are formed. There are also several contacts, and only 1AL is limited to the area surrounding the contact.
H7 is provided. TH7 rising from the drain region divided into a plurality is connected, and a signal is output to the next stage logic circuit. Since the drain output is 2AL, it can freely cross the gate and source signals formed by 1AL. Therefore, the degree of freedom in interconnecting the signal lines of the logic circuit is increased, and the area can be reduced and the wiring length can be reduced. Also, since the area of the drain wiring is large due to the 2AL, there is an effect of reducing the capacitance due to the difference in the AL layer between the gate and the source input. Compared to the first embodiment, the gate
The reduction of the mirror effect between the drains is slightly inferior. Although the drain 2AL signal is extended to the source AL side in the drawing, it may be extended to the gate 1AL side and pass over it. (Refer to the drain 2AL drawing part in Fig. 5)

Next, a third embodiment of the present invention will be described with reference to FIG. In this example, unlike the first and second embodiments, it is assumed that the salicide technique cannot be used in the diffusion layer region. This increases the resistance of the diffusion layer,
The number of contacts of the source and the drain needs to be fully provided by the distance of the gate poly W, and naturally the 1AL wiring disposed thereon must also be disposed in parallel with the gate poly wiring. FIG. 5 shows an example in which only 1AL is used for extracting the source and 2AL is used for extracting the drain signal. The portion where the drain is pulled up to 2AL by TH can be crossed with the gate and drain 1AL layer by pulling up from the 1AL region located on the diffusion layer region, thereby facilitating signal layout between logic circuits. Although the effect of reducing the capacitance between the gate poly and the source / drain 1AL layer is lower than that of the first or second embodiment, 1AL
There is no drain signal from the field due to the increase of the pull-in distance of the gate poly wiring, and there is a significant effect of reducing the drain-source and drain-gate capacitance between 1ALs. That is,
This shows that the high-speed property of the present invention can be applied even to a product that focuses on eliminating the salicide process and reducing the manufacturing cost, and can be said to be one of the most suitable embodiments for cost performance.

Next, a fourth embodiment will be described with reference to FIG. In this example, a through-hole (TH) 7 is provided in a 1AL region provided on the source and drain diffusion layers, and both signals are led out by 2AL.
In this figure, since the case where the salicide technique is not used is shown as an example, a contact is formed over the entire diffusion layer region. Since the source or drain signal is not drawn out from the field side opposite to the gate poly input side at 1AL, the area of the lead line portion is further reduced. Since one to several THs are sufficient for the source and the drain, each of the diffusion layers alternately separated can be connected to the gate poly by a 2AL line running in the vertical direction. MO
Since two 2ALs need only be passed through the width of Wmax of the S transistor, it is not necessary to make the wiring interval close to a distance at which parasitic capacitance becomes a problem, and the increase in capacitance due to this layout is slight. However, when the drain output signal is extended in the direction in which the source 2AL is arranged, there is a restriction that the signal line must be bypassed.
Depending on the product specifications and the complexity of the logic block circuit to be realized, the area reduction effect may be higher than in other embodiments.

Next, a fifth embodiment will be described with reference to FIG. In this example, the length of one side of the field quadrilateral in the direction in which the gate poly wiring signal runs is twice Wmax, and the gate poly is contacted from the AL wiring at the center of the transistor region. By driving the gate poly from the center, the influence of the resistance of the poly wiring in the transistor can be reduced by one.
/ 2, so that the Wmax value can be doubled. In the future, if the Wmax value is extremely reduced, the effect will be particularly high when used in combination with other embodiments.

Finally, a sixth embodiment will be described with reference to FIG. In this example, a method of connecting a plurality of stages of the logic circuit layout according to the first embodiment is shown. As the simplest example, FIG. 10B shows a drive buffer circuit in which inverter circuits having a large W value are connected in two stages. FIG. 10 (a)
Although the drain AL wiring, which is the output of the first-stage inverter, is arranged vertically across the PN separation,
This connects the PMOS side and the NMOS side and also serves as the AL wiring for the gate input of the second-stage inverter. By connecting the logic gates in this manner, the effect of the first embodiment for reducing the parasitic resistance and the capacitance is obtained, and at the same time, the distance of the AL wiring signal between the logic circuits is minimized. This indicates that there is a sufficient effect of reducing the area in addition to increasing the speed.

[0019]

According to the present invention, by appropriately laying out each wiring, the drawing distance of the gate poly wiring is minimized, the parasitic capacitance between the gate, source and drain is reduced, and the length of the poly wiring in the transistor is reduced. PMOS and NMO standardized within tolerance of delay due to resistance
A semiconductor circuit in which S is laid out can be provided. Higher speed can be realized by using the layout means in which the resistance and the capacitance are reduced, and at the same time, the area is reduced and the continuity of the current layout design style, that is, the design easiness is excellent.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of a semiconductor device according to the present invention.

FIG. 2 is a schematic diagram showing an example of connecting a relatively small number of semiconductor units.

FIG. 3 is a schematic diagram showing an example of connecting a relatively large number of semiconductor units.

FIG. 4 is a circuit diagram showing a second embodiment of the semiconductor device according to the present invention.

FIG. 5 is a circuit diagram showing a third embodiment of the semiconductor device according to the present invention.

FIG. 6 is a circuit diagram showing a fourth embodiment of the semiconductor device according to the present invention.

FIG. 7 is a circuit diagram showing a fifth embodiment of the semiconductor device according to the present invention.

FIG. 8 is a circuit diagram showing a sixth embodiment of the semiconductor device according to the present invention.

FIG. 9 is a circuit diagram showing a first conventional example of a semiconductor device.

FIG. 10 is a circuit diagram showing a second conventional example of a semiconductor device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 PN element isolation part 2 PMOS transistor 3 NMOS transistor 4 Field quadrilateral 5 Gate poly wiring 6 Drain wiring 6a Source wiring 7 Through hole

 ──────────────────────────────────────────────────続 き Continued on the front page F-term (reference)

Claims (10)

[Claims] 1. A semiconductor circuit using a field-effect transistor in which NMOS and PMOS transistors each having a gate, a source, and a drain, which are arranged on a semiconductor substrate, are arranged via a PN separation part.
A plurality of gates are drawn into the field quadrilateral from the first gate wiring extending in the vicinity of the field quadrilateral surrounding the gate, source and drain along one side of the field quadrilateral and perpendicular to the PN separation part. A parallel gate poly wiring, a second wiring parallel to the first wiring and extending along another opposite side of the field quadrilateral is drawn into the field quadrilateral, and the tip thereof is between the adjacent gate poly wirings. A plurality of drain wirings located in a required space of the space, and a source wiring connected to the third wiring via a through hole formed in a space between the adjacent gate poly wirings where the drain wiring does not exist. A semiconductor circuit, comprising: 2. The field quadrilateral, wherein the tip of the drain wiring is located near the end of the field quadrilateral in the field quadrilateral.
3. The semiconductor circuit according to claim 1. 3. A semiconductor circuit using a field effect transistor in which an NMOS and a PMOS transistor each having a gate, a source, and a drain disposed on a semiconductor substrate and disposed via a PN separation part are provided.
A plurality of gates are drawn into the field quadrilateral from the first gate wiring extending in the vicinity of the field quadrilateral surrounding the gate, source and drain along one side of the field quadrilateral and perpendicular to the PN separation part. A parallel gate poly wiring, a second wiring parallel to the first wiring and extending along another opposite side of the field quadrilateral is drawn into the field quadrilateral, and the tip thereof is between the adjacent gate poly wirings. A plurality of source wirings located in a required space of the space, and a drain wiring connected to a third wiring via a through hole formed in a space between the adjacent gate poly wirings where the source wiring does not exist. A semiconductor circuit, comprising: 4. The semiconductor circuit according to claim 1, wherein a tip of the source wiring is located near an end of the field quadrilateral in the field quadrilateral. 5. A semiconductor circuit using a field-effect transistor in which NMOS and PMOS transistors each having a gate, a source, and a drain and disposed on a semiconductor substrate and arranged via a PN separation portion are provided.
A plurality of gates are drawn into the field quadrilateral from the first gate wiring extending in the vicinity of the field quadrilateral surrounding the gate, source and drain along one side of the field quadrilateral and perpendicular to the PN separation part. , A drain wiring connected to a third wiring via a through hole formed in a required space between adjacent gate poly wirings, and a through-hole formed in a space where the drain wiring is not formed. A semiconductor circuit comprising a source wiring connected to a third wiring via a hole. 6. A field-effect transistor which is disposed on a semiconductor substrate and includes an NMOS and a PMOS transistor each including a gate, a source and a drain via a PN separation unit, wherein the gate, the source and the drain are used. A plurality of parallel gate poly wirings drawn into the field quadrilateral from the first gate wiring extending in the vicinity of the surrounding field quadrilateral along one side of the field quadrilateral and along the direction perpendicular to the PN separation part; A semiconductor circuit comprising a drain wiring contact and a source wiring contact alternately formed in a plurality of spaces formed between adjacent wirings among a plurality of gate poly wirings, wherein a gate wiring for the drain wiring contact and a source wiring contact is formed. Semiconductors characterized by shifting the relative position across the wiring circuit. 7. A field-effect transistor in which NMOS and PMOS transistors each having a gate, a source, and a drain disposed on a semiconductor substrate and disposed via a PN separation unit is used. A plurality of parallel gate poly wirings drawn into the field quadrilateral from the first gate wiring extending in the vicinity of the surrounding field quadrilateral along one side of the field quadrilateral and along the direction perpendicular to the PN separation part; In a semiconductor circuit in which a drain wiring contact and a source wiring contact are alternately formed in a plurality of spaces formed between adjacent wirings among a plurality of gate poly wirings, a drain or a source is formed outside the field quadrilateral through the contact and the wiring. In the area near the edge of the field quadrilateral A semiconductor circuit comprising one or two or more contacts. 8. A field effect transistor in which NMOS and PMOS transistors respectively disposed on a semiconductor substrate and including a gate, a source, and a drain are disposed via a PN separation unit, wherein the gate, the source, and the drain are used. A plurality of parallel gate poly wirings drawn into the field quadrilateral from the first gate wiring extending in the vicinity of the surrounding field quadrilateral along one side of the field quadrilateral and along the direction perpendicular to the PN separation part; In a semiconductor circuit in which a drain wiring contact and a source wiring contact are alternately formed in a plurality of spaces formed between adjacent wirings of a plurality of gate poly wirings, a drain or a source is formed through a field quadrilateral through the contact and the through hole. When pulled out, the area below the through hole A semiconductor circuit, wherein one or two or more contacts are provided only in the semiconductor circuit. 9. A field effect transistor in which NMOS and PMOS transistors each having a gate, a source, and a drain disposed on a semiconductor substrate are disposed via a PN separation unit, and the gate, the source, and the drain are used. A plurality of parallel gate poly wirings drawn into the field quadrilateral from the first gate wiring extending in the vicinity of the surrounding field quadrilateral along one side of the field quadrilateral and along the direction perpendicular to the PN separation part; In a semiconductor circuit in which a drain and a source are alternately formed in a plurality of spaces formed between adjacent wirings among a plurality of gate poly wirings, a relationship between a gate width (W) and a maximum allowable length (Wmax) of the poly wiring is determined. In the case of W <3Wmax, the gate poly wiring is arranged in the vertical direction with the PN separation, and W> 3W
In the case of max, a semiconductor circuit characterized in that a gate poly wiring is arranged in a direction parallel to the PN separation. 10. A field effect transistor, wherein NMOS and PMOS transistors respectively disposed on a semiconductor substrate and each including a gate, a source and a drain are disposed adjacent to each other via a PN separation part, wherein said gate, source and drain are used. A plurality of parallel gate poly wirings drawn into the field quadrilateral from the first gate wiring extending in the vicinity of the field quadrilateral surrounding the field quadrilateral along one side of the field quadrilateral and perpendicular to the PN separation part; A required space of the space between the adjacent gate poly wirings is drawn into the field quadrilateral from a second wiring parallel to the first wiring and extending along the other opposite side of the field quadrilateral and the tip thereof is provided. A plurality of drain wirings located in the same area, and the adjacent gate poly where the drain wiring does not exist. In a plurality of semiconductor circuits including a source wiring connected to a third wiring via a through hole formed in a space between the wirings, the drain wiring on the former stage also serves as a wiring for gate poly input in the latter stage. A semiconductor circuit characterized by the above-mentioned.