JP2009239316A - Crosstalk prevention circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a circuit which reduces or removes crosstalk in a method which does not affect microfabrication or improvement in integration degree. <P>SOLUTION: The crosstalk prevention circuit includes a third signal line 13 between two signal lines formed almost in parallel to each other, for example, master clock and slave clock lines l1 and l1, the third signal line being grounded when there is no signal applied to at least one of those two signal lines, for example, when a test signal is applied and the signal is applied to the two signal lines. Preferably, a driver circuit is connected to the third signal line, and ratio of current driving capabilities of an N-channel transistor and a P-channel transistor as output transistors of the driver circuit is almost 2:1. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a circuit that reduces the influence of crosstalk in an electronic circuit, and in particular, reduces the influence of crosstalk in a digital signal processing device (DSP), an IC, and other semiconductor devices, or the influence of crosstalk. The present invention relates to a crosstalk prevention circuit for removing noise.

As the electronic circuit, a circuit formed in a semiconductor device, for example, a digital signal processing circuit (DSP), a microprocessor, a memory circuit, and the like will be described.
Various attempts have been made to reduce the size and increase the operating speed of semiconductor devices. However, in such a circuit, an obstacle to speeding up due to signal propagation delay in the signal line is encountered.

The signal propagation delay in the signal line is mainly determined by the wiring resistance, the parasitic capacitance (parasitic capacitance), and the wiring capacitance (wiring capacitance) in the semiconductor device, for example, a metal oxide semiconductor device (mos device).
In the manufacturing process up to about 0.8 μm, the capacitance between the wiring and the semiconductor substrate mainly dominates the wiring capacitance. However, as microfabrication progresses, the distance between adjacent wirings in a semiconductor device becomes shorter, and the capacitance between adjacent wirings cannot be ignored. In the manufacturing process after 0.6 μm, wiring is performed at the minimum pitch. In this case, the capacitance between adjacent wirings occupies 90% or more of the total capacitance.

Crosstalk increases due to an increase in the capacitance between wires. Increased crosstalk increases signal delay. Such signal delay caused by crosstalk causes various problems.
For example, when crosstalk occurs in the clock wiring, performance deterioration due to clock delay may occur, and in a two-phase clock, there is a possibility that a skew (phase shift) occurs between the two-phase clocks.
Also, when crosstalk occurs on the bus line, the delay due to crosstalk limits the operating speed of the IC. In other words, it can be said that the crosstalk determines the operation speed of the IC.
Other electronic circuits also have problems such as skew caused by crosstalk similar to that described above, a reduction in operating speed, and malfunction due to pulse signal distortion.

  In general, various attempts have been made to prevent such crosstalk. For example, there is a method of separating two adjacent wirings, but it cannot be applied to a semiconductor device and a semiconductor circuit that are becoming finer because the area increases.

Another common method is to take a shield. However, when a shield is applied, an area is required for the shield construction.
The requirement for a new area for shield construction is not applicable to semiconductor devices, ICs, and the like that further improve the miniaturization and integration.

  Accordingly, it is an object of the present invention to provide a circuit that reduces or eliminates crosstalk in a manner that does not affect the miniaturization and improvement in integration.

  According to the first aspect of the present invention, a signal is applied when there is no signal applied to at least one of the two signal lines between at least two signal lines formed substantially in parallel. In addition, a crosstalk prevention circuit is provided in which a third signal line that is grounded when a signal is applied to the two signal lines is disposed.

  Preferably, a driver circuit is connected to the third signal line, and the ratio of the current drive capability of the N-channel transistor and the P-channel transistor of the output transistor of the driver circuit is approximately 2: 1.

  Preferably, a first clock and a second clock having a predetermined phase difference from the first clock are applied to the first and second signal lines, and a test operation is applied to the third signal line. Sometimes applied signals are applied.

  Preferably, the first and second signal lines are signal lines whose voltage changes according to a first signal, and the third signal line changes in voltage according to a signal having a phase different from that of the first signal. Signal line.

  According to the second aspect of the present invention, the first power metal wiring and the second power metal wiring are provided in parallel at a predetermined distance on both sides of the metal signal wiring through which the pulse signal is propagated. There is provided a crosstalk prevention circuit having a wiring characterized in that the metal signal wiring and the first and second power supply metal wirings have widths that improve resistance to electromigration.

  Preferably, even when the metal signal wiring, the first power metal wiring, and the second power metal wiring are in different layers, the metal signal wiring is the first power metal wiring and the second power metal wiring. It is provided to be surrounded.

According to the first aspect of the present invention, the influence of crosstalk can be reduced without increasing the area.
Further, the present invention does not require any special advanced technology and can be easily implemented.

  According to the second aspect of the present invention, it is possible to completely eliminate the problem of delay and function failure due to crosstalk while suppressing the increase in area by utilizing the property of electromigration.

In FIG. 1, the master clock 1mt wiring l1 and the slave clock 1st wiring l2 are arranged adjacently and in parallel in an ideal state in which the influence of crosstalk is not taken into consideration. FIG. 6 is a circuit diagram for propagating a master clock 1mt and a slave clock 1st through the network. FIG. 2 differs from FIG. 1 in that the wiring 11 for the master clock 1mt and the wiring l2 for the slave clock 1st are arranged adjacent to each other in parallel in the state in which the influence of crosstalk is taken into consideration. FIG. 6 is a circuit diagram for propagating a master clock 1mt and a slave clock 1st through DR2. FIG. 3 is a diagram illustrating various crosstalk modes. FIG. 4 is a diagram illustrating the occurrence of crosstalk from adjacent circuits electrically connected via capacitance. FIGS. 5A to 5C show how the crosstalk receiver is affected by the signal transition state of the signal that receives the crosstalk (crosstalk receiver) and the change (change timing) of the adjacent crosstalk sources 1 and 2. It is the graph which illustrated the result of analysis. FIG. 6 is a characteristic diagram of the rise time of the master clock 1mt in FIG. FIG. 7 is a characteristic diagram of the fall time of the master clock 1mt in FIG. FIG. 8 is a characteristic diagram of the gate delay time viewed from the rising edge of the master clock 1mt in FIG. FIG. 9 is a graph illustrating signal changes when the crosstalk between the wirings of the master clock 1mt and the slave clock 1st in FIG. 2 is considered and when the crosstalk is not considered. FIG. 10 is a crosstalk prevention circuit diagram of the first embodiment of the present invention. FIG. 11 is a characteristic diagram of the rise time of the master clock 1mt in FIG. FIG. 12 is a characteristic diagram of the fall time of the master clock 1mt in FIG. FIG. 13 is a circuit diagram as an embodiment of the crosstalk prevention circuit illustrated in FIG. FIG. 14 is a signal waveform diagram when the P / N ratio of the output transistor of the driver circuit DR3 is 80 μm / 2 μm = 40: 1 in FIG. 13 and only the slave clock 1st is applied to the wiring l2. FIG. 15 shows a signal waveform when the P / N ratio of the output transistor of the driver circuit DR3 is 80 μm / 2 μm = 40: 1 in FIG. 13, the master clock 1mt is applied to the wiring l1, and the slave clock 1st is applied to the wiring l2. FIG. FIG. 16 shows signal waveforms when the P / N ratio of the output transistor of the driver circuit DR3 is 80 μm / 4 μm = 20: 1 in FIG. 13, the slave clock 1st is applied to the wiring 12, and the test clock 1tt is applied to the wiring 13. FIG. FIG. 17 is a graph showing the influence of crosstalk on the master clock 1mt when the wiring 13 of the test clock 1tt is used as a shield in FIG. FIG. 18 is a graph showing the influence of crosstalk on the slave clock 1st when the wiring 13 of the test clock 1tt in FIG. 13 is used as a shield. FIG. 19 is a graph showing the influence of crosstalk on the wiring l3 of the test clock 1tt used as a shield in FIG. FIG. 20 shows a bus wiring circuit in the case where crosstalk is not considered as the second embodiment. FIG. 21 shows a bus wiring circuit in consideration of crosstalk as the second embodiment. FIG. 22 is a graph showing the influence of crosstalk on bus wiring. FIG. 23 is a circuit diagram of a bus wiring circuit as a second embodiment of the present invention. FIG. 24 is a graph showing the influence of crosstalk on bus wiring. FIG. 25 is a graph showing the influence on the bus smt2 whose value changes due to the change of the master clock when a bus whose value changes due to the change of the slave clock is used as a shield. FIG. 26 is a graph showing the influence on the bus smt1 whose value changes due to a change in the master clock when a bus whose value changes due to a change in the slave clock is used as a shield. FIG. 27 is a graph showing the influence on the bus whose value changes due to the change of the slave clock used as a shield. FIG. 28 is a conventional wiring diagram. FIG. 29 shows a signal wiring diagram for preventing crosstalk in consideration of electromigration as a third embodiment. FIG. 30 is an illustration of the fourth embodiment.

First Embodiment As a first embodiment of the crosstalk prevention circuit of the present invention, it is applied to a two-phase clock circuit used as an internal clock of an arithmetic control unit (CPU) in a semiconductor device (semiconductor device) such as a DSP or an IC. The case where it did is illustrated.
In order to test a circuit by operating as a master clock 1mt, a two-phase clock of the master clock 1mt and a slave clock 1st having a predetermined phase difference from the master clock 1mt as well as a test when the master clock 1mt does not operate An example will be described in which three clocks of the test clock 1tt used in the above are provided.
The master clock 1mt and the slave clock 1st are active clocks during operation of the semiconductor device, and the test clock 1tt is grounded during normal operation of the semiconductor device so as not to affect normal operation.

The three wirings of the master clock 1mt, the slave clock 1st, and the test clock 1tt are normally wired (wired) almost parallel to the entire CPU. Normally, as illustrated in FIG. 1, a wiring 11 for the master clock 1mt and a wiring 12 for the slave clock 1st are disposed adjacent to each other. Therefore, the master clock 1mt and the slave clock 1st are affected by crosstalk.
In order to know the extent of the influence of the crosstalk, the present inventor prepared a simple model considering only the capacitance, and performed a simulation using a simulation model “spice”.

In FIG. 1, the master clock 1mt wiring l1 and the slave clock 1st wiring l2 are arranged adjacent to each other in parallel in an ideal state in which the influence of crosstalk is not taken into consideration, and the driver circuits DR1 and DR2 are respectively connected. FIG. 6 is a circuit diagram of a clock supply circuit (two-phase clock circuit) that propagates a master clock 1mt and a slave clock 1st through the clock. Wiring l1, l2 respectively interconnect capacitance _C l1 _{to, C l2} is present.
FIG. 2 differs from FIG. 1 in that the wiring 11 for the master clock 1mt and the wiring l2 for the slave clock 1st are arranged adjacent to each other in parallel in the state in which the influence of crosstalk is taken into consideration. FIG. 6 is a circuit diagram for propagating a master clock 1mt and a slave clock 1st through DR2. Between the wiring l1, l2, l3, there wiring between the capacitance _{C C} is.

FIG. 3 is a diagram illustrating various crosstalk modes.
Crosstalk includes DC crosstalk caused by DC voltage, AC-1 crosstalk caused by AC voltage from one side, and AC-2 crosstalk caused by AC from both sides.
As described above, delays in signal lines due to crosstalk of wiring portions have become a problem due to recent miniaturization of LSIs. In order to solve this problem, it has been found that the signal propagation delay due to crosstalk increases by up to 46% if the design considering the operation timing and phase of the adjacent wiring is not performed. The outline is shown in FIG. For example, when a signal that changes in the master phase is reverted, if a signal on both sides changes from low to high when an arbitrary signal changes from high to low, the wiring pitch decreases in the recent miniaturization of VLSI The delay due to coupling due to the increase in the ratio of the capacitance between the lines due to has become a big problem.
FIG. 4 is a diagram illustrating the occurrence of crosstalk from an adjacent circuit electrically connected via a capacitance, and is an expression for determining the value of a coupling voltage during dynamic operation that leads to an increase in delay time. The model is shown.

FIGS. 5A to 5C show how the crosstalk receiver is affected by the signal transition state of the signal that receives the crosstalk (crosstalk receiver) and the change (change timing) of the adjacent crosstalk sources 1 and 2. It is the graph which illustrated the result of analysis.
As illustrated in FIGS. 3 to 5, the crosstalk is subjected to various forms of crosstalk due to various factors.
First, however, the simulation conditions and results for the relatively simple circuit illustrated in FIGS. 1 and 2 are described below.

Simulation conditions and results A model considering the crosstalk illustrated in FIG. 2 will be described. 90% of the wiring capacitance of the master clock 1mt and the slave clock 1st are wirings l1, and a wiring capacitance _{C l1, C l2} of l2, the cross between line l1-l2 mutually adjacent 45% one-sided The inter-wiring capacitance C _C causing the talk was added to the inter-wiring l1-l2.
Using this and the model when there is no crosstalk effect shown in FIG. 1, a clock in which the non-overlap period (isolation) of the master clock 1mt and the slave clock 1st is between 0.4 ns and 0.7 ns is used. The following simulation results were obtained.

FIG. 6 is a characteristic diagram of the rise time of the master clock 1mt. The horizontal axis indicates isolation, and the vertical axis indicates rise time. A broken line is a curve when it is assumed that there is no influence of the crosstalk shown in FIG. 1, and a solid line is a curve when there is an influence of the crosstalk shown in FIG.
FIG. 7 is a characteristic diagram of the fall time of the master clock 1mt. The horizontal axis indicates isolation, and the vertical axis indicates fall time. A broken line is a curve when it is assumed that there is no influence of the crosstalk shown in FIG. 1, and a solid line is a curve when there is an influence of the crosstalk shown in FIG.

  FIG. 8 is a characteristic diagram of the gate delay time as seen from the rising edge of the master clock 1mt. The horizontal axis indicates isolation, and the vertical axis indicates delay time. A broken line is a curve when it is assumed that there is no influence of the crosstalk shown in FIG. 1, and a solid line is a curve when there is an influence of the crosstalk shown in FIG.

6 to 8, the rise time was measured as the time for the waveform to change from 10% to 90% of the steady state value. The gate delay time was a time difference from the 50% level of the input to the 50% level of the output.
From these results, it can be said that the delay time increases due to the influence of crosstalk as the isolation decreases. The gate delay time when the isolation is 0.4 ns is increased by 0.08 ns compared to the case where there is no influence of crosstalk. The waveform at this time is shown in FIG.

FIG. 9 is a graph illustrating signal changes when the crosstalk between the wirings of the master clock 1mt and the slave clock 1st is considered and when the crosstalk is not considered.
A curve CV11R is a curve showing a rising characteristic when there is an influence of crosstalk of CV12F.
A curve CV21R is a curve showing a rising characteristic when there is no influence of crosstalk.
The output (curve CV11R) of the master clock 1mt when there is an influence of crosstalk rises after it has been lowered to -0.2V due to the influence of crosstalk. For this reason, the waveform is delayed as compared with the case where there is no influence of crosstalk. Next, when looking at the fall (curve CV12F), there is almost no difference at the 50% level as described above, but it takes 0.1n or more to drop to 0V after being greatly dragged from around 0.2V. Yes. This greatly affects the fall time.
Due to the influence of such crosstalk, a skew occurs between the master clock 1mt and the slave clock 1st.

Crosstalk Improvement Method FIG. 10 illustrates a circuit for preventing an increase in clock rise and fall delays due to the waveform distortion described above.
FIG. 10 is a crosstalk prevention circuit diagram of the first embodiment of the present invention.
In the crosstalk prevention circuit illustrated in FIG. 10, the master clock 1mt propagates to the wiring l1 to which the driver circuit DR1 is connected, and the slave clock 1st propagates to the wiring l2 to which the driver circuit DR2 is connected. This is a circuit for laying a wiring l3 to which a driver circuit DR3 is connected to l2 to propagate a test clock 1tt. Wiring l1, l2, l3, respectively there is wiring capacitance _{C l1, C l2, C l3} to, between lines l1, l3, l2 exist wiring inter capacitance _{C C1, C C2} Yes.

As described above, as the internal clock of the CPU, in addition to the master clock 1mt and the two-phase clock of the master clock 1mt and the slave clock 1st having a predetermined phase difference, the circuit operates and operates during the test when the master clock 1mt does not operate. There are provided three systems of scan test clocks 1tt used for performing the above test.
The three main clock wirings l1, l2, and l3 of the master clock 1mt, the slave clock 1st, and the test clock 1tt are usually wired (wired) almost in parallel with the entire CPU. Normally, as illustrated in FIG. 1 or FIG. 2, the wiring 11 for the master clock 1mt and the wiring 12 for the slave clock 1st are disposed adjacent to each other. However, in the present embodiment, the wiring 11 is provided. Wiring 12 for test clock 1tt is wired between 1 and 12 to also serve as a shield line, preventing crosstalk between master clock 1mt and slave clock 1st, thereby reducing signal delay and waveform distortion. Is intended to prevent.

In the circuit shown in FIG. 10, the wiring 13 for the test clock 1tt is wired between the wiring 11 for the master clock 1mt and the wiring 12 for the slave clock 1st, and serves as a shield line. There is an advantage that the area in the device does not increase.
Since the master clock 1mt and the slave clock 1st are active clocks when the semiconductor device is in operation, and the test clock 1tt is grounded during the normal operation of the semiconductor device and does not affect the normal operation, the shielding effect by the wiring l3 is large. .

However, when the wiring 13 for the test clock 1tt is adjacent to the wirings 11 and 12 for the master clock 1mt and the slave clock 1st and is wired between them, the test clock 1tt and the slave clock 1st that operate at the time of the test are arranged. Crosstalk occurs between the two.
In the present embodiment, it is preferable to suppress the current drive capability of the P-channel transistor constituting the driver circuit DR3 and increase the current drive capability of the N-channel transistor in order to increase the signal level stability of the wirings 12 and 13. .
Such a change in the P / N transistor width (the length is constant) of the driver circuit DR3 causes the test clock 1tt to slow down, but the test clock 1tt differs from the master clock 1mt and the slave clock 1st in the test operation. Because it is only used for, it does not cause a big problem even at low speed. By delaying the rising edge of the test clock 1tt and taking a greater isolation from the falling edge of the slave clock 1st than in the normal operation, skew due to crosstalk is prevented.

As for the crosstalk prevention circuit of FIG. 10, the result of performing a simulation by “SPICE” as in the circuits of FIGS. 1 and 2 will be described.
FIG. 11 is a characteristic diagram of the rise time of the master clock 1mt. The horizontal axis indicates isolation, and the vertical axis indicates rise time. A curve CV31 shows a characteristic result when there is an influence of crosstalk, a curve CV32 shows a characteristic result when there is no influence of crosstalk, and a curve CV33 arranges the test clock 1tt wiring l3 as a shield and a driver circuit. DR3 shows a characteristic result in a normal state, and a curve CV34 shows a case where the wiring 13 for the test clock 1tt is wired as a shield and the ratio of the P / N transistor width of the driver circuit DR3 is 1: 1. The characteristic results are shown.
FIG. 12 is a characteristic diagram of the fall time of the master clock 1mt. The horizontal axis indicates isolation, and the vertical axis indicates fall time. A curve CV41 shows a characteristic result when there is an influence of crosstalk, a curve CV42 shows a characteristic result when there is no influence of crosstalk, and a curve CV43 arranges the test clock 1tt wiring l3 as a shield and a driver circuit. DR3 shows a characteristic result in a normal state, and a curve CV44 shows a case where the wiring 13 for the test clock 1tt is wired as a shield and the ratio of the P / N transistor width of the driver circuit DR3 is 1: 1. The characteristic results are shown.

First Example A first example of the first embodiment will be described.
Table 1 exemplifies the ratio of the size of the output transistor and the P / N transistor width of the driver circuits DR1 to DR3 used in the actual design. Note that the length L of each transistor is 0.6 μm.

The P / N transistor width ratio of the output transistor of the driver circuit DR3 connected to the wiring l3 of the test clock 1tt was set to 1: 1.
Although the operation of the test clock 1tt is reduced, from the viewpoint of crosstalk, the ratio of the P / N transistor width of the output transistor of the driver circuit DR3 of the test clock 1tt wiring l3 is desirably 1: 1 or the vicinity thereof.

Second Example A second example of the above-described first embodiment will be described.
FIG. 13 is a circuit diagram as an embodiment of the crosstalk prevention circuit illustrated in FIG. This circuit example is a circuit example for examining the limit of the driver circuits (buffer circuits) DR1 to DR3, particularly the driver circuit DR3.
In FIG. 13, the conditions were set as follows.
(1) lines l1, l2, wiring capacitance _C l1 of _{l3, C l2, C l3:} 1.1pF, 1.1pF, 0.2pF
(2) Inter-wiring capacitance C _C1 , C _C2 : 0.9 pF, 0.9 pF
(3) Ratio of output transistor P / N transistor width of driver circuit DR1 (L is 0.6 μm)
80 μm / 40 μm = 2: 1
Ratio of P / N transistor width of output transistor of driver circuit DR2 (L is 0.6 μm)
80 μm / 40 μm = 2: 1
Ratio of P / N transistor width of output transistor of driver circuit DR3 (L is 0.6 μm)
80μm /? (Various)

  The simulation results of the circuit of FIG. 13 with various changes in the P / N transistor width ratio (L is 0.6 μm) of the output transistor of the driver circuit DR3 will be described below.

FIG. 14 is a signal waveform diagram when the ratio of the P / N transistor width of the output transistor of the driver circuit DR3 (L is 0.6 μm) is 80 μm / 2 μm = 40: 1, and only the slave clock 1st is applied to the wiring l2. is there.
FIG. 15 shows a signal waveform when the ratio of the P / N transistor width of the output transistor of the driver circuit DR3 is 80 μm / 2 μm = 40: 1, the master clock 1mt is applied to the wiring l1, and the slave clock 1st is applied to the wiring l2. FIG.
FIG. 16 shows a signal waveform when the ratio of the P / N transistor width of the output transistor of the driver circuit DR3 is 80 μm / 4 μm = 20: 1, the slave clock 1st is applied to the wiring 12, and the test clock 1tt is applied to the wiring 13. FIG.
When the ratio of the P / N transistor width of the output transistor of the driver circuit DR3 of the test clock 1tt wiring l3 is large, adjacent wirings, for example, l1 and l3 and l3 and l2 are affected by crosstalk.

FIG. 17 is a graph showing the influence of crosstalk on the master clock 1mt when the wiring 13 of the test clock 1tt is used as a shield in FIG. Isolation is 0.45 ns.
FIG. 18 is a graph showing the influence of crosstalk on the slave clock 1st when the wiring 13 of the test clock 1tt in FIG. 13 is used as a shield. Isolation is 0.45 ns.
FIG. 19 is a graph showing the influence of crosstalk on the wiring l3 of the test clock 1tt used as a shield in FIG. Isolation is 0.45 ns.

Second Embodiment A bus wiring circuit will be described as a second embodiment of the present invention.
As the first embodiment, the wirings l1, l2, and l3 of the master clock 1mt, the slave clock 1st, and the test clock 1tt have been described. However, the present invention is not limited to various fields such as a bus line crosstalk problem in a semiconductor device. It can also be applied effectively.
When buses are wired together, the value changes at the same timing, so if the signal transition between a bus line and the bus line running on both sides of the bus line changes in the opposite direction, the bus line running in the center will Influenced by crosstalk with the line. The details are described below.

FIG. 20 shows a bus wiring circuit when crosstalk is not considered, and FIG. 21 shows a bus wiring circuit when crosstalk is considered.
smt1 to smt3 mean buses whose values change with the master clock.
Assuming that the bus changes its value with a master clock, a capacity corresponding to about 10,000 μm of wiring is provided, and simulation by spice was performed in the same manner as the clock simulation. The results are shown in Table 2 and FIG.

FIG. 22 is a graph showing the influence of crosstalk on bus wiring.
The output of the central master clock smt2 rises after being lowered to around -0.2V due to the influence of crosstalk. Therefore, the gate delay time from the rise increases by 0.3 ns or more. Moreover, the fall becomes gentle and the fall time increases by about 0.4 ns.

Therefore, consider the circuit shown in FIG. FIG. 23 is a circuit diagram of a bus wiring circuit as a second embodiment of the present invention.
Symbols sst1 and sst2 are buses whose values change with a slave clock. The bus sst1 whose value changes with the slave clock is inserted between the bus smt1 and the bus smt2 whose value changes with the master clock, and the bus sst2 whose value changes with the slave clock and the bus smt2 and bus whose value changes with the master clock It is inserted between smt3. That is, as in the first embodiment, the influence of crosstalk is prevented by arranging the buses sst1 and sst2 whose values change with the slave clock as shields. As a result, the results shown in Table 3 and FIG. 24 were obtained.

FIG. 24 is a graph showing the influence of crosstalk on bus wiring.
From the results of Table 3 and FIG. 24, it can be seen that the rise time and the fall time remain slightly affected, but the gate delay time is completely different from the case where there is no crosstalk effect. That is, the crosstalk between the bus smt whose value changes with the master clock and the bus sst whose value changes with the slave clock does not affect the gate delay time, and the bus sst sufficiently improves the crosstalk problem as a shield. ing.

Third Example An example (third example) of the second embodiment will be described below.
FIG. 25 is a graph showing the influence on the bus smt2 whose value changes due to a change in the master clock when a bus whose value changes as a shield is used as a shield.
FIG. 26 is a graph showing the influence on the bus smt1 whose value changes with the change of the master clock when a bus whose value changes with the change of the slave clock is used as a shield.
FIG. 27 is a graph showing the influence on the bus whose value changes due to the change of the slave clock used as a shield.
From these results, the crosstalk between the bus smt whose value changes with the master clock and the bus sst whose value changes with the slave clock does not affect the gate delay time, and the bus sst is sufficiently crosstalked as a shield. The problem has been improved.

Area Consideration Table 4 shows that there is no area increase in the first embodiment and the second embodiment described above.

On the other hand, as a conventional countermeasure against crosstalk, there are (1) a method of expanding the space and (2) a method of separately providing a shield.
In the case of improvement by expanding the space between the wirings, the area of the 16-bit bus is increased by 243 μm, so it is impossible to actually make such wiring.
The addition of the shield wiring is very effective as described in the present invention. However, when a new shield wiring is arranged, the added area increases.
The present invention has the advantage that the crosstalk problem can be improved without considering such an area increase. That is, the present invention also has an advantage that the area is not increased.

As the crosstalk prevention circuit of the present invention, the clock supply circuit is illustrated as the first embodiment, and the bus wiring circuit is illustrated as the second embodiment. However, the present invention is not limited to the above-described embodiment. It can be applied to other similar fields.
Other crosstalk prevention circuits will be described below.

Third Embodiment A third embodiment of the crosstalk prevention circuit of the present invention will be described.
As described above, delays in signal lines due to crosstalk of wiring portions have become a problem due to recent miniaturization of LSIs. In order to solve this problem, if the design considering the operation timing and phase of the adjacent wiring is not performed, the signal propagation delay due to the crosstalk of the data path such as the DSP, including the gate part delay due to the glitch, is the maximum. It has been found that it increases by 46%. The outline is shown in FIG.
For example, when a signal that changes in the master phase is reverted, if a signal on both sides changes from low to high when an arbitrary signal changes from high to low, the wiring pitch decreases in the recent miniaturization of VLSI The delay due to coupling due to the increase in the ratio of the capacitance between the lines due to has become a big problem. FIG. 4 shows an equation and a model for obtaining a coupling voltage value that leads to an increase in delay time.

Conventionally, in metal wiring, in the era when lithography and metal grain size (about 1 μm) or less were not implemented, the addition of shield lines to prevent crosstalk was simply overhead and increased in area. .
However, in the recent 0.35 μm class semiconductor device manufacturing process using a wiring width of 0.5 μm or less, the peak current density of the metal is doubled.
By utilizing this property, it is possible to completely eliminate the problem of delay and function failure due to crosstalk while suppressing an increase in area.
The third embodiment of the present invention is based on this finding. That is, the third embodiment relates to a wiring technique related to a new design method that takes into consideration electromigration (EM) guidelines in recent miniaturized VLSIs in order to solve the problem of crosstalk.

Conventionally, as illustrated in FIG. 28, the power supply, the ground line, and the signal line are arranged and wired with a certain arbitrary width. This width was determined by analyzing the average current consumed by the connected module, the peak current, the RMS current, and the voltage drop in the resistance section. However, in practice, in most cases, the wiring width is determined by the peak current.
When the width of the metal wiring is 0.5 μm or less, since the grain size (grain boundary) of the metal is 1 μm, the resistance to electromigration is greatly improved. As a result, the peak current is allowed up to twice that of the prior art.
Therefore, when a wiring having a width of 0.5 μm or less is used for a power source, a ground, a signal line, etc., it is expected that the layout area will be superior.
As described above, the width of the metal wiring is determined by this peak current in most cases. Therefore, in the third embodiment, there is no area increase by using this property, and the operation phase of the wiring is taken into consideration. We propose a wiring method that can completely eliminate the crosstalk due to the shielding effect without having to make the
It is difficult to accurately understand the verification and impact of the design considering the operation phase of the wiring. Since the design proceeds based on the worst case assumption, the area increase due to excessive quality and the time required for the design and verification are greatly increased. Have spent on. If the embodiment of the present invention is adopted, since there is no influence of crosstalk, all of these problems can be solved and the best electrical condition can be realized, which is suitable for high-speed design.

FIG. 29 shows a signal wiring diagram for preventing crosstalk in consideration of electromigration as a third embodiment.
In FIG. 29, when the width of the metal wiring is 0.5 μm or less, the resistance to electromigration is doubled. Therefore, the wiring width of the power supply Vdd and the ground Gnd are compared with the example illustrated in FIG. Therefore, in the process having a width of 0.5 μm and a space of 0.5 μm, the space is offset, so there is no area increase.
However, since the influence on WR (Width Reduction Factor) is increased by dividing the wiring as illustrated in FIG. 29, for example, in the 0.35 μm process, 0.035 μm / side, the present invention is applied to 16 buses. When applied, the worst case is 16 × (0.035 × 2) = 1.125 μm, and 0.5 μm wiring is required, and an increase of about 2 lines is required. However, if the 0.5 μm shield and power ground are wired at 0.5 μm on both sides of the 16 buses, there are 17 wires, and when combined with 2 for WR reinforcement, the total of 19 × 0.5 μm = 9.5 μm Since these widths are only widths, these widths in actual use are required to be thicker, so the increase of the two does not increase in most cases.

  There are few obstacles to making such wiring using a routing tool, and the resistance to electromigration will be doubled by forming power, ground, and other wiring with a width smaller than the grain size of electromigration. Using the electrical properties, there is no increase in area, and it is possible to design without crosstalk function, verification by conventional high-speed static timing simulation, and excessive quality design assuming the worst case.

Fourth Embodiment A fourth embodiment of the present invention will be described.
FIG. 30 is an illustration of the fourth embodiment.
FIG. 30 shows an application example of the third embodiment, and in FIG. 29, an example in which the power supply line and the ground line are distributed in a width of 0.5 μm in consideration of electromigration in the plane direction is shown. FIG. 30 shows the first layer metal wiring and the third layer metal wiring as shown in FIG. 29 so that the crosstalk of the same layer metal wiring is reduced, and also in the height direction. An example in which crosstalk is reduced is shown.
In other words, the fourth embodiment shows an example of performing wiring in consideration of electromigration three-dimensionally.

  Although two forms of the crosstalk prevention circuit of the present invention have been described, the present invention is not limited to the above-described form, and can be applied to other fields similar to the above-described form.

l1, l2, l3 ... wiring
DR1 to DR3 ... Driver circuit

Claims (6)

A signal is applied when there is no signal applied to at least one of the two signal lines between at least two signal lines formed substantially in parallel, and a signal is applied to the two signal lines. A crosstalk prevention circuit in which a third signal line that is grounded when applied is arranged.   2. The crosstalk prevention circuit according to claim 1, wherein a driver circuit is connected to the third signal line, and the ratio of the current drive capability of the N-channel transistor and the P-channel transistor of the output transistor of the driver circuit is approximately 2: 1. . A first clock and a second clock having a predetermined phase difference from the first clock are applied to the first and second signal lines,
The crosstalk prevention circuit according to claim 1, wherein a signal applied during a test operation is applied to the third signal line. The first and second signal lines are signal lines whose voltage changes according to a first signal;
3. The crosstalk prevention circuit according to claim 1, wherein the third signal line is a signal line whose voltage changes according to a signal having a phase different from that of the first signal. A first power supply metal wiring and a second power supply metal wiring are provided in parallel at a predetermined distance on both sides of the metal signal wiring through which the pulse signal is propagated,
A crosstalk prevention circuit having a wiring, wherein the metal signal wiring and the first and second power supply metal wirings have widths that improve resistance to electromigration. The metal signal wiring surrounds the first power metal wiring and the second power metal wiring even in different layers of the metal signal wiring, the first power metal wiring, and the second power metal wiring. The crosstalk prevention circuit according to claim 5 provided.

Images