JP2003332415A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device wherein dummy protruding part regions are formed by a prescribed pattern in a trench element isolation region, and to provide a method for manufacturing the semiconductor device. <P>SOLUTION: The semiconductor device contains a silicon substrate 10 having the trench element isolation region 24, in which the plurality of dummy protruding part regions 32 are arranged. In the case that a first imaginary straight line L1 stretching in a direction crossing a row direction is imagined, the angle between the first imaginary straight line L1 and the row direction is 2-40°. In the case that a second imaginary straight line L2 stretching in a direction crossing a column direction is imagined, the angle between the second imaginary straight line L2 and the column direction is 2-40°. The dummy protruding part regions 32 are arranged so as to be positioned on the first and the second imaginary straight lines L1, L2. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having an element isolation region and a manufacturing method thereof.

[0002]

2. Description of the Related Art In recent years, with the miniaturization of semiconductor elements (for example, MOS transistors), it has become necessary to miniaturize element isolation regions. To achieve miniaturization of the element isolation region,
A trench element isolation technique is under study. The trench element isolation technology provides trenches between semiconductor elements on a substrate,
This is a technique for separating the semiconductor elements by filling the trench with an insulating material. Next, an example of this technique will be described.

FIG. 11 is a sectional view schematically showing a process of forming an element isolation region using a conventional trench element isolation technique.

As shown in FIG. 11A, the trench 11 is formed.
An insulating layer 121 is formed on the silicon substrate 110 having the structure 6. The effective convex region 130 of the silicon substrate 110
A polishing stopper layer 114 is formed on the above. Between the effective convex region 130 and the polishing stopper layer 114,
The pad layer 112 is interposed.

Next, as shown in FIG. 11B, the insulating layer 121 is planarized by using the polishing stopper layer 114 as a stopper. The planarization of the insulating layer 121 is performed by a chemical mechanical polishing method (hereinafter referred to as “CMP method”).

Then, as shown in FIG. 11C, by removing the polishing stopper layer 114, the trench insulating layer 120 is formed and the trench element isolation region 124 is completed.

However, as shown in FIG. 11B, due to the design of the device, the effective convex regions 13 formed densely with each other are formed.
In some cases, 0 and the isolated effective convex region 130 are formed. In such a case, for example, the following problem occurs.

When the insulating layer 121 is flattened by the CMP method, the phenomenon that the polishing stopper layer 114 in the isolated effective convex region 130 is extremely scraped occurs. On the other hand, the polishing stopper layers 114 in the densely formed effective convex regions 130 are formed in the isolated effective convex regions 130.
Compared to, it can't be scraped. This phenomenon is caused by the effective convex area 1
The pattern density of 30 results in different polishing rates. That is, the polishing pressure is concentrated on the polishing stopper layer 114 in the isolated effective convex region 130. As a result, the polishing rates in the isolated effective convex regions 130 are such that the effective convex regions 13 formed densely with each other.
It becomes faster than the polishing rate at 0. Therefore, the polishing of the polishing stopper layer 114 in the isolated effective convex region 130 is excessively advanced.

As described above, the isolated effective convex region 130 is isolated.
If the polishing stopper layer 114 is extremely shaved, problems such as variations in the thickness of the obtained trench insulating layer 120 will occur (see FIG. 11C). Also,
There is also a problem in that the polishing stopper layer 114 cannot perform its function. Further, when the isolated effective convex regions 130 are shaved, the polishing cloth is bent, and erosion occurs in the polishing stopper layers 114 in the effective convex regions 130 which are densely formed with each other. Erosion means the corner portion 1 of the polishing stopper layer 114.
This is a phenomenon in which 14a is scraped. Also, when the polishing cloth is bent, dishing (dishin
g) occurs. Dishing is a phenomenon in which the upper portion of the insulating layer 121 has a dish shape.

In order to solve the above problem, as shown in FIG. 12, the dummy convex region 132 is formed in the trench 116.
Techniques have been proposed for forming the. Dummy convex area 13
By forming 2, the polishing pressure is reduced to the dummy convex region 1
It is possible to prevent the polishing pressure from being concentrated on the isolated effective convex region 130 dispersed in 32. As a result, it is possible to prevent the polishing rate in the isolated effective convex region 130 from increasing. Therefore, by forming the dummy convex region 132, the isolated effective convex region 1 is formed.
It is possible to prevent the 30 from being scraped.

The technique for forming the dummy convex region 132 is as follows.
JP-A-9-107028, JP-A-9-18115
No. 9, JP-A-10-92921, JP-A No. 11
No. 26576, US Pat. No. 5,885,856 and US Pat. No. 5,902,752.

[0012]

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device in which a dummy convex region is formed in a predetermined pattern in a trench element isolation region, and a manufacturing method thereof.

[0013]

(Semiconductor Device) (A) A first semiconductor device of the present invention has a trench element isolation region, and a plurality of dummy convex regions are provided in the trench element isolation region. Assuming a first virtual straight line extending along a direction intersecting the row direction, an angle formed by the first virtual straight line and the row direction is 2 to 40 degrees, and the dummy convex region Are arranged so as to be located on the first virtual straight line.

Here, the "row direction" is one direction which is assumed in consideration of, for example, the active region, the gate region, the boundary region between the n-well and the p-well, and the prohibited area.

According to the first semiconductor device of the present invention, the dummy convex region is formed so as to be located on the first virtual straight line. The angle between the first virtual straight line and the row direction is 2 to 40 degrees. That is, the dummy convex regions adjacent to each other in the row direction on the same first virtual straight line are formed so as to be displaced from each other in the column direction. Therefore, even in the vicinity of the prohibited area extending in the row direction, it is easy to densely form the dummy convex regions. That is, even when a certain dummy convex region overlaps the prohibited area, another dummy convex region is reliably arranged in the vicinity of the prohibited area. As a result, when polishing the insulating layer filled in the trench, even in the vicinity of the prohibited area, the dummy convex region,
The polishing pressure can be surely dispersed.

Further, since the dummy convex regions can be surely arranged even in the vicinity of the prohibited area, the dummy convex regions can be surely arranged even in the region where the interval between the effective convex regions is narrow. it can.

In the first semiconductor device of the present invention, it is preferable that a predetermined space be provided between the first virtual straight lines. The spacing is preferably 1 to 16 μm.

It is preferable that the dummy convex region is arranged such that the center of the dummy convex region is located on the first virtual straight line.

(B) A second semiconductor device according to the present invention has a trench element isolation region, and a plurality of dummy convex regions are provided in the trench element isolation region, along a direction intersecting the column direction. Assuming a second imaginary straight line that extends in a horizontal direction, the angle formed by the second imaginary straight line and the column direction is
2 to 40 degrees, and the dummy convex region is arranged so as to be located on the second virtual straight line.

Here, the "column direction" is a direction orthogonal to the row direction, and includes, for example, an active region, a gate region,
This is one direction that is assumed in consideration of the boundary region between the n-well and the p-well, the prohibited area, and the like.

According to the second semiconductor device of the present invention, the dummy convex region is formed so as to be located on the second virtual straight line. The angle formed by the second virtual straight line and the column direction is 2 to 40 degrees. That is, the dummy convex regions that are adjacent to each other in the column direction on the same second virtual straight line are formed so as to be offset from each other in the row direction. Therefore, it is easy to densely form the dummy convex regions even near the prohibited area extending in the column direction. That is, even when a certain dummy convex region overlaps the prohibited area, another dummy convex region is reliably arranged in the vicinity of the prohibited area. As a result, when polishing the insulating layer filled in the trench, even in the vicinity of the prohibited area, the dummy convex region,
The polishing pressure can be surely dispersed.

Further, since the dummy convex regions can be surely arranged even in the vicinity of the prohibited area, the dummy convex regions can be surely arranged even in the region where the interval between the effective convex regions is narrow. it can.

Further, the above-described first semiconductor device of the present invention and the second semiconductor device of the present invention may be combined. According to the semiconductor device having the combination as described above, the dummy convex region can be formed more reliably in the vicinity of the prohibited area.

In the second semiconductor device of the present invention, it is preferable that a predetermined space be provided between the second virtual straight lines. The spacing is preferably 1 to 16 μm.

It is preferable that the dummy convex region is arranged such that the center of the dummy convex region is located on the second virtual straight line.

In the first and second semiconductor devices of the present invention, the dummy convex region can have at least one of the following features.

(1) In the plan view, the ratio of the area of the dummy convex region to the area of the trench element isolation region is 30 to 50%. This ratio is 30
By being in the range of up to 50%, the polishing pressure can be more effectively dispersed in the dummy convex region. Further, it is preferable that the ratio is about 40%.

(2) The plane shape of the dummy convex region is
This is a substantially rectangular shape. When the shape is substantially rectangular, the dummy convex region can be easily formed. The plane shape of the dummy convex region is preferably substantially square. Since the planar shape of the dummy convex region is substantially square, the dummy convex regions can be formed more densely. For example, even in the vicinity of a place where the prohibited areas are orthogonal to each other, the dummy convex region can be formed more reliably. Therefore, the dummy convex region can be formed more effectively even in the vicinity of the prohibited area formed with the complicated pattern (for example, the prohibited area around the gate area formed with the complicated pattern).

(3) When the planar shape of the dummy convex region is rectangular, the adjacent dummy convex regions arranged on the first virtual straight line or the second virtual straight line have a planar shape. , Is a mode having sides that partially face each other. It is preferable that the interval between the sides facing each other is shorter than one side of the dummy convex region. Alternatively, the distance between the sides facing each other is preferably 0.5 to 5
μm, more preferably about 1 μm.

(4) When the plane shape of the dummy convex region is rectangular, the length of one side of the dummy convex region is preferably 1 μm or more. When the length of one side of the dummy convex region is 1 μm or more, when a mask for generating the dummy convex region is created,
It is possible to suppress an increase in the amount of mask creation data.

The length of one side of the dummy convex region is preferably 10 μm or less, and more preferably 5 μm or less. When the length of one side of the dummy convex region is 5 μm or less, it is possible to prevent the insulating layer deposited on the dummy convex region from becoming thick when the insulating layer is embedded in the trench. It is particularly suitable when the insulating layer is embedded in the trench by using the high density plasma CVD method.

Particularly preferably, the length of one side of the dummy convex region is about 2 μm.

(5) In the trench element isolation region, it is preferable that a prohibited area is set, and a dummy convex region that partially overlaps the prohibited area is not formed. As a result, it is possible to reliably prevent pattern skipping and scratches when polishing the insulating layer. The width of the prohibited area is, for example, 0.5 to 20 μm.

(C) A third semiconductor device of the present invention has a trench element isolation region, a plurality of dummy convex regions are provided in the trench element isolation region, and the dummy convex region is a flat surface. The shape is almost square,
The interval between the dummy convex regions adjacent to each other in the row direction is approximately half the length of one side of the dummy convex region, and the dummy convex regions adjacent to each other in the row direction are displaced from each other in the column direction, The width of the dummy convex region displaced in the column direction is approximately half the length of one side of the dummy convex region.

Here, "row direction" and "column direction" are
This is the same as that described in the section of the first and second semiconductor devices of the present invention.

According to the third semiconductor device of the present invention, the dummy convex regions adjacent in the row direction are displaced from each other in the column direction. Therefore, the third semiconductor device of the present invention can achieve the same operational effect as the first semiconductor device of the present invention.

(D) A fourth semiconductor device of the present invention has a trench element isolation region, a plurality of dummy convex regions are provided in the trench element isolation region, and the dummy convex region is flat. The shape is almost square,
The interval between the dummy convex regions adjacent to each other in the column direction is approximately half the length of one side of the dummy convex regions, and the dummy convex regions adjacent to each other in the column direction are displaced from each other in the row direction, The width of the dummy convex portion area shifted in the row direction is approximately half the length of one side of the dummy convex portion area.

Here, "row direction" and "column direction" are
This is the same as that described in the section of the first and second semiconductor devices of the present invention.

According to the fourth semiconductor device of the present invention, the dummy convex regions adjacent in the column direction are displaced from each other in the row direction. Therefore, the fourth semiconductor device of the present invention can achieve the same operational effect as the second semiconductor device of the present invention.

Further, the above-described third semiconductor device of the present invention and the fourth semiconductor device of the present invention may be combined. According to the semiconductor device having the combination as described above, the dummy convex region can be formed more reliably in the vicinity of the prohibited area.

In the third and fourth semiconductor devices of the present invention, it is preferable that one side of the dummy convex region has a length of about 2 μm.

(Method for Manufacturing Semiconductor Device) (A) A first method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device having a trench element isolation region, comprising: (a) a silicon substrate A step of forming a polishing stopper layer having a predetermined pattern, (b) forming a trench in the silicon substrate using at least the polishing stopper layer as a mask, and (c) the silicon substrate so as to fill the trench. A step of forming an insulating layer thereon, and (d) a step of polishing the insulating layer using the polishing stopper layer as a stopper. In the step (b), a plurality of dummy protrusions are formed in the trench. Assuming a first virtual straight line in which a partial region is formed and extends along a direction intersecting the row direction, the angle formed by the first virtual straight line and the row direction is 2 to 40 degrees. Yes, the dummy convex region is arranged so as to be located on the first virtual straight line.

According to the first semiconductor device manufacturing method of the present invention, the dummy convex region is formed in the step (b). This dummy convex region is formed in the same pattern as the pattern described in the section of the first semiconductor device of the present invention. Therefore, in the step (b),
The dummy convex region is surely formed in the vicinity of the prohibited area. As a result, in step (d),
When polishing the insulating layer, the polishing pressure can be reliably dispersed in the dummy convex region. Therefore, the thickness of the insulating layer obtained after polishing can be made uniform.

(B) A second method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device having a trench element isolation region, wherein (a) a predetermined pattern is formed on a silicon substrate. A step of forming a polishing stopper layer,
(B) forming a trench in the silicon substrate using at least the polishing stopper layer as a mask, (c) forming an insulating layer on the silicon substrate so as to fill the trench, and (d) Polishing the insulating layer using the polishing stopper layer as a stopper, and in the step (b), a plurality of dummy convex regions are formed in the trench, and the dummy convex regions are formed along a direction intersecting the column direction. Assuming a second virtual straight line that extends,
The angle formed by the virtual straight line and the column direction is 2 to 40 degrees, and the dummy convex region is arranged so as to be located on the second virtual straight line.

According to the second method of manufacturing the semiconductor device of the present invention, the dummy convex region is formed in the same pattern as the pattern described in the section of the second semiconductor device of the present invention. There is. Therefore, according to the present invention, it is possible to obtain the same effects as the first semiconductor device manufacturing method of the present invention.

A first semiconductor device manufacturing method of the present invention;
You may combine with the manufacturing method of the 2nd semiconductor device of this invention.

That is, in the first semiconductor device manufacturing method of the present invention, further assuming a second virtual straight line extending along a direction intersecting the column direction, the second virtual straight line and the column The angle formed with the direction is 2 to 40 degrees, and the dummy convex region may be arranged so as to be located on the second virtual straight line.

In the case of such combination, the dummy convex region can be formed more reliably in the vicinity of the prohibited area. Therefore, the thickness of the insulating layer obtained after polishing can be made more uniform.

The items described in the section of the semiconductor device can be applied to the first and second semiconductor device manufacturing methods of the present invention as the configuration of the first and second virtual straight lines. Further, the dummy convex region can take the same forms (1) to (5) described in the section of the semiconductor device.

(C) A third method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device having a trench element isolation region, wherein (a) a predetermined pattern is formed on a silicon substrate. A step of forming a polishing stopper layer,
(B) forming a trench in the silicon substrate using at least the polishing stopper layer as a mask, (c) forming an insulating layer on the silicon substrate so as to fill the trench, and (d) Polishing the insulating layer using the polishing stopper layer as a stopper, and in the step (b), a plurality of dummy convex regions are formed in the trench, and the dummy convex regions are
The space between the dummy convex regions that are substantially square in the plane shape and that are adjacent to each other in the row direction is approximately half the length of one side of the dummy convex regions, and the dummy convex regions that are adjacent to each other in the row direction. The regions are displaced from each other in the column direction, and the width of the dummy protrusion regions displaced in the column direction is approximately half the length of one side of the dummy protrusion regions.

According to the third method of manufacturing a semiconductor device of the present invention, the dummy convex region is formed in the same pattern as the pattern described in the section of the third semiconductor device of the present invention. There is. Therefore, according to the present invention, it is possible to obtain the same effects as the first semiconductor device manufacturing method of the present invention.

(D) A fourth method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device having a trench element isolation region, wherein (a) polishing having a predetermined pattern on a silicon substrate. A step of forming a stopper layer, (b)
Forming a trench in the silicon substrate using at least the polishing stopper layer as a mask; (c) forming an insulating layer on the silicon substrate so as to fill the trench; and (d) the polishing stopper. Polishing the insulating layer using a layer as a stopper, and in the step (b), a plurality of dummy convex regions are formed in the trench, and the dummy convex regions have a substantially planar shape. The interval between the dummy convex regions that are square and adjacent in the column direction is approximately half the length of one side of the dummy convex region, and the dummy convex regions that are adjacent in the column direction are arranged in rows. The width of the dummy convex region displaced in the row direction is approximately half the length of one side of the dummy convex region.

According to the fourth method of manufacturing a semiconductor device of the present invention, the dummy convex region is formed in the same pattern as the pattern described in the section of the fourth semiconductor device of the present invention. There is. Therefore, according to the present invention, it is possible to obtain the same effects as the first semiconductor device manufacturing method of the present invention.

A third method for manufacturing a semiconductor device of the present invention;
You may combine with the 4th semiconductor device manufacturing method of this invention.

With such a combination, the dummy convex region can be formed more reliably in the vicinity of the prohibited area. Therefore, the thickness of the insulating layer obtained after polishing can be made more uniform.

[0056]

BEST MODE FOR CARRYING OUT THE INVENTION Preferred embodiments of the present invention will be described below with reference to the drawings.

[Semiconductor Device] (Device Structure) The semiconductor device according to the present embodiment will be described below. The semiconductor device according to the present embodiment has a trench element isolation region in a silicon substrate. A feature of the semiconductor device according to the present embodiment is the configuration of the silicon substrate having the trench element isolation region. The configuration of the silicon substrate having the trench element isolation region will be specifically described below. FIG. 1 is a plan view of a silicon substrate having a trench isolation region. Figure 2
It is sectional drawing which shows typically the cross section along the AA line in FIG.

The silicon substrate 10 is provided with an effective convex region 30 having a predetermined pattern. The effective convex region 30 serves as an element forming region such as a MOS transistor. The effective convex region 30 is arranged regularly or randomly. The effective convex regions 30 are formed densely with each other in terms of device design.
And an isolated effective convex region 30. A wide element isolation region 24 is formed between the effective convex region 30 and the isolated effective convex region 30 which are densely formed with each other.

A dummy convex region 32 is formed in the wide trench isolation region 24. Dummy convex area 3
2 are formed so as to be aligned along a direction intersecting the row direction. Further, the dummy convex regions 32 are formed so as to be aligned along the direction intersecting the column direction. Width W1 of the trench element isolation region 24 in which the dummy convex region 32 is formed (interval between effective convex regions) W1
0 is not particularly limited.

A forbidden area, which will be described in detail later, is set around the effective convex area 30. Here, the prohibited area means an area where the dummy convex area 32 is not generated. That is, the dummy convex region 32 is formed so as not to overlap the prohibited area. More specifically,
The dummy convex area that entirely or partially overlaps the prohibited area is completely excluded. The advantage of completely eliminating the dummy convex region that partially overlaps the prohibited area will be described in detail in the section of action and effect described later.

The layout pattern of the dummy convex regions 32 will be described below with reference to FIG. FIG. 3 is a diagram for explaining an arrangement pattern of the dummy convex region 32.

The dummy convex region 32 has a first imaginary straight line L.
It is formed so that it may be located above 1. The dummy convex region 32 is formed so as to be located on the second virtual straight line L2. The dummy convex region 32 is formed, for example, such that the center of the dummy convex region 32 is located on the first virtual straight line L1. In addition, the dummy convex region 3
2 is formed, for example, such that the center of the dummy convex region 32 is located on the second virtual straight line L2.

The first virtual straight line L1 intersects the row direction. The angle θ1 formed by the first virtual straight line L1 and the row direction is
It is 2 to 40 degrees, preferably 15 to 25 degrees, and more preferably about 20 degrees. Here, "row direction" means
For example, active region, gate region, n-well and p
This is one direction that is assumed in consideration of the boundary region with the well, the well functioning as a resistance, the prohibited area, and the like.

The second virtual straight line L2 intersects the column direction. The angle θ2 formed by the second virtual straight line L2 and the column direction is
It is 2 to 40 degrees, preferably 15 to 25 degrees, and more preferably about 20 degrees. Here, "column direction" means
The direction is orthogonal to the row direction, and is one direction that is assumed in consideration of, for example, the active region, the gate region, the boundary region between the n-well and the p-well, the well functioning as a resistance, and the prohibited area.

A plurality of first virtual straight lines L1 are assumed,
Moreover, it is assumed at a predetermined pitch. First virtual straight line L1
The interval is not particularly limited and is, for example, 1 to 16 μm, preferably 2 to 5 μm. Second virtual straight line L
The number 2 is assumed to be plural and is assumed to be at a predetermined pitch. The interval between the second virtual straight lines L2 is not particularly limited,
For example, it is 1 to 16 μm, preferably 2 to 5 μm.

Adjacent dummy convex regions 32 arranged on the same first virtual straight line L1 are formed so as to be displaced from each other in the column direction. The width Y10 of the dummy convex regions 32 shifted in the column direction is preferably 0.5 to 5 μm, more preferably 0.5 to 2 μm, and particularly preferably about 1 μm.

The dummy convex regions 32 adjacent to each other in the column direction, which are arranged on the same second virtual straight line L2, are formed so as to be offset from each other in the row direction. The width X10 of the dummy convex region 32 which is displaced in the row direction is preferably 0.5 to 5 μm,
More preferably 0.5 to 2 μm, particularly preferably about 1 μm.
m.

The ratio of the area of the dummy convex regions 32 to the unit area of the trench element isolation region 24 in the plan view is not particularly limited and is preferably 30 to 50%, more preferably about 40%. Specifically, the ratio of the area of the dummy convex region to the entire area of the unit unit is
It is preferably 30 to 50%, more preferably about 40%.

Here, the "unit unit" means the smallest unit that can form the entire pattern by repeating the unit vertically and horizontally. In particular,
In FIG. 3, the “unit unit” is a square ABCD.
The area surrounded by.

The plane shape of the dummy convex region 32 is not particularly limited, and examples thereof include a polygon and a circle. The planar shape of the dummy convex region 32 is preferably polygonal, more preferably rectangular, and particularly preferably square. When the dummy convex region 32 has a square planar shape, the dummy convex regions 32 can be formed more densely in the trench element isolation region 24. For example,
Even in the vicinity of a place where the prohibited areas intersect at right angles, the dummy convex region 32 can be formed more reliably. Therefore, the dummy convex region 32 can be formed more effectively even in the vicinity of the prohibited area formed with the complicated pattern (for example, the prohibited area around the gate area formed with the complicated pattern). .

When the planar shape of the dummy convex region 32 is a square, the length T10 of one side is not particularly limited, but is, for example, 1 to 10 μm, preferably 1 to 5 μm.
m, more preferably about 2 μm. When the length T10 of one side of the dummy convex region is 1 μm or more, it is possible to prevent the amount of mask creation data from significantly increasing when creating a mask for generating the dummy convex region 32. . Since the length T10 of one side of the dummy convex region 32 is 5 μm or less, the thickness of the insulating layer deposited on the dummy convex region 32 when the insulating layer 21 is embedded in the trench 16, which will be described later. However, it can be made substantially equal to the thickness of the insulating layer deposited on the effective convex region (for example, the circuit region) 30. Therefore, when the length T10 of one side of the dummy convex region is 5 μm or less, the insulating layer 21 remains on the dummy convex region 32 after the polishing step of the insulating layer 21 described later. It can be suppressed more reliably. Further, the length T10 of one side of the dummy convex region is 5 μm or less, which is particularly useful when the trench 16 is filled with the insulating layer 21 by the high-density plasma CVD method.

When the dummy convex region 32 has a square planar shape, adjacent dummy convex regions 32 arranged on the same first virtual straight line L1 have sides S1 and S2 which are partially opposed to each other. Have. The distance G10 between the facing sides S1 and S2 is not particularly limited, but is preferably 0.5 to 5 μm, and more preferably about 1 μm. Alternatively, the interval G10 is the length T of one side of the dummy convex region 32.
The length is preferably set to be shorter than 10, and more preferably approximately half of the length T10 of one side of the dummy convex region 32.

When the dummy convex region 32 has a square planar shape, the adjacent dummy convex regions 32 arranged on the same second virtual straight line L2 have sides S3 and S4 which are partially opposed to each other. Have. The distance G20 between the facing sides S3 and S4 is not particularly limited, but is preferably 0.5 to 5 μm, and more preferably about 1 μm. Alternatively, the interval G20 is the length T of one side of the dummy convex region 32.
The length is preferably set to be shorter than 10, and more preferably approximately half of the length T10 of one side of the dummy convex region 32.

When the dummy convex region 32 has a square planar shape, the width Y10, which is adjacent in the row direction and is displaced in the column direction, of the dummy convex regions 32 is equal to the length of one side of the dummy convex region 32. , Preferably about half. Further, the width X of the dummy convex regions 32 that are adjacent to each other in the column direction is shifted in the row direction.
It is preferable that 10 is substantially half the length of one side of the dummy convex region.

(Function and Effect) By forming the dummy convex region 32 with the above structure, for example, the following function and effect can be obtained. This function and effect will be described with reference to FIG. FIG. 4 is a diagram for explaining the function and effect of the arrangement pattern of the dummy convex regions 32.

(1) Consider a case where there is a prohibited area extending in the row direction in the trench element isolation region and around the effective convex region as shown in FIG. In this case, it is conceivable to form a grid-shaped dummy convex region in parallel with the prohibited area. If the dummy convex areas are formed in a grid pattern and one of the dummy convex areas overlaps the prohibited area, all the other dummy convex areas in the same row as the dummy convex area become the prohibited area. It will hang. Therefore, it is necessary to control the position of the dummy convex region in order to form the dummy convex region in the vicinity of the prohibited area so that the dummy convex region does not overlap the prohibited area. This control is technically difficult because it causes an increase in mask creation data, for example. On the other hand, if the dummy convex regions cannot be formed in the vicinity of the prohibited area, the density of the dummy convex regions formed in the trench isolation region in the vicinity of the prohibited area will be insufficient.

However, in the present embodiment, FIG.
As shown in (b), the dummy convex region 32 is formed so as to be located on the first virtual straight line L1 extending in the direction intersecting the row direction. That is, the adjacent dummy convex regions 32 on the same first virtual straight line L1 are formed so as to be offset from each other in the column direction. Therefore, even if a certain dummy convex region falls on the forbidden area on the same virtual straight line, the other adjacent dummy convex regions 32 are
Can be placed so that it does not hang over the prohibited area. as a result,
The dummy convex region 32 can be reliably formed in the vicinity of the prohibited area without controlling the formation position of the dummy convex region 32.

Further, in the present embodiment, the dummy convex region 32 is further formed so as to be located on the second virtual straight line L2 extending in the direction intersecting the column direction. That is, the adjacent dummy convex regions 32 on the same second virtual straight line L2 are formed so as to be offset from each other in the row direction. Therefore, for the same reason as when the dummy convex region 32 is on the first virtual straight line L1, the dummy convex region 32 can be reliably formed in the vicinity of the prohibited area extending in the column direction.

(2) In the present embodiment, the dummy convex region that partially overlaps the prohibited area is completely excluded.
Therefore, for example, the following operational effects are exhibited.

In FIG. 4 (b), of the dummy convex regions that partially overlap the prohibited area, some regions (hatched areas) that do not overlap the prohibited area (hereinafter referred to as "remaining dummy convex regions"). Is likely to occur. This remaining dummy convex portion area has a planar shape in which a part of the original dummy convex portion area in planar shape is missing. That is, the planar shape of the remaining dummy convex region is smaller than the original planar shape of the dummy convex region. When the dimension of the plane shape of the remaining dummy convex portion region becomes extremely small (for example, smaller than the resolution limit or the design rule), the following problems may occur, for example.

(A) It becomes difficult to form a resist layer that defines the residual dummy convex regions, and pattern skipping occurs in the residual dummy convex regions. (B) Even if the resist layer for forming the remaining dummy convex region can be formed, the resist layer collapses, and the collapsed resist layer becomes dust during the etching for forming the trench, which causes the etching. Adversely affect. (C) Since the convex portion of the residual dummy convex portion area becomes thin, the convex portion of the residual dummy convex portion area is broken during the substrate cleaning step after the etching step for forming the convex portion area, and becomes a surface foreign matter. . (D) If the surface foreign matter is taken into the insulating layer, scratches may occur during polishing of the insulating layer.

However, in the present embodiment, the residual dummy convex region is not formed. Therefore, it is possible to reliably prevent the above problems from occurring.

(Prohibited Area) Next, the prohibited area will be specifically described. FIG. 5 is a diagram for explaining the prohibited area,
FIG. 6 is a plan view of a silicon substrate having a dummy convex region.
In FIG. 5, the prohibited area is indicated by diagonal lines. The prohibited area is set in the following area, for example.

(1) Firstly, the area around the actual active area A1. If no prohibited area is provided in this area, the dummy convex area 32 may be formed in contact with the actual active area A1. In this case, for example, the actual active area A1 and the dummy convex area 32 are short-circuited, causing a problem that an unnecessary area becomes an active area. The width W1 of the prohibited area is not particularly limited as long as this problem can be suppressed, and is, for example, 0.5 to 20 μm, preferably 1 to 5 μm. The dummy convex region 32 is preferably formed up to the vicinity of the actual active region A1 to the extent that it does not cover the prohibited area.

(2) Secondly, the area around the area A2 where the gate area is to be formed. If the prohibited area is not provided in this area, the dummy convex area 32 and the gate area may be formed in an overlapping state. in this case,
An active region is formed below the gate region in a region other than the required region, and active capacitive coupling is formed with the gate, which causes a problem such as deterioration of original transistor characteristics. The width W2 of the prohibited area is not particularly limited as long as this problem can be suppressed, and is, for example, 0.5 to 20 μm, preferably 1 to 5 μm.

(3) Third, it is a region around the boundary region A3 between the n-well and the p-well. If the prohibited area is not provided in this region, the dummy convex region 32 may be formed in the boundary region A3 between the n well and the p well. In this case, the n-well and the p-well come into contact with each other through the dummy convex region 32, causing a problem such as current leakage. The width W3 of the prohibited area is not particularly limited as long as this problem can be suppressed, and is, for example, 0.5.
˜20 μm, preferably 1 to 5 μm. In addition, it is preferable that the dummy convex region 32 is formed up to the vicinity of the boundary region A3 between the n-well and the p-well so as not to cover the prohibited area.

(4) Fourth, it is a region around the well region A4 which functions as a resistor. If the prohibited area is not provided in this region, the dummy convex region 32 is formed on the well region A4, so that a problem such as a change in the resistance of the well region A4 occurs. The width W4 of the prohibited area is not particularly limited as long as this problem can be suppressed, and is, for example, 0.5 to 20 μm, preferably 1 to 5 μm. It is preferable that the dummy convex region 32 is formed up to the vicinity of the well region A4 that functions as a resistance so that the dummy convex region 32 does not cover the prohibited area.

[Manufacturing Method of Semiconductor Device] (Manufacturing Process) Next, a manufacturing process of the semiconductor device according to the embodiment will be described. Specifically, a method of forming the trench element isolation region will be described. 6 to 8
FIG. 7A is a cross-sectional view schematically showing the manufacturing process of the semiconductor device according to the present embodiment.

(1) First, description will be made with reference to FIG. The pad layer 12 is formed on the silicon substrate 10. Examples of the material of the pad layer 12 include silicon oxide and silicon oxynitride. When the pad layer 12 is made of silicon oxide, a thermal oxidation method,
It can be formed by a CVD method or the like. Pad layer 1
When 2 is made of silicon oxynitride, it can be formed by a CVD method or the like. The film thickness of the pad layer 12 is
For example, it is 5 to 20 nm.

Next, the polishing stopper layer 14 is formed on the pad layer 12. The polishing stopper layer 14 may have a single layer structure or a multilayer structure. Examples of the single layer structure include a silicon nitride layer, a polycrystalline silicon layer, and an amorphous silicon layer.
The multilayer structure has at least two selected from a silicon nitride layer, a polycrystalline silicon layer, and an amorphous silicon layer.
There may be mentioned a multilayer structure composed of seeds. As a method of forming the polishing stopper layer 14, a known method such as a CVD method can be used. Polishing stopper layer 1
No. 4 has a film thickness sufficient to function as a stopper in the subsequent CMP, for example, a film thickness of 50 to 250 nm.

Next, a resist layer R1 having a predetermined pattern is formed on the polishing stopper layer 14. Specifically, the resist layer R1 is patterned so that the pattern of the convex regions 30 and 32 described in the section of the device structure is formed (see FIG. 1). More specifically, the resist layer R1 includes the effective convex region 30 and the dummy convex region 3.
It is patterned so that the resist layer R1 above the formation region of 2 remains.

(2) Next, as shown in FIG. 6B, the polishing stopper layer 14 and the pad layer 12 are etched using the resist layer R1 as a mask. This etching is
For example, dry etching is performed.

(3) Next, the resist layer R1 is removed.
The resist layer R1 is removed by, for example, ashing. Next, as shown in FIG. 6C, the silicon substrate 10 is etched using the polishing stopper layer 14 as a mask to form a trench 16. By forming the trench 16, the effective convex portion region 30 and the dummy effective convex portion region 32 are formed. The depth of the trench 16 varies depending on the device design, but is, for example, 300 to 500 nm. The etching of the silicon substrate 10 can be performed by dry etching. These convex areas 30, 3
The cross-sectional shape of 2 is preferably tapered. Since the convex regions 30 and 32 have a tapered cross-sectional shape, it becomes easy to embed the insulating layer 21 in the trench 16, which will be described later. The taper angle α of the cross-sectional shape of the convex regions 30 and 32 is preferably 70 degrees or more and less than 90 degrees.

Next, although not shown, the pad layer 12 interposed between the silicon substrate 10 and the polishing stopper layer 14.
Etch the edges of.

(4) Next, as shown in FIG. 7A, the silicon substrate 10 in the trench 16 is formed by thermal oxidation.
The exposed surface is oxidized to form a trench oxide film 18. In addition, since the end portions of the pad layer 12 are etched by this thermal oxidation, the shoulder portions 10a of the convex regions 30 and 32 are oxidized and are rounded. The thickness of the trench oxide film 18 is, for example, 10 to 70 nm, preferably 10 to 50 nm.

(5) Next, as shown in FIG. 7B, the insulating layer 21 is deposited on the entire surface so as to fill the trench 16. Examples of the material of the insulating layer 21 include silicon oxide. The insulating layer 21 has a film thickness that fills the trench 16 and is at least the polishing stopper layer 14
The film thickness is not particularly limited as long as it covers. Insulation layer 2
The film thickness of 1 is, for example, 500 to 800 nm. As a method of depositing the insulating layer 21, for example, high density plasma C
VD (HDP-CVD) method, thermal CVD method, TEOS plasma CVD method, etc. can be mentioned.

(6) Next, as shown in FIG. 7C, the insulating layer 21 is flattened by the CMP method. This flattening is
This is performed until the polishing stopper layer 14 is exposed. That is, the insulating layer 21 is planarized by using the polishing stopper layer 14 as a stopper. In the present embodiment, the large element isolation region 24
In, the dummy convex region 32 is formed. That is, the dummy convex region 32 is formed between the effective convex region 24 and the isolated effective convex region 24 which are densely formed with each other. Then, the dummy convex region 32
Are formed in the arrangement pattern described in the section of the semiconductor device. Therefore, the dummy convex region 32 is reliably formed in the vicinity of the prohibited area in the wide element isolation region 24. As a result, during this polishing, the polishing pressure can be reliably dispersed in the dummy convex regions 32 by the amount that the dummy convex regions 32 are reliably formed in the large element isolation region 24. Therefore, it is possible to further suppress the polishing pressure from being concentrated on the isolated effective convex region 30. Therefore, it is possible to further prevent the polishing stopper layer 14 in the isolated effective convex region 30 from being scraped.

(7) Next, as shown in FIG. 8, the polishing stopper layer 14 is removed by using, for example, a hot phosphoric acid solution.
Next, as shown in FIG. 2, the pad layer 12 and the insulating layer 21
And isotropically etched with hydrofluoric acid. Thus, the trench insulating layer 20 is formed in the trench 16 and the trench element isolation region 24 is completed.

(Operation and Effect) The operation and effect of the semiconductor device manufacturing method according to the present embodiment will be described below.

In the method of manufacturing the semiconductor device according to the present embodiment, the dummy convex region 32 is formed in the same pattern as the dummy convex region 32 described in the section of the semiconductor device. Therefore, the dummy convex region 32 is reliably formed in the vicinity of the prohibited area. As a result, as described in step (6), it is possible to further prevent the polishing stopper layer 14 in the isolated effective convex region 30 from being scraped. Therefore, the film thickness of the trench insulating layer 20 can be made more uniform.

[Experimental Example] An experiment was conducted to investigate how the dummy convex regions are formed between the effective convex regions due to the difference in the arrangement pattern of the dummy convex regions.

(Conditions of the Embodiment) The conditions of the embodiment will be described below.

(1) In the embodiment, the layout pattern of the dummy convex regions is according to the following rules. (A) The angle formed by the first virtual straight line and the row direction is about 1
It was set to 8.4 degrees. (B) The distance between the first virtual straight lines was set to about 3.2 μm. (C) The angle formed by the second virtual straight line and the column direction is about 1
It was set to 8.4 degrees. (D) The distance between the second virtual straight lines was set to about 3.2 μm. (E) The ratio of the area of the dummy convex region per unit area of the element isolation region was set to 40%. (F) The planar shape of the dummy convex region is a square. (G) One side of the plane shape of the dummy convex region is 2 μm. (H) In the adjacent dummy convex regions arranged on the same first virtual straight line, the interval between the opposing sides is 1
μm. (I) In the adjacent dummy convex regions arranged on the same second virtual straight line, the interval between the opposing sides is 1
μm. (J) In the adjacent dummy convex regions arranged on the same first virtual straight line, the widths shifted from each other in the column direction are:
It was 1 μm. (K) In the adjacent dummy convex regions arranged on the same second virtual straight line, the widths shifted in the row direction are:
It was 1 μm. (L) The dummy convex region is formed such that its center is located on the first virtual straight line. (M) The dummy convex region is formed so that its center is located on the second virtual straight line. (N) The dummy convex region (including the dummy convex region in contact with the prohibited area) that entirely or partially overlaps the prohibited area is
Has been eliminated.

(2) The prohibited area is set in the area around the effective convex area. The width of the prohibited area was 1 μm.

(3) A region A1 having a space between the effective convex regions of 10 μm and a region B1 having a space between the effective convex regions of 6 μm are set.

(Conditions for Comparative Example) The conditions for the comparative example will be described below.

(1) In the comparative example, the dummy convex regions are arranged in a grid pattern. Specifically, the layout pattern of the dummy convex regions is according to the following rules. (A) The distance between the adjacent dummy convex regions in the row direction is 1
μm. (B) The distance between the adjacent dummy convex regions in the column direction is 1
μm. (C) The planar shape of the dummy convex region is square. (D) One side of the dummy convex region is 2 μm. (E) The dummy convex area (including the dummy convex area in contact with the prohibited area) which entirely or partially overlaps the prohibited area is
Has been eliminated.

(2) The prohibited area is set in the area around the effective convex area. The width of the prohibited area was 1 μm.

(3) As the pattern of the effective convex area, the same pattern as that of the embodiment was used. The area A1 of the embodiment
The area corresponding to the area A2 is represented as A2, and the area corresponding to the area B1 in the embodiment is represented as B2.

(Results) The results are shown in FIGS. 9 and 10. FIG. 9 is a plan view of a part of the wafer according to the example. FIG. 10 is a plan view of a part of the wafer according to the comparative example. It should be noted that the squares shown by solid lines show the dummy convex regions actually formed, and the squares shown by imaginary lines show the fictitious dummy convex regions that have been excluded.

In the comparative example, in the area A2, 1
Only dummy convex regions for the rows are formed. That is, the dummy convex region is not formed in the vicinity of the prohibited area. On the other hand, in the embodiment, the area A
In No. 1, the dummy convex region is surely formed near the prohibited area.

Further, in the embodiment, the dummy convex region is formed in the region (region B1) where the interval between the effective convex regions is narrow. On the other hand, in the comparative example, the dummy convex region is not formed in the region (region B2) where the interval between the effective convex regions is narrow.

From the above, according to the example, it is understood that the dummy convex region can be formed in the element isolation region more reliably than in the comparative example.

[Modification] The present invention is not limited to the above-mentioned embodiment, and various modifications can be made within the scope of the present invention.

(1) In the above-described embodiment, the dummy convex region 32 is such that the center of the dummy convex region 32 is the first
Was formed so as to be located on the virtual straight line L1. However, the dummy convex area 32 is
Another portion other than the center of 2 may be formed so as to be located on the first virtual straight line L1. That is,
It suffices if the dummy convex region 32 is on the first virtual straight line L1.

(2) In the above-described embodiment, the dummy convex region 32 has the center of the dummy convex region 32 at the second position.
It was formed so as to be located on the virtual straight line L2. However, the dummy convex area 32 is
Another portion other than the center of 2 may be formed so as to be located on the second virtual straight line L2. That is,
It suffices if the dummy convex region 32 is on the second virtual straight line L2.

[Brief description of drawings]

FIG. 1 is a plan view of a silicon substrate having a trench isolation region.

FIG. 2 is a cross-sectional view schematically showing a cross section taken along the line AA in FIG.

FIG. 3 is a diagram for explaining an arrangement pattern of a dummy convex region.

FIG. 4 is a diagram for explaining the function and effect of the arrangement pattern of the dummy convex regions.

FIG. 5 is a view for explaining a prohibited area, and is a plan view of a silicon substrate having a dummy convex region.

FIG. 6 is a cross-sectional view schematically showing the manufacturing process of the semiconductor device according to the embodiment.

FIG. 7 is a cross-sectional view schematically showing the manufacturing process of the semiconductor device according to the embodiment.

FIG. 8 is a cross-sectional view schematically showing the manufacturing process of the semiconductor device according to the embodiment.

FIG. 9 is a plan view of a part of the wafer according to the example.

FIG. 10 is a plan view of part of a wafer according to a comparative example.

FIG. 11 is a schematic view of a conventional trench element isolation technique,
It is sectional drawing which shows the formation process of an element isolation area typically.

FIG. 12 shows a case where a dummy convex region is formed,
It is sectional drawing which shows the formation process of a trench element isolation area typically.

[Explanation of symbols]

10 silicon substrate, 12 pad layer, 14 polishing stopper layer, 16 trench, 18 trench oxide film, 20 trench insulating layer, 21 insulating layer, 24
Element isolation region, 30 effective convex region, 32 dummy convex region, D1 distance between first virtual straight lines, D2
Distance between second virtual straight lines, G10, G20 Distance between sides, L1 First virtual straight line, L2 Second virtual straight line, S1, S2, S3, S4 side, T10 Length of one side of dummy convex region , X10 deviation width, Y10 deviation width, θ1 angle formed by the first virtual straight line and the row direction, θ
2 Angle between second virtual straight line and column direction

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Yoshikazu Kasuya             Seiko, 3-3-3 Yamato, Suwa City, Nagano Prefecture             -In Epson Corporation F term (reference) 5F032 AA35 AA44 BA02 CA17 DA04                       DA23 DA33 DA78                 5F038 CA05 CA07 CA18 EZ11 EZ14                       EZ15 EZ16 EZ20

Claims (7)

[Claims] 1. A trench element isolation region, a forbidden area set in the trench element isolation region, and a plurality of dummy convex regions provided in the trench element isolation region excluding the forbidden area. A semiconductor device in which the planar shapes of the dummy convex regions are equal to each other. 2. A trench element isolation region, a prohibited region set in the trench element isolation region, and a plurality of dummy convex regions provided in the trench element isolation region excluding the prohibited region. However, assuming a first virtual straight line extending along a direction intersecting the row direction, the angle formed by the first virtual straight line and the row direction is 2 to 4
The semiconductor device is 0 degrees, the dummy convex regions are arranged so as to be located on the first virtual straight line, and the planar shapes of the dummy convex regions are equal to each other. 3. A trench element isolation region, a prohibited region set in the trench element isolation region, and a plurality of dummy convex regions provided in the trench element isolation region excluding the prohibited region. However, assuming a second virtual straight line extending along a direction intersecting the column direction, the angle formed by the second virtual straight line and the column direction is 2 to 4
The semiconductor device is 0 degrees, the dummy convex regions are arranged so as to be located on the second virtual straight line, and the planar shapes of the dummy convex regions are equal to each other. 4. A trench element isolation region, a prohibited region set in the trench element isolation region, and a plurality of dummy convex regions provided in the trench element isolation region excluding the prohibited region. However, assuming a first virtual straight line extending along a direction intersecting the row direction, the angle formed by the first virtual straight line and the row direction is 2 to 4
Assuming a second virtual straight line that is 0 degree and extends along a direction intersecting the column direction, the angle formed by the second virtual straight line and the column direction is 2 to 4
It is 0 degree, The said dummy convex part area | region is arrange | positioned so that it may be located on the said 1st and 2nd virtual straight line, and the planar shape of the said dummy convex part area | region is mutually equal, A semiconductor device. 5. A trench element isolation region, a forbidden area set in the trench element isolation region, and a plurality of dummy convex regions provided in the trench element isolation region excluding the forbidden area. However, the dummy convex region has a substantially square shape in a plan view, and an interval between the dummy convex regions adjacent to each other in the row direction is approximately half the length of one side of the dummy convex region, The dummy convex regions that are adjacent to each other in the row direction are displaced from each other in the column direction, and the width of the dummy convex regions that are displaced from each other in the column direction is approximately half the length of one side of the dummy convex region. A semiconductor device in which the planar shapes of the dummy convex regions are equal to each other. 6. A trench element isolation region, a prohibited region set in the trench element isolation region, and a plurality of dummy convex regions provided in the trench element isolation region excluding the prohibited region. However, the dummy convex portion area has a substantially square shape in a plan view, and the interval between the dummy convex portion areas adjacent in the column direction is approximately half the length of one side of the dummy convex portion area, The dummy convex regions that are adjacent to each other in the column direction are displaced from each other in the row direction, and the width of the dummy convex regions that are displaced from each other in the row direction is approximately half the length of one side of the dummy convex region. A semiconductor device in which the planar shapes of the dummy convex regions are equal to each other. 7. A trench element isolation region, a prohibited region set in the trench element isolation region, and a plurality of dummy convex regions provided in the trench element isolation region excluding the prohibited region. However, the dummy convex region has a substantially square shape in a plan view, and an interval between the dummy convex regions adjacent to each other in the row direction is approximately half the length of one side of the dummy convex region, The dummy convex regions adjacent to each other in the row direction are displaced from each other in the column direction, and the width of the dummy convex regions displaced in the column direction is about half the length of one side of the dummy convex region, The distance between the dummy convex regions adjacent in the direction is approximately half the length of one side of the dummy convex regions, and the dummy convex regions adjacent in the column direction are displaced from each other in the row direction, Width of the dummy convex area shifted in the row direction Is approximately half the length of one side of the dummy convex region, and the planar shapes of the dummy convex regions are equal to each other.