JP2003332295A - Low temperature wet etching method for highly insulated thin layer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a low temperature wet etching method for a highly insulated thin layer which is advantageous for manufacturing a highly insulated gate insulating layer of a CMOS, an insulating film of a highly insulated capacitor of a DRAM, and the like and solves a problem of forming ruggedness over silicon in an active area or over USG in an isolate block. <P>SOLUTION: Wet etching is performed upon the highly insulated thin layer at a room temperature in a mixed liquid of hydrofluoric acid, perchloric acid, other perhalogenated element acid, and the like such that an etching rate of the layer becomes ≥10 Å/min, at the same time, an etching rate of silicon oxide, USG or polysilicon becomes ≤10 Å/min all and a selection ratio becomes appropriate for needs of respective processes. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a low temperature wet etching method for a highly insulating thin layer, and more particularly to an improved wet etching method for a highly insulating thin layer.

[0002]

2. Description of the Related Art CMOS (complementary metal oxide semi)
conductor) logic components and DRAM (dynamic R)
In semiconductor devices such as AM), the design standard is drastically reduced due to the increase in integration, the increase in capacity, the decrease in drive voltage, etc., and the thickness of the gate silicon dioxide film is made extremely thin. We have succeeded in making thickness less than 6nm (60Å). Therefore, it is difficult to control in this manufacturing process, and the capacitor of DRAM cannot meet the charge requirement of the memory by silicon dioxide or oxide-nitride-oxide, that is, ONO anymore. Thin film as gate insulating layer, silicon dioxide and ON
It is designed to serve as an insulating layer for DRAM capacitors that replace O. The current design standard extends to the range of 0.18 μm, and various materials are used to select the gate insulating layer, and what is particularly required is an active area that is not contaminated and easy to etch. Therefore, the dielectric constant is high and the current loss is small. Among them, the most noticeable one is hafnium oxide (Hf
O2), zirconium oxide (ZrO2), etc., and the dielectric constant (dielectric constant) k is stable at an ideal value of 15 to 25. It does not diffuse into the silicon active area and the current loss is small. However, the disadvantage is that etching is not easy.

[0003]     ≪Table 1≫     Chemicals HfO₂Etching rate (all units are Å / min)   pureHC1O_Four                0.3   pureH₂SO_Four(At 160 ℃) 1.25 ~ 5.25   pureH₃PO_Four(At 80 ℃) 0   BOE 20   pureCH₃(COOH)₂   0-2    pureHC1 0-0.9   pureHBr 2.5 ~ 10   pureHI 0   pureHF 101   pureH₂O₂                 0   TMAH 0.4 As shown in << Table 1 >> above, sulfuric acid (H₂SO_Four)
In ching, you have to heat up to a high temperature of 160 ℃,
The etching rate is only about 5Å / min.
Other examples include phosphoric acid (H₃PO_Four) And acetic acid CH₃(COO
H)₂, Hydrochloric acid (HC1), hydrobromic acid (HBr), iodo acid (HI),
Pure perchloric acid (HC1O_FourEtching rate is close to 0, but
And cannot be used to etch into silicon dioxide
Yes. Also, dry etching is not suitable for silicon.
Damages the source / drain surface and increases current loss
I will let you. Therefore, etching with hot sulfuric acid or dry
B. Others that have further developed in consideration of defects caused by etching
It is necessary to develop the etching method. However,
The insulating layer of the RAM capacitor is
It is not suitable at the current level already, and everyone after the BST etc.
I have a diffusion problem. On the other hand, hafnium oxide (HfO
_Two), The problem of diffusion is less,
However, in etching, the resistance to hot sulfuric acid etching
There is a problem of thermal equipment, and dope is not used in dry etching
Silica glass (ie USG, un-doped silica glass)
Etching selectivity of borin silica glass (BPSG) etc.
I have foot problems.

Therefore, as shown in the sectional view before the etching gate insulating layer in FIG. 1, CMOS (complementary metal oxide) is used in the conventionally used gate insulating layer of hafnium oxide.
When manufacturing a semiconductor), first, LOCOS (Local Oxide of Silicon) and STI (Shallow) are placed on the silicon wafer 1.
Isolation area 4 is formed by Trench Isolation) and p-type well 2 is formed by ion implantation by lithography.
And n-type well 3 are formed, hafnium oxide (HfO ₂ ) film 5, doped silicon 7 and tungsten silicide or other silicide film 8 are deposited, and hafnium oxide is used as an etching stop layer by lithographic etching to form gate 9. To do. Further, a small amount is doped by ion implantation by lithography to form a source / drain region 8, a silicon nitride film is further deposited on the entire surface, and further, a silicon nitride side wall 6 is formed by anisotropic dry etching. As shown in Fig. 3, ion implantation by lithography forms the LDD structure of the n ⁺ source / drain region 10 and the P ⁺ source / drain region 11 having a high doping degree. At this time, hafnium oxide is not yet removed,
It is used as a cushion layer during ion implantation to prevent damage to the silicon surface.

[0005]

However, in the known method as described above, the hafnium oxide in the source / drain region is finally removed by the known dry etching. However, the hafnium oxide is converted to USG (un-doped silica glass). Since the etching selection ratio of silicon is not large, it may be over-etched in order to completely remove hafnium oxide. Therefore, the silicon on the surface of the source / drain region and the USG of the isolation region have 14 depressed portions. Will be done. When the subsequent process is completed, an increase in the current loss of the component is unavoidable. Similarly, when the DRAM insulating layer is etched, the lower electrode (lower electrode, lower el
(ectrode) and the insulating film (IMD) between layers are also likely to be damaged. Further, in the case of wet etching with hot sulfuric acid, although the etching selectivity is excellent, the etching rate is insufficient and a heat and acid resistant tank must be used.
Therefore, in order to solve various problems related to the gate high insulation etching of the high insulation thin layer in the method of the known structure as described above, when performing low temperature etching on the high insulation thin layer, silicon dioxide, USG, polysilicon, We provide etching methods with a relatively high selectivity for silicon and silicon wafers, including USG and polysilicon gate, and source / source
Preventing the formation of a recessed part of the drain due to etching, reducing the loss of current and the height difference of the surface,
At the same time, in order to shorten the time in the manufacturing process and increase the manufacturing efficiency, a low temperature wet etching method of the highly insulating thin layer of the present invention by low temperature and wet etching, and a semiconductor device manufacturing method having a highly insulating gate insulating layer are provided. To do.

[0006]

[Means for Solving the Problems] First, hydrofluoric acid and perchloric acid (HC1O4) and other perhalogen group element acids (HBrO ₄ ,
Etch a highly insulating thin layer on silicon oxide or on polysilicon with a mixture of HIO ₄ ). The mixing ratio should be in the range of 1:50 to 1: 5000, and the most ideal ratio should be in the range of 1: 1000 to 1: 2500. Wet etching is performed at low temperature to etch highly insulating thin layers. The rate is over 10Å / min, but silicon oxide (SiO 2
₂ ), USG (un-doped silica glass), polysilicon, etc. all have an etching rate of 10Å / min or less, and this method provides extremely excellent selectivity.

In addition, CMOS (complementary metal oxide se
In order to manufacture a logic component, after forming a source / drain and a gate electrode side wall with low doping in the gate, hydrofluoric acid and perchlorine are formed in a portion on the source / drain with respect to the highly insulating gate electrode insulating layer. Etching with a mixed solution of acid or other perhalogen group acid, silicon on source / drain and USG in STI
Do not damage the polysilicon gate, the polysilicon gate, the metal gate or the refractory metal silicide gate.

Further, a DRAM for manufacturing a highly insulating capacitor
In the transistor structure and the lower electrode layer (lower electrode) for which the DRAM has been completed, a highly insulating thin layer is deposited on the lower electrode layer (lower electrode) to form the insulating layer of the capacitor, and the photoresist ( Ph
oto Resist (PR) protects the lower electrode layer (lower electrode) and the highly insulating film above it, and wet etching with a mixed solution of hydrofluoric acid, perchloric acid, and other perhalogen group element acids. To remove the highly insulating thin layers other than the lower electrode layer (lower electrode) to provide an excellent etching effect, without damaging the lower boron phosphorus silica glass (BPSG) or phosphorus silica glass (PSG). Further, the etching rate for the highly insulating thin layer is 10 Å / min or more, while the etching rate for BPSG or PSG is 10 Å / min or less.

In order to manufacture a high-insulating capacitor, a high-insulating thin layer is deposited on the front surface of the substrate of the lower electrode layer (lower electrode) to form the insulating layer of the capacitor, which is formed by a lithographic process. Photoresist (Ph
OTO Resist (PR) protects the lower electrode layer (lower electrode) and the highly insulating thin layer above it, and uses a mixed solution of hydrofluoric acid and perhalogen group element acid as an etching solution for etching at low temperatures. By proceeding, the highly insulating thin layer other than the lower electrode layer (lower electrode) is removed so as not to damage the silicon substrate and the isolation silicon oxide thereunder.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION Hafnium oxide (Hf) having a high dielectric constant is used.
The etching of the O ₂ ) layer is performed with different etching solutions. First, in the PVD (physical vapor deposition) method, USG and polysilicon are all CVD (chemical vapor deposition).
In the CVD method, the thickness before and after etching is measured with an n & k analyzer. In addition, all of these depositions and measurements are completed in a first-class dust-free room, and one person is in charge of the measurements. The highly insulating thin layer was etched with concentrated sulfuric acid (H ₂ SO ₄ ) at 160 ° C.
It is 1.25-5.25Å / min, the etching selectivity with the USG is 1: 1 and it is in the range of "OK", but it is not easy to find a bath that can withstand high temperature acid, and the bath can be maintained. Has become difficult. However, pure phosphoric acid (H ₃ PO
⁴ ), pure peroxochloric acid (HC1O ₄ ), pure hydrochloric acid (HC1),
Etching with pure hydrobromic acid (NBr), pure hydroiodic acid (HI), pure oxalic acid (COOH) 2, etc. is not suitable because the etching rate is too low. Then dilute hydrofluoric acid (HF: H2O
= 1: 2000), the etching rate for high insulation is extremely slow at 1 Å / min, and the etching rate for USG is slightly high at 7 Å / min, but the selectivity is 1: 7, which is inappropriate. . That is Shallow Trench Isolation
This is because there are too many USGs in (STI). However, when etching at a low temperature with a mixed solution of hydrofluoric acid and peroxochloric acid, the volume ratio is from 1:50 to 1: 5000, all of which are 10 Å / min or more. However, the etching rate with USG decreases as the concentration of peroxochloric acid increases, and the etching selectivity ratio between HfO ₂ and USG becomes 1: 0.65 at 1: 2000 (see FIGS. 3 and 4). ).

The mixed solution of hydrofluoric acid shown in FIG. 3 is a curve diagram of the etching selectivity of HfO ₂ and USG obtained at different mixing ratios. As can be seen from the figure, the selectivity is HfO 2.
2: USG = 1: 66 = 0.015, gradually becoming 1: 0.65 =
It has increased to 1.54, and it can be seen that the selection ratio increases as the mixing ratio increases. As shown in FIG. 4, when the volume mixing ratio is gradually increased from 1: 5 to 1: 2000, the etching rate of high insulation (HfO ₂ ) is maintained at 10 Å / min or more. The etching rate for USG gradually decreased to below 10Å / min, and the etching rate for polysilicon was
10 Å / min or less. Therefore, when etching a highly insulating thin layer (HfO ₂ ), it should be performed at room temperature and at a sufficient rate.
It can be said that the etching rate is appropriate, but the USG on the STU isolation layer and the USG on the gate and the polysilicon on the gate, metal, refractory metal silicide, polysilicon on the capacitor lower electrode layer (lower electrode), BPSG, PSG interlayer Since the etching is performed at low temperature without damaging the insulating film (IMD), the time and cost of preparing a tank having a complex structure that withstands acid is saved, and it becomes suitable for mass production. The volume mixing ratio of hydrofluoric acid and peroxochloric acid is in the range of 1:50 to 1: 500 at low temperature (0 to 100 ° C), and the etching rate to the hafnium oxide (HfO ₂ ) layer and wet oxide film and US
The selection ratio for G, BPSG, polysilicon, etc. is sufficient, and the ideal range is 1: 1000 to 1: 2500. The etching method is a single-piece etching machine (Si
ngle wafer tools), batch type etching machines, multi-cavity etching machines (Clusters tools) and single-cavity etching machines (Stand alone tools), and achieves the purpose of etching highly insulating thin layers at low temperatures. However, the present invention is not limited to this, and any one can be used as long as hydrofluoric acid and peroxochloric acid can contact the wafer. Further, even if other perhalogen group element acid is replaced with perchloric acid, the effect is almost the same. Therefore, the mixed solution of the present invention is not limited to HF: HC1O ₄ , and HF: halogen group element acid (HbrO ₄ , HIO ₄ ).

In the second embodiment, the manufacturing sequence is as shown in FIGS. 5 to 15, and the CMOS (comp.
In the method of manufacturing the logic component 200, the procedure and method for forming the highly insulating gate are particularly emphasized (see FIG. 5 for the structure of the CMOS logic component 200). Although the conductivity type of the silicon semiconductor substrate is p-type in the following description, an n-type substrate may be used or an SOI (Silicon on insulator) substrate may be used. STI (Shallow TrenchIsolati
However, the present invention is not limited to this, and other methods such as Local oxidation of Silicon (LOCOS) may be adopted. Tungsten silicide may also be used on the polysilicon gate, again but not exclusively. TiSi2, CoSi2
And the like may be replaced by WSix. The gate is not limited to the polysilicon gate, but may be other metal gates or refractory metal silicide gates, and is a highly insulating gate insulating film CMOS (complementary metal oxide semiconducto).
r) It is not limited to the above as long as it includes a matching process.

As shown in FIG. 6, STI (Shallow Trench Isolation) is selectively performed on the p-type silicon wafer substrate 1.
An isolation area 4 is provided to form an active area, and then a p-type well 2 and an n-type well 3 are formed by ion implantation by lithograph, the p-type well area being an NMOS area and the n-type well area being Form the PMOS area. Next, as shown in FIG. 7, a highly insulating thin layer (HfO ₂ or ZrO ₂ ) 5 is formed on the above substrate by the PVD method, a gate insulating film is formed, and then a polysilicon layer 6 is formed on the entire surface. That is, the polysilicon gate to be formed later is formed.

As shown in FIG. 8, the n-type well area 3 is lithographically processed to form a photoresist (Photo Resist, P.
R.) PR1 is coated, and n-type impurities (As ⁺ or P ⁺ ) are ion-implanted into the polysilicon layer 6 on the p-type well region 2 to form a N ⁺ -doped polysilicon layer 6a having low electric resistance. To do. After the photoresist PR1 is removed, in the process shown in FIG. 9, the p-type well area 2 is lithographically covered with the photoresist PR2, and impurities (B ⁺ and BF2 ⁺⁺ are added to the polysilicon layer on the p-type well area 2 by ion implantation). Implanted and p ⁺ -doped polysilicon layer 6b with low electrical resistance
To form.

Then, after removing the PR2, as shown in FIG. 10, a tungsten silicide (WSix) layer 7 is deposited on the entire surface to reduce the resistance of the gate, but it is not necessary to deposit tungsten silicide, In the above procedure, tungsten silicide may be formed together with the source / drain. As shown in FIG. 11, a lithographically formed gate photoresist is formed on tungsten silicide, and the tungsten silicide layer 7 and the polysilicon layer 6 are selectively etched to form the tungsten silicide layers 7a and 7b for forming gates. The polysilicon layers 6c and 6d are used as gates 9a and 9b, respectively. Next, as shown in FIG. 12, by lithography on the n-type well area 3 to form a photoresist PR3, under the coating with the gate 9a and the photoresist, a very small amount ^{(1 × 10 1 3 ~1 ×} 10 14
cm ⁻² ) n-type doping (As ⁺ or P ⁺ ) is ion-implanted in the p-type well region, and n ⁻ source / drain region 10
To form.

As shown in FIG. 13, after removing the PR3, a photoresist PR4 is formed on the p-type well 2 by a lithographic method, and an extremely small amount (1) is formed under the condition that the photoresist PR4 is covered with the gate 9b and the photoresist. P of × 10 ¹³ to 1 × 10 ¹⁴ cm ^-2 )
The type dope (B ⁺ ) is ion-implanted in the p-type well region 3 to form p ⁻ source / drain regions 11. As shown in FIG. 14, after the PR4 is removed, a silicon nitride layer is formed on the entire surface, and anisotropic silicon nitride dry etching is used to form the silicon nitride side wall 8. At this time, the gate 9 is formed.
Highly insulating thin layer 5 is exposed except for a and 9b and the side wall 8 where it is covered. As shown in FIG. 15, hydrofluoric acid, perchloric acid, and other perhalogen group element acids are used as etching liquids to cover the gates 9a and 9b and the side walls 8 and perform wet etching in an acid bath. / Remove the highly insulating thin layer on the drain and isolation tank. HF used: HC1O ₄
The volume mixing ratio is 1:50 to 1: 5000, and the most ideal is 1: 1000 to 1: 2500, which is low temperature (0 ℃ ~ 100
Etching proceeds at (° C.). This method is a known method, in which sulfuric acid is easier to perform etching at a temperature of 160 ° C., and equipment does not need to consider heat resistance,
Moreover, the etching rate is fast, it is less likely to damage silicon and silicon oxide (USG or wet oxide) than dry etching, and current loss and surface irregularities are avoided as much as possible.

CMOS (complementary metal oxide semico)
The manufacturing process of the gate of the nductor) component ends here, and the subsequent manufacturing process is performed in the same manner as a known method. For example, LDD of n ⁺ and p ⁺ by ion implantation
If the source / drain is formed, a silicide (TiSi ₂ or CoSi ₂ ) is formed on the source / drain, and the gate has not yet formed tungsten silicide, the silicide formed by this procedure is It is formed on the silicon 6a and 6b, and the metallization process which is the subsequent manufacturing process is completed (see FIG. 5 for the completed CMOS logic component).

In the third embodiment, as shown in FIG. 16, a DRAM of a highly insulating insulating layer (HfO ₂ or ZrO ₂ ) capacitor forms a stack lower electrode layer (lower electrode), and a highly insulating thin layer is formed. (HfO ₂ or ZrO ₂ ) is a cross-sectional view after deposition,
Isolation tank 4, LDD source / drain 12 on p-type well 2
(Or n ⁺ source / drain instead of LDD) Gate 9, interlayer insulating film (ILD) 15, tungsten or polysilicon contact hole 17, intermetallic insulating film (IMD) 16 formed by BPSG, and silicon nitride etch stop layer 1
9. After completing the manufacturing process of the lower electrode layer (lower electrode) 21, etc., the highly insulating thin layer 22 is deposited by PVD to form the capacitor insulating layer (see FIG. 16), but the lower layer is not limited to this. The electrode layer (lower electrode) may have a stack shape or other large area shape.

As shown in FIG. 17, a lower electrode layer (lower electrode) and a lower electrode which are protected by photoresist PR5 by using hydrofluoric acid, perchloric acid, or other perhalogen group element acid as an etching solution. The highly insulating thin layer on the layer (lower electrode) is wet-etched in an etching machine to remove the highly insulating thin layer except the lower electrode layer (lower electrode). HF used: HC
The volume mixing ratio of 1O4 is 1:50 to 1: 5000, and low temperature (0 ℃ ~
Etching at 100 ° C) proceeds. According to this method, sulfuric acid by a known technique is easier than etching at a high temperature of 160 ° C., and the cost and labor related to equipment of high temperature resistance and acid resistance required for equipment can be saved. Incidentally, the etching rate was also successfully increased, and the purpose of avoiding current loss and surface unevenness as much as possible was achieved without damaging the metal interlayer insulating film (IMD) 16 of BPSG by dry etching. As shown in FIG. 18, during the subsequent manufacturing process, the polysilicon top electrode 23 and another layer IMD 24, etc. connect the uppermost electrode layer (top electrode) to the bonding pad 26 through the through hole 25. , The steps such as grounding by electric welding are completed (see FIG. 17).

In Example 4, a high-insulating thin layer was deposited on the entire surface of a substrate on which a lower electrode layer (lower electrode) had been completed to form an insulating layer of a capacitor, and then the lower layer was formed by a photoresist formed by lithography. The lower electrode layer (lower electrode) is protected by protecting the electrode layer (lower electrode) and the highly insulating thin layer above it, and the mixed solution of hydrofluoric acid and perhalogen group element acid is used as an etching solution to carry out etching at a low temperature. Similar etching effects of the high insulating thin layer can be obtained by removing the high insulating thin layer other than the lower electrode and then depositing the top electrode and completing the subsequent metallization step.

[0021]

EFFECTS OF THE INVENTION According to the present invention, the problems of heat resistance and acid resistance, which were required in the equipment in the conventional process, are solved, the cost is reduced and the manufacturing process is facilitated, and the active area is reduced. By avoiding the formation of irregularities, it was possible to provide an excellent etching effect in terms of both cost and quality.

[Brief description of drawings]

FIG. 1 is a CMOS (complementary meta) according to a known technique.
FIG. 6 is a cross-sectional view after forming the silicon nitride side wall of the gate in the initial stage of the manufacturing process of the oxide semiconductor) and before etching the gate insulating layer.

FIG. 2 is a CMOS (complementary meta) according to a known technique.
FIG. 3 is a cross-sectional view of a highly insulating thin layer which is etched after a heavily doped source / drain is formed in the initial stage of the manufacturing process of the oxide semiconductor).

FIG. 3: HfO obtained with different volume ratios for HF and HC1O4
FIG. 3 is a curve diagram showing etching selectivity ratios of ₂ and USG.

FIG. 4 is a curve diagram of etching rates for highly insulating HfO ₂ , USG, and polysilicon according to mixing ratios of different volumes of HF and HC1O ₄ .

FIG. 5: CMOS (complementary metal oxide semiconduc)
tor) is a cross-sectional view after the manufacture of the logic component is completed.

FIG. 6 CMOS (complementary metal oxide semiconduc)
tor) is a cross-sectional view of the substrate.

FIG. 7 is a cross-sectional view after deposition of high insulation (HfO ₂ ) and polysilicon.

FIG. 8 shows a manufacturing process after doping n ⁺ into polysilicon.

FIG. 9 shows a manufacturing process after doping p ⁺ into polysilicon.

FIG. 10 is a step of depositing tungsten silicide.

FIG. 11 is a step of forming a gate by etching tungsten silicide and polysilicon.

FIG. 12 is a step of forming an n ⁻ -doped source / drain gate by ion implantation.

FIG. 13 shows a step of forming p ⁻ -doped type source / drain gates by ion implantation.

FIG. 14 shows a step of forming sidewalls by anisotropic etching after the deposition of chip silicon.

FIG. 15 is a step of performing etching with high insulation (HfO ₂ ) on the source / drain gate with a mixed solution of HF and HC1O ₄ .

FIG. 16 is a cross-sectional view of a DRAM in which a stack type lower electrode layer (lower electrode) is formed and then a high insulation property (HfO ₂ ) is deposited.

FIG. 17 is a cross-sectional view after the DRAM has been etched with high insulation.

FIG. 18 is a cross-sectional view after completion of DRAM.

[Explanation of symbols]

1 p-type silicon wafer substrate 2 p-type well 3 n-type well 4 LOCOS or STI isolation layer 5 high insulating (HfO ₂ ) layer 5a high insulating (HfO ₂ ) gate insulating layer 6 polysilicon gate 6a phosphorus-doped polysilicon 6b , 6c, 6d polysilicon layer 7 WSix or TiSi2 7a, 7b tungsten silicide layer 8 silicon nitride (Si ₃ n ₄₎ side walls 9, 9a, 9b gate 10 n ^- lightly doped 11 p ^- lightly doped 12 n ^- source / drain 13 p ^- source / drain 14 recessed portion after etching 15 interlayer insulating film (ILD) 16 metal interlayer insulating film (IMD) 17 contact hole 18 metal wire 19 silicon nitride 20 through hole 200 logic component 21 lower electrode layer (lower elect Road) (lower El
ectrode) 22 Capacitor High insulation (HfO ₂ or ZrO ₂ ) insulation film 24 IMD 25 Through hole 26 Bonding pad PR1, PR2, PR3 Photoresist

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Xiao Seoto             No.71, 2nd dan, Minamishinsato Beigang Road, Taibo City, Chiayi County, Taiwan (72) Inventor Yasu Munetaka             No.123-1, No.123-1, 89, Gwangbokro, Hsinchu City, Taiwan             Tower 2 (72) Inventor Choi             No.56 University Road 56, Hsinchu City, Taiwan (72) Inventor Hwang             Taiwan Hsinchu City University Road 1001 No. 4 process 630 rooms (72) Inventor Liang Jianxiang             Taiwan Hsinchu City University Road 1001 No. 4 process 630 rooms F-term (reference) 5F043 AA37 BB25 EE40

Claims (24)

[Claims] 1. A low-temperature wet etching method for a highly insulating thin layer, wherein at least first, a wafer having a highly insulating thin layer deposited on a silicon dioxide layer or polysilicon is prepared, and then, a wafer containing hydrofluoric acid is used. A highly insulating thin layer is characterized in that it comprises a step of etching a highly insulating thin layer on a wafer surface with a mixed solution of a halogen group element acid, further washing the wafer with ionized water and then drying. Low temperature wet etching method. 2. A highly insulating gate insulating layer CMOS (complementar)
y metal oxide semiconductor (LO) on a wafer that is USG (un-doped silicon glass) in a logic component manufacturing method.
COS (Local Oxide of Silicon) and STI (Shallow Trench
Forming an isolation ku by Isolation), as well as to form a p-type well and n type well, forming a gate conductive layer is deposited a highly insulating thin layer, patterning the gate by lithography, n ^- the p-type well And p ⁻ into the n-type wells by ion implantation, the source / drain regions are lightly doped, silicon oxide is deposited, and the silicon dioxide side wall of the gate is formed by etching. The highly insulating thin layer is etched with a mixed solution of perhalogen group acid to remove the highly insulating thin layer on the source / drain, and it is covered with the gate and the silicon dioxide side wall, and ion-implanted by self-alignment. A low-temperature wet etching method for a highly insulating thin layer, comprising a step of heavily doping a source / drain region and finally performing a metallization step. 3. A method of manufacturing a highly insulating thin-layer DRAM, comprising:
By using the substrate of the lower electrode layer (lower electrode), a highly insulating thin layer is deposited on the entire surface of the lower electrode layer (lower electrode) to form the insulating layer of the capacitor, and the photoresist (Photo Resist
t, PR) to protect the lower electrode layer (lower electrode) and the highly insulating thin layer above it, and use a mixed solution of hydrofluoric acid and halogen group acid as an etching solution to etch at low temperature. To remove highly insulating thin layers other than the lower electrode layer (lower electrode), deposit the uppermost electrode layer (top electrode), and complete the subsequent metallization process. Low temperature wet etching method for highly insulating thin layers. 4. In the method for manufacturing a high insulation thin layer capacitor, a high insulation thin layer is first deposited on the entire surface of a lower electrode layer (lower electrode) by a substrate having at least a lower electrode layer (lower electrode) completed. Then, it is used as the insulating layer of the capacitor, and photolithography (Photo Resist, P.
R.) is formed to protect the lower electrode layer (lower electrode) and the highly insulating thin layer thereabove, and etching is carried out at a low temperature using a mixed solution of hydrofluoric acid and a halogen group element acid as an etching solution. A process characterized by including the steps of removing the highly insulating thin layers other than the lower electrode layer (lower electrode), depositing the upper electrode layer (top electrode), and completing the subsequent metallization process. Low temperature wet etching method for insulating thin layers. 5. The highly insulating thin layer is hafnium oxide (HfO ₂ ).
Claims 1, 2, 3, characterized in that
4. The low temperature wet etching method for a highly insulating thin layer according to 4. 6. The thin insulating layer is zirconium oxide (ZrO 2).
₂ ) According to claim 1 or 2,
3. A low-temperature wet etching method for a highly insulating thin layer described in 3 and 4. 7. The halogen group element acid is peroxochloric acid (HC1O ₄ ).
4. The low temperature wet etching method for a highly insulating thin layer according to 4. 8. The halogen group element acid is peroxobromic acid (Hb
The low temperature wet etching method for a highly insulating thin layer according to claim 1, 2, 3 or 4, characterized in that it is rO ₄ ). 9. The halogen group element acid is peroxoiodoic acid (HIO ₄ ).
A low temperature wet etching method for a highly insulating thin layer as described. 10. A highly insulating thin film according to claim 1, wherein the volume mixing ratio of hydrofluoric acid and halogen group element acid is in the range of 1:50 to 1: 5000. Low temperature wet etching of layers. 11. The high insulating property according to claim 1, wherein the volume mixing ratio of the hydrofluoric acid and the halogen group element acid is in the range of 1: 1000 to 1: 2500. Low temperature wet etching method for thin layers. 12. The wet etching is performed at a low temperature of 0 ° C. to 100 ° C.
A low temperature wet etching method for a highly insulating thin layer as described. 13. The low-temperature wet etching method for a highly insulating thin layer according to claim 1, wherein the wet etching is performed in a single wafer tool. . 14. The low temperature wet etching method for a highly insulating thin layer according to claim 1, wherein the wet etching is performed in a batch type etching machine. 15. The low temperature wet etching method for a highly insulating thin layer according to claim 1, wherein the wet etching is performed in a multi-cavity etching machine (Clusters tools). 16. The low-temperature wet etching method for a highly insulating thin layer according to claim 1, 2, 3 or 4, wherein the wet etching is carried out in a single cavity type etching machine (Stand alone tools). . 17. An etching rate of a silicon wafer by a mixed solution of hydrofluoric acid and halogen group element acid is 10Å / min.
5. The low temperature wet etching method for a highly insulating thin layer according to claim 1, wherein: 18. The etching rate of the mixed solution of hydrofluoric acid and halogen group element acid with respect to a highly insulating thin layer of zirconium oxide is 10 Å / min or less. A low temperature wet etching method for a highly insulating thin layer as described. 19. A highly insulating thin film according to claim 1, wherein the mixed solution of hydrofluoric acid and halogen group element acid has an etching rate for silicon oxide of 10 Å / min or less. Low temperature wet etching of layers. 20. The highly insulating thin layer according to claim 1, wherein the mixed solution of hydrofluoric acid and halogen group element acid has an etching rate with respect to USG of 10 Å / min or less. Low temperature wet etching method. 21. The etching rate of a mixed solution of hydrofluoric acid and a halogen group element acid with respect to borophosphorus silica glass (BPSG) is 10 Å / min or less. A low temperature wet etching method for a highly insulating thin layer as described. 22. The etching rate of a mixed solution of hydrofluoric acid and a halogen group element acid with respect to phosphorus silica glass (PSG) is 1.
0 Å / min or less, Claims 1, 2,
3. A low-temperature wet etching method for a highly insulating thin layer described in 3 and 4. 23. The highly insulating thin film according to claim 1, wherein the mixed solution of hydrofluoric acid and halogen group element acid has an etching rate for polysilicon of not more than 10 Å / min. Low temperature wet etching of layers. 24. The etching rate of a mixed solution of hydrofluoric acid and a halogen group element acid with respect to a silicon wafer is 10Å / mi.
The low-temperature wet etching method for a highly insulating thin layer according to claim 1, 2, 3, or 4, wherein n or less.