JP2003332189A - Semiconductor test system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor test system which is capable of realizing a more effective and optimal test for semiconductors. <P>SOLUTION: The semiconductor test system 1 is composed of a semiconductor test device 3 which does a test consisting of a plurality of test items on semiconductor chips, which are formed on a semiconductor wafer, on the basis of a test program and a control device 2 which controls the test program, and the semiconductor test device 3 and the control device 2 are connected together through a communication network 4. The control device 2 is equipped with a collecting means 51 of collecting test result data on a plurality of the test items and a determining means 52 of determining the omissible test items for all the semiconductor chips or the semiconductor chips meeting the prescribed conditions, a test program formulating means 61 of formulating a test program which omits the test items that are determined to be omitted, and a transmission means 62 of transmitting the formulated test program. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor test system for testing a plurality of test items on a semiconductor chip formed on a semiconductor wafer.

[0002]

2. Description of the Related Art Conventionally, a manufacturing process of a semiconductor chip such as an integrated circuit (IC) is performed by, for example, a wafer forming process in which chips are formed after processing a silicon substrate etc.
A wafer test process for testing good and defective semiconductor chips, etc. on the created wafer, an assembly process for mounting semiconductor chips that have passed the wafer test, and all test items for all components in the final product after assembly is completed. It is composed of the final test process and so on. Here, in the wafer testing process, since the semiconductor chips created in the wafer creating process may have variations in characteristics between products, by extracting semiconductor chips having characteristics that deviate from the specified standard, This is executed for the purpose of preventing an unnecessary increase in the assembly cost due to a defective product flowing out to the assembly process of the next process.

[0003]

In the wafer test process described above, if all the test items similar to the test items executed in the final test process are performed, the extra assembly cost (time (Cost, cost) can be avoided. However, in the wafer test process, executing all the tests that overlap with the final test process may also execute test items that are not necessary, and there is a problem in terms of manufacturing cost and manufacturing efficiency. On the other hand, if some or all of the test items are omitted from the wafer test process in anticipation that all test items will be executed in the final test process, some defective products will inevitably flow to the assembly process. Therefore, there is a problem that the yield is deteriorated.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor test system capable of realizing a more efficient and optimum semiconductor test.

[0005]

In order to solve the above problems, the present invention provides a test program for testing a plurality of test items on a semiconductor chip formed on a semiconductor wafer, for example, as shown in FIGS. And a management device (semiconductor management device 2, test program optimization server 5, test program management) that manages the test program used in this semiconductor test device. Server 6) is connected to the semiconductor test system 1 via a communication network (LAN 4), and the management device collects test result data of a plurality of test items for the semiconductor chip ( For example, the test program optimization server 5,
Controller 51) and a determining means for determining an omissible test item for all semiconductor chips or for semiconductor chips satisfying a predetermined condition, based on the test result data collected by the collecting means. (For example, the test program optimization server 5, the control unit 51, etc.) and a test in which the test items determined by the determining unit are omitted for all semiconductor chips or for semiconductor chips satisfying a predetermined condition. Test program generating means for generating a program (for example, the test program management server 6,
Control unit 61) and a transmission unit (for example, test program management server 6, communication unit 62, etc.) that transmits the test program generated by the test program generation unit to the semiconductor test device. Performs a test according to the test program transmitted by the transmitting means.

Further, the determining means of the management apparatus in the semiconductor system of the present invention is a defective product rate calculating means (for example, a test program) for calculating the defective product occurrence rate for each test item based on the test result data. The optimization server 5, the control unit 51, etc.) to increase the manufacturing cost based on the defective product occurrence rate of one test item calculated by the defective product rate calculating unit, and the test cost of the test item. Based on this, the test omission of the relevant test item is decided.

Further, the management device 2 of the present invention includes a test program optimization server 5 including the collecting means and the determining means, a test program generating means, and a test program managing server 6 including the transmitting means. And the test program optimization server creates optimization information creating means for creating optimization information for omitting the test of the test item determined by the determining means (for example,
Control unit 51 and the like) and optimization information transmitting unit (for example, communication unit 55 and the like) that transmits the optimization information created by the optimization information creating unit to the test program management server.
And the test program generation means of the test program management server generates a test program based on the optimization information transmitted by the optimization information transmission means.

[0008] Here, the optimization information includes, for example, test item information that can be omitted from a plurality of test items included in the test program, and depends on the test cost of performing the test and the non-execution of the test. This is the basic information for creating the most appropriate test program considering the negative cost.

Further, the test program management server 6 of the present invention is provided with a timing judging means (for example, a control section 61 etc.) for judging whether or not it is a preset test program generating time, and the test program generating server The means generates the test program when the time determination means determines that it is time to generate the test program.

Further, the test program optimizing server 5 of the present invention includes template data creating means (eg, the control unit 51, etc.) for creating template data of a test program having test contents of all test items, and the template data creating. Template data transmission means for transmitting the template data created by the means to the test program management server 6 (for example, the communication unit 55, etc.)
And the test program management server 6 stores the template data transmitted by the template data transmitting unit (for example, the storage unit 63).
Etc.), the test program creation means creates a test program based on the template data stored in the storage means and the optimization information.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION A semiconductor test system according to an embodiment of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a diagram showing the overall structure of a semiconductor test system according to the present embodiment. As shown in FIG. 1, a semiconductor test system 1 of the present invention manages a test execution process of a plurality of test items on a semiconductor chip formed on a semiconductor wafer. ), And according to the management of this management device 2,
The management apparatus 2 includes a semiconductor test apparatus 3 (hereinafter, referred to as a test apparatus) that executes the test of the above test items.
And the test apparatus 3 are connected by, for example, a LAN 4. It should be noted that the LAN 4 is not the only option, and it may be, for example, an intranet or WAN.

The management apparatus 2 collects information for optimally creating a test program for causing the test apparatus 3 to execute a semiconductor test, and optimizes a test program for creating optimization information of the test program by calculation or the like. The test program optimization server 5 includes a server 5 and a test program management server 6 that manages the test program such as creating a test program based on the optimization information and transmitting the test program to the test apparatus 3. The test program management server 6 is connected to a network such as LAN 4. The test program optimizing server 5 internally includes, for example, a control unit 51 and a display unit 5 as shown in FIG.
2, input unit 53, printing unit 54, communication unit 55, storage unit 56
Etc., and each unit is connected by a bus 57.

The control unit 51 uses, for example, a CP (not shown).
U, RAM, etc., and reads programs, data, etc. stored in the storage unit 56 to temporarily store the data in the RAM (not shown), and then controls each unit, transfers the data, Performs various calculations.

Specifically, the control unit 51, as a collecting means, executes a test result information collecting process for collecting the test result information executed by the test apparatus 3. In addition, the control unit 51
Is a defective product rate calculating means, calculates a defective product rate based on the test result information collected from the test apparatus 3, and determines a defective product rate data, a test result information, and a final test process. From the result information and the like, a test item in which the overall manufacturing cost is lower when the test is omitted is determined, and the process of creating the omitted test item information is controlled. Further, the control unit 51, as a template data creating means, controls the creation process of the template data of the test program including the test contents of all the test items.

The display unit 52 is composed of, for example, a CRT or LCD, and displays various display data and images input from the control unit 51.

The input unit 53 is provided with, for example, a mouse and a keyboard, and can select and specify the designation information displayed on the screen of the display unit 52, or input desired designation information or the like. Specifically, for example, it is used by the operator to input / designate predetermined information or an execution instruction signal for performing optimization.

The printing unit 54 is, for example, a printing machine, and is used to print out data analysis results, test results, defective product rate data, and the like.

The communication unit 55 (optimization information transmission means, template data transmission means) is composed of a modem, a terminal adapter, a router, etc., and communicates with the test program management server 6, the test apparatus 3, or an external device. Control for.

The storage unit 56 is pre-stored with programs, data and the like, and has a structure including a magnetic or optical recording medium or a recording medium (not shown) readable by the control unit 51 such as a semiconductor memory. . This recording medium is C
It includes a portable medium such as a D-ROM and a memory card and a fixed medium such as a hard disk. In addition, this storage unit 56
The programs, data, etc. stored in the server may be configured to receive a part or all of them from other servers or devices via a network such as WAN, LAN4, etc., and the storage unit may be a server connected via a network or The storage unit of another device may be used.

The storage unit 56 records and stores various operations of the semiconductor test system 1 according to the present embodiment, for example, various application programs and various data for executing optimum information creating processing. Specifically, the storage unit 56 includes a test reference data DB 56a, a test program template DB 56b, a test result information storage DB.
56c, an optimization information DB 56d, an optimization information creation program 56e, a data analysis program 56f, etc. are stored.

The test reference data DB 56a is a database that stores various reference data relating to the execution of semiconductor tests. Specifically, the test reference data DB 56a
For each semiconductor test, reference value data 56a relating to the time and cost of performing the test is included.
1 and the assembling cost data 5 regarding the cost in the assembling process of the semiconductor chip performed after the wafer test process.
6a2, final test cost data 56a regarding the test cost in the final test process after the semiconductor chip assembly process
3. Monitor condition data 56a4 related to various monitor processes in the semiconductor test are stored.

Test program template DB 56b
Is a database that stores template data 56b1 of the test program created by the test program management server 6. This template data 56b1
Is data including test item content information of all tests in the semiconductor chip wafer test process executed by the test apparatus 3, and includes a test program created by the test program management server 6, an optimum test program, and a monitor test. This is basic data such as a program.

The test result information storage DB 56c is a database for storing and storing the result information of the test executed by the test apparatus 3. Specifically, for example, cost data such as the test execution time and cost is stored. 56c1, defective product rate data 56c2, etc. are stored for each test. Although not shown, physical parameter (film thickness, processing dimension, etc.) value and electrical parameter (voltage, current, resistance, etc.) value for judging whether the semiconductor chip to be tested is good or defective It may be configured to store the information such as The test result information is data transmitted from the test apparatus 3 in a predetermined data format, and data obtained by data analysis processing of the data.

The optimization information DB 56d is a database that manages and stores the optimization information 56da in the execution of the test program created by the control unit 51. Specifically, the optimization information DB 56d is, for example, omitted test item data. 56d1, monitor condition information 56d2, etc. are stored for each test program. In detail, the optimization information is defined by the control unit 56 based on the data of the test reference data DB 56a, the test result information storage DB 56c, and the like.
In the wafer test process, it is necessary to omit the test item data, that is, the final manufacturing cost is lower, that is, the omitted test item data 56d1 and the omitted test item are adjusted or reviewed, and the defective product rate is reviewed. It is composed of monitor condition information 56d2 and the like for executing the monitor test processing for executing all the test items.

The optimization information creation program 56e includes the test reference data DB 56a and the test result information storage D.
Based on the test result information stored in B56c,
Determining process to determine the optional test items by calculating the test cost when the defective product ratio is lower than the predetermined standard, the test cost by executing the test, the assembly cost when the defective product is assembled, the final manufacturing cost, etc. , And the monitor condition information creation processing based on the above, are programs programmed to be executable under the control of the control unit 51.

The data analysis program 56f is a program for extracting the cost, defective product rate, etc. for each test by data analysis of the test result information transmitted from the test apparatus 3. Here, the test result information includes the result of the test executed according to the optimum test program, the result of the test executed according to the monitor test program, and the like. Then, in detail, the data analysis program 56f determines, for example, from the physical parameter (film thickness, processing dimension) value measured in the test apparatus 3, the electrical parameter (voltage, current, resistance, etc.) value, or the like of the chip. This is a program for classifying and analyzing defective products for each test.

The test program management server 6 manages the test program such as creating an optimum test program based on the template data transmitted from the test program optimization server 5 and the optimization information and transmitting it to the test apparatus 3. Is a device for executing. The test program management server 6 internally includes a control unit 6 as shown in FIG.
1, a communication unit 62, a storage unit 63, etc.
It is connected by a bus 64. Here, since the functions of these units are almost the same as those of the test program optimizing server 5, detailed description will be omitted and only different points will be described below. The test program management server 6
A display unit similar to the test program optimization server 5,
It may be configured to include an input unit, an output unit, and the like.

The control unit 61 includes a CPU and a RAM (not shown).
As the test program generating means, it controls the optimum test program creating process for creating the optimum test program based on the template data transmitted from the test program optimizing server 5 and the optimization information. Further, the control unit 61 controls, as timing determination means, the determination processing as to whether or not the test program creation processing is to be executed, and as the monitoring condition establishment determination means, based on the monitor condition information included in the optimization information, The test apparatus 3 executes a process of determining whether the conditions for executing the monitor test are complete. In addition, the control unit 61
The monitor test program creating means executes a process of creating a monitor test program to be executed by the test apparatus 3 based on the monitor condition information. Here, the monitor test program is, for example, a program in which an operation for causing the test apparatus 3 to execute all test items including test items omitted in the optimization information is programmed.

In the storage unit 63, in the present embodiment, for example, an application program for implementing a test program management process such as an optimum test program creation process, each processing program, and data processed by the processing program. Is stored. Specifically, the optimum test program DB 63a, the monitor test program DB 63b, the distribution data DB 63c, the optimum test program generation program 63d, the monitor test program generation program 63e, and the like are stored.

The optimum test program DB 63a is a database that stores and manages the optimum test programs created by the control of the control unit 61 by classifying them for each test.
The optimum test program means that the execution operation of the omitted test item data is omitted based on the optimization information and the test program template data created by the test program optimization server 5 by the optimum test program creation process of the control unit 61. It was regenerated into an optimal test program. Then, for example, in the optimum test program 63aa, the instruction to execute the test item to be executed in the test apparatus 3 and the instruction to collect the result information of the test item are programmed by the number of the test items.

The monitor test program DB 63b is a database for storing a monitor test program for monitoring the operation status of the test apparatus 3 and the like. The monitor test program is a program created by the control unit 61 based on the monitor condition information in the optimization information transmitted from the test program optimization server 5. Then, for example, a monitor test program 63ba
Is programmed with an instruction to execute all test item data and an instruction to collect test result information for each test item. By executing the monitor test program, the calculation of the defective product rate is reviewed to adjust the optimization information, detect the defective lot, and detect the characteristic of failure unique to the test apparatus 3, such as the failure of the test apparatus 3. It is possible.

The distribution data DB 63c stores the template data 6 sent from the test program optimization server 5.
3c1, optimization information 63c2, etc. is a database that manages and stores data related to the optimum test program creation process and the monitor test program creation process.

Optimal test program generation program 6
In 3d, the control unit 61 programs the operation for generating the optimum test program. Also, a monitor test program generation program 63e
Is a program of the operation for the control unit 61 to generate the monitor test program.

The test device 3 is a device for testing a semiconductor chip formed on a semiconductor wafer based on various instruction signals transmitted from the management device 2. As shown in FIG. 31 and a test apparatus main body 32 and the like. The test apparatus main body 32 has a test head 32a for mounting a semiconductor chip formed on a semiconductor wafer and measuring original data for determining a good product or a defective product. The test head 32a is provided with a prober or the like (not shown). Here, the content of the semiconductor test executed by the test apparatus 3 is the content of an existing test, and for example, process parameters (eg, film thickness, processing size, etc.) for physical evaluation / management of the structure of the chip, etc. ) Or the values of electrical parameters (for example, voltage, current, resistance, etc.) for performance evaluation / management of the chip, and whether the chip is good or bad is tested based on the measurement result.
Among these, as an electrical test, for example, there is a test called a probe test. In this probe test, the prober is brought into contact with the electrode pads on the chip
By measuring the performance, frequency, voltage and current, etc., the non-defective and defective chips are determined.

Further, the control unit 31 includes a CPU (not shown),
A RAM or the like is provided, and for example, an optimum test program test transmitted from the test program management server 6,
The monitor test program is temporarily stored in the RAM, and controls the operation of the test apparatus main body 32 so as to execute the semiconductor test based on the execution instruction of the test item of the optimum test program or the monitor test program. Further, the control unit 31 controls so that the test result information for each test item executed by the test apparatus main body 32 is transmitted to the test program optimization server 5 based on the information collection instruction of the optimum test program. .

The operation flow of the semiconductor test system 1 configured as described above will be described below with reference to the flow charts shown in FIGS.

The operation flow of the optimization information creation process executed in the test program optimization server 5 will be described with reference to the flowchart of FIG.

First, in the test program optimization server 5, the control unit 51 creates template data of a test program to be executed in the semiconductor wafer test process after the semiconductor wafer manufacturing process, and the created template data is used as the test program management server. 6 (step S101). Specifically, based on an input signal from the operator of the test program optimization server 5 or the like, the control unit 51
For each test executed in the semiconductor wafer test process, template data of a test program including test content information of a plurality of test items included in the test is created and stored in the test program template DB 56b. Then, the control unit 51 transmits the created template data to the test program management server 6 via the LAN 4 by the communication unit 55.

Next, the control unit 61 of the test program management server that has received the template causes the distribution data DB 6
The template data is stored in 3c (step S10).
2).

Next, the test program optimization server 5
The control unit 51 determines whether it is the optimization information creation time for optimizing the test program according to the main program or the like (step S103), and when it is determined that it is the optimization information creation time (step S103). S103:
If Yes), the process proceeds to step S104 and it is determined that it is not the optimization processing time (step S103: No).
Repeat this process until the time comes. The timing of the optimization process performed by the control unit 51 is determined, for example, in a predetermined time period, when the accumulated amount of information for optimization exceeds a certain reference amount, or when the test program optimization server 5 is used.
Is performed based on the operator's instruction or the like.

In step S104, the control unit 51 of the test program optimization server 5 reads the test result information previously received from the test apparatus 3 and stored in the test result storage information DB 56c according to the optimization information creation program 56e. Temporarily store in RAM. Next, the control unit 51 executes data analysis processing, such as calculation of a defective product rate and calculation of a monitor execution frequency, on the read test result information for each test item according to the data analysis program 56f, and outputs the analysis result data. Test result accumulation information DB 56
It is stored in c (step S105).

Next, the control section 51 executes the optimization information creation and distribution processing based on the above analysis data.
Specifically, the control unit 51 controls the test reference data DB 56a.
The standard data such as the cost (time and cost) data about the test and its test items, the assembly cost data of the completed semiconductor device, and the analysis data of the test result information in the test result storage information DB 56c stored in A certain omitted test item is determined from the defective product rate data 56c2 for each test item of the test. More specifically, for a test item having a defective product rate lower than a predetermined reference value, the cost of reducing the test cost by omitting the test item and the wasteful product of the defective product caused by omitting the test item. Compare assembly cost and final test cost. Then, as a result, when it is determined that it is more cost-effective to omit the test item, it is determined to be omitted. Even if the test item is omitted, the test item may be carried out again due to changes in the conditions of the semiconductor wafer manufacturing process. At that time, it is necessary to carry out a monitor test as appropriate. Determine the content of the condition. The monitor condition content is, for example, the frequency of performing a predetermined monitor test, or the setting content such as executing the monitor test when the omitted test item exceeds a predetermined defective product rate in the final test process. .

Then, the control unit 51 stores the optimization information including the omission test item data determined as described above and the monitor condition information in the optimization information DB 56d. Then, the control unit 51 sends the created optimization information to the communication unit 55.
Test program management server 6 via LAN 4
Send to.

Next, the control unit 61 of the test program management server 6 receives the optimization information including the monitor condition information by the communication unit 62 as described above, and the distribution data DB
The data is stored in 63c (step S107), and this completes the optimization information creation process.

Next, the optimum test program creating process executed in the test program management server 6 will be described below with reference to the flowchart of FIG.

First, the control unit 61 of the test program management server 6 determines whether or not it is time to execute the optimization process of the test program, that is, whether it is time to generate the optimum test program, by using a predetermined condition. When it is determined based on the contents (step S201) and it is determined that it is time to generate the optimum test program (step S201: Yes)
In step S202, the process proceeds to step S202. On the other hand, the control unit 61
When it is determined that it is not the time to generate the optimum test program (step S201: No), the process returns and is repeated until the time comes. The control unit 62 determines whether it is the generation time or not, according to a predetermined time cycle or an artificial instruction by an operator or the like.

In step S202, the controller 61
Reads out the optimum test program generation program 63d and executes the optimized test program generation process based on the program 63d. In particular,
The control unit 61 firstly, based on the optimization information stored in the distribution data DB 63c, gives execution instructions for each test item excluding test items to be omitted from the test items included in the template data, and for each test item. Create an optimal test program that includes the test result collection and processing instructions.

Next, the control section 61 executes a monitor test program creating process for creating a monitor test program from the monitor condition information included in the optimization information and the template data according to the monitor test program generating program 63e. (Step S203). Here, the monitor test program is a program for causing the test apparatus 3 to appropriately check whether or not omission is appropriate for the test items omitted in the optimum test program.

Next, the control unit 61 of the test program management server 6 stores and stores the optimum test program in the optimum test program DB 63a and the monitor test program in the monitor test program 63b (step S204). Then, with this step S204,
The optimum test program creation process in the test program management server 6 ends.

Next, the program execution process executed in the test apparatus 3 by the program created in the optimum test program creation process (steps S201 to S204) will be described below with reference to the flowchart shown in FIG. .

First, the control unit 31 of the test apparatus 3 outputs a test start signal to the test program management server 6 based on, for example, an input of a test start instruction of a desired wafer test by an operator (step S301).

Control unit 6 of test program management server 6
In accordance with a test start signal of a desired wafer test output from the test apparatus 3, 1 indicates an optimum test program for the corresponding wafer test, a monitor test program corresponding to the optimum test program from the optimum test program DB 63a, and a monitor test. The optimization information is read from the program DB 63b, the optimization information is read from the distribution data DB 63c, and transmitted to the test apparatus 3 that has output the test start signal (step S302).

Next, when the control unit 31 of the test apparatus 3 receives the optimum test program, the monitor test program, and the optimization information, it temporarily stores them in the RAM of the control unit 31 (step S303).

Next, the control unit 31 determines whether or not the monitor test needs to be performed based on the optimization information and the like transmitted from the test program management server 6 (step S
304), if it is determined that the monitor test needs to be performed (step S304: Yes), step S3
If it is determined that the monitor test does not need to be performed (step S304: No), the process proceeds to step S08.
Move to 305.

Next, in step S305, the control section 31 activates the optimum test program and, in accordance with the optimum test program, the test apparatus main body 3
2. Control the test operation of 2. Specifically, the control unit 31
The test item X included in the optimum test program is executed in the test apparatus main body 32, then the test result information of the test item X is collected, and the collected test result information is temporarily stored in the RAM of the control unit 31. (Step S3
06).

Next, the control section 31 judges whether or not the tests of all the test items included in the optimum test program have been executed (step S307), and when it is judged that all the tests have been executed (step S307: If Yes), the process proceeds to step S311, and if it is determined that there is a test item that has not been executed (step S307: No),
The process returns to step S305.

In step S308, the control unit 31 of the test apparatus 3 controls the test apparatus main body 32 to execute the monitor test item (for example, the monitor test item Y) according to the monitor test program. Next, the test result information of the monitor test item Y is collected and temporarily stored in the RAM (step S309).

Next, the control section 31 judges whether or not all the monitor test items included in the monitor test program have been executed by the test apparatus main body 32 (step S310), and if it is judged that all have been executed (step S310). Step S310: Yes), the process proceeds to Step S311.
When it is determined that there is a test item that has not been executed (step S310: No), the process proceeds to step S308.

In step S311, the controller 31
Judges whether or not a predetermined test has been completed for all the semiconductor chips, and if it is judged that the test has not been completed (step S311: No), step S30
The process returns to step 4 and the subsequent processes are performed again. on the other hand,
When the control unit 31 determines that the test is completed (step S311: Yes), the test result information about all the semiconductor chips collected and temporarily stored in the test program in step S306 or step S309. The process is transmitted to the optimization server 5, and the operation of the program execution process ends at this step.

In the optimization information creating process, the optimization information is obtained based only on the result information of the test executed based on the optimum test program and the result information of the test executed based on the monitor test program. Is not always created, and may be created in consideration of the test result information of the final test process executed after the assembly process. Further, it goes without saying that not only optimization information is created based on the above-mentioned test result information, but also the test apparatus 3 and the test method are reviewed.

As described above, according to this embodiment, in the test process of the semiconductor wafer, according to the test result,
Since the contents of the optimum test program are automatically updated as appropriate so that the semiconductor chip and the semiconductor device can be manufactured most efficiently, the optimum semiconductor test can be easily realized.

The above embodiment is merely an example of the present invention, and can be appropriately modified. For example, the test content executed in the wafer test process is not limited to the above content. Further, the management device 2 has been described as having a configuration in which the test program optimizing server 5 and the test program managing server 6 share the functions, but even if it is one device or is connected via a network such as the LAN 4 or the like. It may be composed of a plurality of devices.

[0063]

According to the present invention, based on the test result data collected by the collecting means, the test items which can be omitted for all the semiconductor chips or for the semiconductor chips satisfying a predetermined condition are Determined by the determining means,
A test program for omitting the determined test item for all the semiconductor chips or for the semiconductor chips satisfying a predetermined condition is generated by the test program generating means, and the test program is transmitted to the semiconductor test device. Therefore, the more optimized test program can be automatically updated, and the optimized test program enables efficient and optimum semiconductor testing.

According to the second aspect of the present invention, the defective product occurrence rate for each test item is calculated by the defective product rate calculating means based on the test result data, and the calculated one test item Manufacturing cost increase based on defective product occurrence rate,
Since the test omission of the test item is calculated by the defective product rate calculation means based on the test cost of the test item, the test program of the semiconductor test should be optimized from the total semiconductor manufacturing cost. You can

Further, according to the invention described in claim 3, the optimization information creating means of the test program optimizing server creates optimization information for omitting the test of the test item determined by the determining means, This optimization information is transmitted to the test program management server by the optimization information transmission means, and the test program generation means of the test program management server generates the test program based on the transmitted optimization information. The creation of the optimization information and the creation of the test program are performed by different servers, which is suitable for optimization management of a test program for a large-scale semiconductor test, for example.

According to the fourth aspect of the invention, the timing determining means of the test program management server determines whether or not the preset test program generation time has come, and the test program generation time comes. In this case, since the test program is generated, the optimum test program can be automatically updated periodically.

According to the invention of claim 5, the template data creating means of the test program optimizing server creates the template data of the test program having the test contents of all the test items, and the created template data is The template data transmission means transmits the template data to the test program management server, the storage means of the test program management server stores the transmitted template data, and the test program creation means stores the template data stored in the storage means and the optimization information. Since the test program is created based on the above, it is not necessary to send and receive the program itself between the test program optimization server and the test program management server when optimizing, so it is easy to create the optimum test program. .

[Brief description of drawings]

FIG. 1 is a block diagram showing an overall structure of a semiconductor test system 1 of the present invention.

FIG. 2 is a block diagram showing an internal structure of a test program optimizing server 5 of FIG.

3 is a block diagram showing an internal configuration of a test program management server 6 of FIG.

FIG. 4 is a flow chart for explaining the operation of the optimization information creation processing of the semiconductor test system of the present invention.

FIG. 5 is a flowchart for explaining the operation of an optimization program creation process.

FIG. 6 is a flowchart for explaining the operation of program execution processing.

[Explanation of symbols]

1 semiconductor test system 2 semiconductor management device (management device) 3 semiconductor test device 4 LAN (communication line network) 5 test program optimization server 6 test program management server 51 control unit (collection means, determination means, optimization information creation means, Defective product rate calculation means, template data creation means) 55 Communication unit (transmission means, template data transmission means, optimization information transmission means) 61 Control unit (test program generation means, timing determination means) 62 Communication unit (transmission means) 63 Storage unit (storage means)

Claims (5)

[Claims] 1. A semiconductor test device for testing a plurality of test items on a semiconductor chip formed on a semiconductor wafer based on a test program, and a management device for managing the test program used in the semiconductor test device. Is a semiconductor test system connected via a communication network, wherein the management device collects test result data of a plurality of test items for the semiconductor chip, and the test results collected by the collecting device. Based on the data, a determination unit that determines an optional test item for all semiconductor chips or a semiconductor chip for which a predetermined condition is satisfied, and a test item determined by the determination unit for all semiconductor chips A test for generating a test program to be omitted for a chip or a semiconductor chip satisfying a predetermined condition. A test program generating means and a transmitting means for transmitting the test program generated by the test program generating means to the semiconductor test apparatus, and the semiconductor test apparatus performs a test according to the test program transmitted by the transmitting means. A semiconductor test system characterized by the above. 2. The semiconductor test system according to claim 1, wherein the determining means includes defective product rate calculating means for calculating a defective product occurrence rate for each test item based on the test result data. Based on the manufacturing cost increase based on the defective item occurrence rate of one test item calculated by the defective item rate calculating unit and the test cost of the test item, it is possible to determine the test omission of the test item. A characteristic semiconductor test system. 3. The semiconductor test system according to claim 1, wherein the management device includes a test program optimization server including the collection unit and the determination unit, the test program generation unit, and the transmission. A test program management server including means, the test program optimization server, optimization information creating means for creating optimization information for omitting the test of the test item determined by the determining means, Optimization information transmission means for transmitting the optimization information created by the optimization information creation means to the test program management server, wherein the test program generation means of the test program management server includes the optimization information transmission The test program is generated based on the optimization information sent by the means. Semiconductor test system to be. 4. The semiconductor test system according to claim 3, wherein the test program management server includes a timing determination means for determining whether or not it is a preset test program generation time, and the test program generation means. The semiconductor test system is characterized in that the test program is generated when the time determination means has reached the generation time of the test program. 5. The semiconductor test system according to claim 3 or 4, wherein the test program optimization server creates template data of a test program having test contents of all test items, and the template data creation. Template data transmission means for transmitting the template data created by the means to the test program management server, and the test program management server comprises storage means for storing the template data transmitted by the template data transmission means. The test program creating means creates a test program based on the template data stored in the storage means and the optimization information.