JP2000306395A - System and method for defect analysis of semiconductor as well as manufacture of semiconductor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a semiconductor device which is efficient and whose yield is high by judging whether a bit defect is generated frequently or no in every recognition region which is set with reference to the semiconductor device and analyzing the defect of the semiconductor device on the basis of information on the recognition region in which the judged bit defect is generated frequently. SOLUTION: A tester 2 sends a test signal to a prober 1, it receives a result signal from the prober 1, it judges whether every semiconductor device is good or not, and it outputs a judged result to an FBM output device 3. A defect sorting WS 4 processes data which is output from the FBM output device 3 at every touchdown. When an analysis request is used, an analysis WS 5 receives analysis preparatory data from the defect sorting WS 4 via a network 6. After a test in one lot portion is finished by the prober 1, the defect sorting WS 4 finishes an analysis preparatory operation in one lot portion after the elapse of the time in which an analysis preparatory processing operation is nearly one touchdown portion is performed. The analysis WS 5 analyzes a wafer which acquires fail bit data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor failure analysis system and method for analyzing failure of a semiconductor device having a storage element using a tester, and a semiconductor manufacturing method.

[0002]

2. Description of the Related Art Semiconductor devices are manufactured by repeating film formation, exposure, etching and the like. Since the processing dimensions of semiconductor devices are often smaller than 1 micrometer,
Due to small foreign matter, operation error of processing equipment, adjustment error, etc.
Insufficient processing accuracy can be maintained or abnormalities occur in the shape.
It becomes defective. Reducing the number of defective products is essential for increasing the productivity of semiconductor devices. For this reason, the cause of the defect is investigated, and measures are taken for each cause to improve the production yield of the product. In order to analyze the cause of a failure, it is important to accurately grasp the state of occurrence of the failure. One of the methods for grasping the cause of the failure is a method of fail bit analysis. In the test after the wafer processing, the operation state of the storage element is tested, particularly for a device having a memory function or a memory block in the device, and the occurrence position of an inactive element (hereinafter, referred to as a fail bit) is detected. The data is recorded and the failure phenomenon is grasped and the cause of the failure is analyzed based on the data (prior art 1: JP-A-61-243378). Here, fail bit data is collected for each wafer, and failure mode classification is performed in advance according to the distribution of the fail bits on the wafer.
By providing the result to the user, the user analyzes the cause of the failure of the semiconductor device. The failure mode classification refers to, when fail bits are arranged in a certain pattern (for example, a straight line), recognizing the failure bits and determining that the corresponding wiring has an abnormality. Also, the frequency of judging that they are arranged in the same kind of pattern is counted.

On the other hand, in order to improve the efficiency of the fail bit analysis, a parallel processing technique has been devised which makes the time required for collecting fail bit data seemless (prior art 2: Hitachi Electronics Engineering, Ltd.). Technical report 1997.77 NO14P10-P14). As a result, during a normal test, a workstation (hereinafter referred to as W) that acquires fail bit data and analyzes them.
The data can be transferred to S). This has made it possible to efficiently collect fail bit data.

[0004]

However, in order to enable the user to perform the analysis efficiently, it is necessary to perform a process such as a failure mode classification during a normal test. However, conventionally, for each generated fail bit pattern,
Since the distribution shape is recognized, the failure mode classification time becomes longer depending on the number of failures in which failure has occurred. First, the time when the failure mode classification takes time will be described. Normally, when a wiring is broken due to adhesion of a foreign substance or the like, a corresponding bit string in a wiring shape becomes defective. In such a case, disconnection or the like occurs as much as the number of adhered foreign substances, but the number of foreign substances adhering to the wafer in a controlled clean room is about several tens and is not so large (Reference: N).
EC Technique Vol. 50 No6 / 1997 p66 ~
p67).

[0005] Defects due to disconnection of wiring due to foreign matter cause line defects and area defects, but these only occur on the wafer at most about one hundred, and the time required for recognizing the generated defect pattern is at most one. This is about one hundred times the time required to recognize one pattern. If the foreign matter is small, only one bit may be defective, but the situation remains the same. When targeting such defects, the load may be estimated by setting the number of defects occurring on the wafer to be slightly larger, such as 500 or 1000.

On the other hand, when a failure occurs in the transistor formation process or the capacitor formation process of the memory portion, a failure in which the transistor or the capacitor does not operate may occur randomly in the chip. If these become defective due to minute foreign matter or defects in the silicon crystal, a defect of only one bit may occur. If there is no other defective bit around this defective bit, it is an isolated point defect. However, for example, in a 64M DRAM, there are 60 capacitors.
Since there are more than one million, if the processing accuracy decreases in such a process, the number of bit defects may increase to several hundred thousand or several million. Conventionally, searching for a classification pattern that applies to each of these fail bit distributions requires a long processing time depending on the number of generated fail bits, and is several million times longer than the time required to recognize a single isolated point defect. That would be. Therefore, the defect classification requires a processing time depending on the number of generated defects, and the fluctuations are extremely large. It is extremely uneconomical to design a system by setting a large load in advance for a defect having a large fluctuation in the number of occurrences.

[0007] When it is impossible to predict when the failure mode classification will end, and because the time of failure mode classification is not constant in system design, data collection and data analysis from a tester must be performed between them. And so on must be a separate processing process with buffering means. Therefore, even if the data from the tester can be efficiently collected as in the prior art 2, the failure mode classification is an off-line process that is not linked to the measurement work of the tester. The analysis itself had to be offline.

[0008] An object of the present invention is to solve the above problems.
It is an object of the present invention to provide a semiconductor failure analysis system and method capable of performing failure analysis by enabling acquisition of all fail bit data of a desired semiconductor device without hindering a test in mass production. Also,
Another object of the present invention is to provide a semiconductor manufacturing method that accurately grasps the number of occurrences of bit failures and appropriately performs a failure countermeasure on a production line, thereby realizing efficient and high-yield semiconductor device production. To provide.

[0009]

SUMMARY OF THE INVENTION In order to achieve the above object, according to the present invention, a failure occurrence measurement is always performed by a tester by efficiently recognizing a bit frequent failure and keeping the time required for failure mode classification constant. The operation is synchronized with the processing time of the failure mode classification and the like, so that not only the collection of the fail bit data but also the time required for the failure mode classification is apparently reduced. The present invention also provides a tester for acquiring fail bit data from a semiconductor device, a physical conversion for receiving the fail bit data acquired by the tester and rearranging the semiconductor device in the layout order, and performing the physical conversion. Based on the failed bit data, it is determined whether or not a bit failure occurs frequently for each recognition area set for the semiconductor device,
An analysis means for analyzing a failure of the semiconductor device based on the information of the recognition area where the determined bit failure occurs frequently is a semiconductor failure analysis system.

Further, according to the present invention, there is provided a tester for obtaining fail bit data from a semiconductor device, and a physical conversion for receiving the fail bit data obtained by the tester and rearranging the same in the layout order of the semiconductor device.
Based on the fail bit data on which the physical conversion has been performed, it is determined whether or not a bit failure occurs frequently for each recognition area set for the semiconductor device. Analysis means for counting the number of recognition areas that are present and analyzing the failure of the semiconductor device based on information on the number of recognition areas in which the counted bit failures occur frequently. System. The present invention also provides a tester for acquiring fail bit data from a semiconductor device, a physical conversion for receiving the fail bit data acquired by the tester and rearranging the semiconductor device in the layout order, and performing the physical conversion. Based on the determined fail bit data, each of the recognition areas set for the semiconductor device is classified into at least an area defect and a bit frequent defect, and information on the categorized area defect and the bit frequent defect recognition area. And a analyzing means for performing a failure analysis of the semiconductor device based on the above.

The present invention also provides a tester for obtaining fail bit data from a semiconductor device, and a physical conversion for receiving the fail bit data obtained by the tester and rearranging the data in the layout order of the semiconductor device.
Based on the fail bit data subjected to the physical conversion, at least a region defect, a bit frequent defect, a line defect, an adjacent defect, and an isolated point defect are classified for each recognition region set for the semiconductor device. A semiconductor device comprising: analysis means for performing a failure analysis of a semiconductor device based on information on a recognized region between a classified region defect and a bit-frequent defect and information on a line defect, an adjacent defect, and an isolated point defect. It is a failure analysis system. The present invention also provides a tester for acquiring fail bit data from a semiconductor device, a physical conversion for receiving the fail bit data acquired by the tester and rearranging the semiconductor device in the layout order, and performing the physical conversion. Based on the failed bit data, classified into at least an area defect, a bit frequent defect, a line defect, an adjacent defect, and an isolated point defect for each recognition area set for the semiconductor device,
A drawing process is performed so that information on the classified failure mode can be displayed. Further, based on the information on the recognition area of the classified area failure and the bit-frequent occurrence failure, and on the information of the line failure, the adjacent failure, and the isolated point failure, An analysis means for performing a failure analysis of the semiconductor device.

According to the present invention, the analysis means of the semiconductor failure analysis system is characterized in that the sum of the processing time from data reception processing to physical conversion, failure classification, and drawing preparation is the time required for each touchdown of the prober in the tester means. It is characterized in that it is configured as follows. Further, the present invention is characterized in that the analysis means of the semiconductor failure analysis system is configured to correct the number of occurrences of bit failures such as isolated point defects by recognizing a region where bit failures occur frequently. And Further, the present invention provides an obtaining step of obtaining fail bit data from a semiconductor device using a tester means, and receiving the fail bit data obtained in the obtaining step using an analyzing means, and arranging the semiconductor device in the layout order of the semiconductor device. The physical conversion to be performed is performed, and it is determined based on the failed bit data that has been subjected to the physical conversion whether or not a bit failure occurs frequently for each recognition area set for the semiconductor device. An analysis step of performing a failure analysis of the semiconductor device based on information of a recognition area in which bit failures frequently occur.

Further, the present invention provides an acquisition step of acquiring fail bit data from a semiconductor device using a tester means, and a step of receiving the fail bit data acquired in the acquisition step using an analysis means. A physical conversion for rearranging in the layout order is performed, and based on the fail bit data on which the physical conversion has been performed, it is determined whether or not a bit defect frequently occurs for each recognition area set for the semiconductor device. An analysis step of counting the number of recognized areas in which the determined bit defects occur frequently, and performing a failure analysis of the semiconductor device based on information on the number of recognized areas in which the counted bit defects occur frequently. This is a semiconductor failure analysis method. Also, the present invention
An acquisition step of acquiring fail bit data from a semiconductor device using a tester means, and a physical conversion for receiving the fail bit data acquired in the acquisition step and rearranging the layout order of the semiconductor device by using an analysis means, Based on the fail bit data on which the physical conversion has been performed, each of the recognition areas set for the semiconductor device is classified into at least an area defect and a bit frequent defect. An analysis step of performing a failure analysis of the semiconductor device based on the information of the recognition area of the semiconductor device.

Further, the present invention provides an acquiring step of acquiring fail bit data from a semiconductor device using a tester means, and receiving the fail bit data acquired in the acquiring step using an analyzing means, Physical conversion for rearranging in the layout order is performed, and at least an area defect, a bit frequent defect, a line defect, and an adjacent defect are determined for each recognition area set for the semiconductor device based on the fail bit data subjected to the physical conversion. An analysis step of classifying the semiconductor device into isolated point defects and performing a failure analysis of the semiconductor device based on the information on the recognized area between the classified area defect and the bit-frequent occurrence defect and the information on the line defect, the adjacent defect, and the isolated point defect; And a semiconductor failure analysis method. Further, the present invention provides an obtaining step of obtaining fail bit data from a semiconductor device using a tester means,
By using the analysis means, the fail bit data obtained in the income step is received, a physical conversion for rearranging in the layout order of the semiconductor device is performed, and the semiconductor device is subjected to the physical conversion based on the failed bit data. For each of the set recognition areas, at least an area defect, a large number of bit failures, a line failure, an adjacent failure, and an isolated point failure are classified, and a drawing process is performed so that information on the classified failure mode can be displayed. An analysis step of performing a failure analysis of a semiconductor device based on information on a recognized area between a classified area failure and a bit-frequent occurrence failure and information on a line failure, an adjacent failure and an isolated point failure. It is an analysis method. Further, the present invention is a method for manufacturing a semiconductor, comprising manufacturing a semiconductor device using the semiconductor failure analysis system. Further, the present invention is a method for manufacturing a semiconductor device, wherein a semiconductor device is manufactured while quality control of a semiconductor manufacturing line is performed based on a change in the number of bit defects obtained using the semiconductor defect analysis system.

According to the configuration described above, a recognition area divided for each chip or divided within a chip is set,
Since each recognition area is classified at least into "area failure" and "bit frequent failure", all fail bit data of a desired semiconductor device (semiconductor wafer) can be obtained without hindering a test in mass production. And a failure analysis can be performed. Further, according to the above configuration, a recognition area divided for each chip or in a chip is set, and each recognition area is classified at least by "area failure" and "bit frequent failure". The number of occurrences of defects can be accurately grasped, and as a result, a measure against a defect in a production line can be taken accurately, and an efficient and high-yield semiconductor device (semiconductor wafer) can be manufactured.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a semiconductor failure analysis system and method according to the present invention and a semiconductor manufacturing method will be described with reference to the drawings. First, FIG. 1 shows a system configuration as an embodiment of a semiconductor failure analysis system according to the present invention. The system includes a tester 2 having a prober 1, a fail bitmap (hereinafter simply abbreviated as FBM) output device 3 connected to the tester 2, a failure classification workstation (hereinafter, workstation is abbreviated as WS) 4, It is composed of an analysis WS5, an FBM output device 3, a failure classification WS4, and a network 6 connecting the analysis WS5. A so-called prober 1 is connected to the tester 2, and a wafer to be tested is set to the prober 1,
Perform the test. The tester means of the present invention comprises the tester 2 and the FBM output device 3, and the analyzing means of the present invention comprises the defect classification WS4 and the analysis WS5.
It is constituted by. Since the tester 2, the FBM output device 3, the defect classification WS4, and the analysis WS5 are so-called information processing devices, some or all of them are processed by one information processing device, or information different from the embodiment is used. The processing may be performed by a processing device. It is also possible to use a so-called bus connection instead of a network connection. Needless to say, the type and name of the WS are not limited, and the type and name are not limited as long as equivalent functions such as a PC and a server are realized. The structure described in this embodiment is merely an example.

FIG. 2 shows the configuration of the defect classification WS4. The WS 4 is connected to the network 6 and includes a processing device 41 including a CPU, an external storage device 42, an output device 43 including a display device, a keyboard, a mouse, a recording medium, and the like. It comprises an input device 44 and the like. The tester 2 sends a test signal to the prober device 1 and receives a result signal from the prober device 1 to determine the quality of each semiconductor device. At this time, the FBM output device 3 does not discard the pass / fail information of each storage element 1 and outputs it to the outside while other test items are being executed. The details are described in “Hitachi Electronics Engineering Technical Report 1997.7 NO14 P10 to P14”. That is, the FBM output device 3 is configured by a memory or the like for writing the fail data generated by the tester 2 in real time. The memory has the same size as the number of simultaneously measured target devices. The connection with the tester 2 is connected by a dedicated cable, and the fail data of the simultaneous measurement number can be taken in at the same time. That is, fail data generated in the test execution (in the case of a failure in the test device quality determination, a defective address is regarded as fail data) is loaded into the memory in real time.

By the way, the timing of outputting from the FBM output device 3 to the outside (in this case, the defect classification WS) can be considered for each lot, each wafer, every touchdown of the prober, and the like. The term “each prober touchdown” means that a plurality of chips can be tested simultaneously by a single needle application (touchdown) in the prober apparatus 1. That is, transmission / reception processing is performed for each destination (touchdown). When only one chip is measured by one touchdown, data transmission / reception is performed for each chip. If performed every prober touchdown, the data buffer used for data transmission and reception can be small, and the data transfer is performed little by little, so the network load can be small.
There are advantages such as.

In the following embodiment, in each touchdown, FB
A case where a fail bit test result is output from the M output device 3 will be described. FIG. 3 shows an output format transferred from the FBM output device 3 to the defect classification WS4. In this format, the following items are described. Product name, lot number, wafer number, tester number, prober number, number of chips to be tested in touchdown (number of chips in touchdown), number of measured chips actually tested, position (X, Y) for each chip (chip (Position X, chip position Y), a category assigned by a tester for each chip (for example, category division corresponding to all bits defective, all bits good, etc.), and a file name storing fail bit data. The process from the position (X, Y) for each chip to the file name storing the fail bit data is repeated by the number of chips tested. Also, this repetition does not exceed the number of chips tested in touchdown. When a predetermined item related to the chip tested by one touchdown is described, a message (EOF) indicating the end of the file is described. The fail bit data for each chip is stored in a file given by the file name storing the previously described fail bit data. Since it is often represented by so-called binary data, it is preferable that the file be separated from a file containing character information.

The message sent from the tester 2 to the FBM output device 3 has the same contents. Note that tester 2 is connected to prober 1.
Is sent only the test results. Since the tester itself manages information such as the product type name, lot number, tester number, prober number, and the position of the tested chip, FIG.
Can be completed. Data output from the FBM output device 3 for each touchdown is subjected to the processing shown in FIG. The process at this stage is referred to as analysis preparation S41. This is because, when providing the FBM data collected from the tester 2 to the staff analysis, when the failure classification WS4 receives the data, the processing unit 41 in the failure classification WS4 performs the failure mode classification and the failure even if there is no analysis request from the staff. This is step S41 in which necessary processing such as drawing processing is performed in advance. By providing this analysis preparation step S41, for example, the analysis request S
At the time of receiving 42, the failure mode classification and the drawing process have been completed, and the process S43 of outputting the processed data to the output device 43 such as a display device can be performed immediately. Analysis WS5
Issues an analysis request and returns from the failure classification WS4 to the network 6
There is an advantage that the analysis preparation data is received via the PC and the analysis can be immediately started. In addition, systematically, the processing device 41 automatically processes the data received from the FBM output device 3, so that there is no need to have an unnecessary buffer.

Next, the contents of the analysis preparation S41 will be described in detail with reference to FIG. First, the processing device 41 executes step S4
At 11, the test result is received from the FBM output device 3 via the network 6 in the format shown in FIG. Thereafter, the processing device 41
Reads the test results (good / bad information for each bit) from the storage device 42 and rearranges them from the test order of the tester to the actual layout order and stores them in, for example, the storage device 42. This rearrangement is hereinafter referred to as physical conversion (S412). Here, if the good bit is described as "0" and the bad bit is described as "1", it can be handled as so-called binary data on the processing device 41 comprising a CPU, which is simple. Furthermore,
After the physical conversion, the processing device 41 performs a failure mode classification process (S413). The failure mode classification is to extract the distribution of fail bits classified in a specific form. Here, as the failure mode classification, “region failure”, “bit occurrence failure”, “X-direction line failure”,
"Y direction line defect", "adjacent defect", "isolated point defect"
For example, and stored in the storage device 42, for example. By classifying in this way, for example, in the case of “line failure in the X direction”, the cause of the failure is not that each transistor constituting the line has failed one by one,
/ O part can be estimated, and if "area failure" in which fail bits are distributed more than a certain rate in a specific area, it can be determined that the whole area operates or a failure of a part that controls I / O occurs. "Y direction line defect" also "X direction line defect"
In the same way as above, "isolated point failure" is considered to be a failure due to individual crystal defects or transistor operation failure, and "adjacent failure" is a candidate for failure cause such as short-circuit between elements or insufficient isolation of elements. Can be considered. by the way,
The “multiple bit failures” are different from the “isolated point failures” due to individual crystal defects or transistor operation failures, and must be recognized separately. In addition, since there is a different cause from “area failure”, it is necessary to distinguish between the two. In any case, by classifying the distribution of the fail bits in the failure classification WS4, for example, it is possible to associate a failure phenomenon estimated as a cause for each classification pattern in the analysis WS5. Therefore, what kind of failure phenomenon is on the wafer
The frequency of occurrence can be clarified, and information that is extremely effective for performing failure analysis can be obtained.

Thereafter, the processing device 41 executes the drawing process (S4
Perform 14). In the drawing processing, the distribution on the wafer is displayed on the display device of the CRT 43 or the like or the analysis WS5 based on the good / bad data of the fail bit test result stored in the storage device 42, or stored in the storage device 42. As a result of the failure mode classification, a list of the number of failures
This is processing related to display on the display device of the RT 43 and the analysis WS 5. Further, it is a process related to the output display of the analysis as described below. In short, the drawing process is a process that enables information about the classified various failure modes to be displayed on the display device. When the processing device 41 receives a message (wafer-end) notifying that the fail bit test has been completed for one wafer (S415), the wafer ending process (S416)
At this stage, the data of the analysis preparation processing is stored in the storage device 42 in wafer units. The wafer end process (S416) in the processing device 41 is a process of summarizing the processes performed on the fail bit test result for each touchdown with respect to the wafer. Then, the procedure shifts to preparation for receiving a fail bit test result of the next wafer.

When the processing device 41 receives a message (lot-end) indicating that all the wafers in the lot subjected to the test have been tested (S417), it performs a lot end process (S418). At this stage, the data of the analysis preparation processing is stored in the storage device 42 in lot units. Processing device 41
In the lot end process (S418), preparations are made to move to the next lot process, such as clearing the lot number and product name of the lot. The FBM output device 3 sends a message indicating the end of measurement of the same lot to the analysis WS5. Here, analysis preparation processing in the failure classification WS4 (S41)
As the receiving process (S411), the physical conversion (S411)
412), failure mode classification (S413), and drawing processing (S
414) and four processes are performed. At this time, as shown in FIG. 6, the sum of the processing time of the analysis preparation processing of the data obtained in each touchdown (each of the first to nth touchdowns) is within the test time for each touchdown of the tester 2. The data processing (analysis preparation processing) necessary for the test and the fail bit analysis can be performed in synchronization with each other. In the defect classification WS4, after the test for one lot is completed by the prober, the time for performing the analysis preparation processing for approximately one touchdown elapses, and then the analysis preparation work for one lot ends. Thereafter, in the analysis WS5, analysis can be performed on the wafer for which the fail bit has been acquired.

The fact that the measurement of the tester can be performed in synchronization with the analysis of the fail bit means that a desired number of wafer fail bit maps can be obtained without reducing the operation rate of the tester. It is very effective in monitoring and analyzing the cause. Conversely, considering the case where the above data processing does not end within the touchdown of the tester, the more fail bits are measured, the more data processing is not completed, the more piles of data processing are finished, Not only can the data not be provided to analyze the cause, but it may be buffered unprocessed in the analysis system and cause a system failure. Therefore, in constructing an analysis system, it is important to complete data processing within the measurement time for each touchdown of the tester.

In the physical conversion process (S412), the amount of data in one chip is fixed for each product type, and the content of the conversion process is also fixed for each product type. Therefore, the processing device 41
By using a high-speed processor or using parallel computing, it is possible to make the processing time sufficiently short. Also in the drawing process (S414), the data amount in one chip is fixed, and the data format used for display is also fixed, so that the processing content is fixed. Therefore, the processing device 4
The processing time can be made sufficiently short by using a high-speed processor or using parallel calculation as 1. However, for the failure mode classification process (S413), it is impossible to predict how many failures have occurred at the time of system design, so that the load cannot be predicted and the system design is difficult. is there. If the load is estimated to be relatively large, for example, in order to secure the necessary computing capacity by parallel processing, an excessive number of CPUs are required. This undesirably increases the cost of manufacturing the system.

Therefore, in the present invention, a method for reducing the dependence of the processing time of the failure mode classification processing (S413) on the number of failure occurrences is created. Enabled to be short enough. The cause of changing the processing time of the failure mode classification is a case where "a bit failure" occurs as shown in FIG. Therefore, we created a method to analyze the "bit failure mode" within a certain time.

First, in the processing unit 41, as shown in FIG. 7, several recognition areas are set for each chip. This recognition area may be the whole one chip,
The area inside the chip may be equally divided into 1/4 or 1/8. When setting the recognition area, the recognition area can be set for the processing device 41 by displaying the image of each chip on the display device 43 and specifying it on the screen. At this time, if the CAD data relating to the semiconductor wafer is obtained from the tester 2 via the network 6 and displayed on the display device 43, for example, the recognition area such as the memory area in the chip, the peripheral circuit area, etc. Can be set for each type of circuit.

FIG. 8 shows a procedure for classifying defects in the processing device 41. Based on the defective bit data that has been physically converted in the physical conversion processing step (S412), the number of fail bits (F
N (y)) is counted (step S81). Next, the number of fail bits (FN (x)) arranged on the x-th line in the Y direction from the left is counted (step S8).
2). Using FN (x) and FN (y), the total number of fail bits (FNtotal) in the recognition area is counted (step S83). This FNtotal is a constant value FNc
If it is equal to or more than onst (step S84), the recognition area is determined to be “area failure” (step S85), and data of the area failure and the coordinates of the recognition area are stored in the storage device.

If the value of FNconst is set small, the processing can be completed in many cases without passing through the following recognition means. Therefore, the processing time itself is shortened. If the total number of bits exceeds FNcont, the presence of a line defect is overlooked and an area defect occurs, so that FNconst cannot be made so small. In practice, about 10% of the total number of bits in the recognition area will be appropriate. Next, when it is not determined in step S84 that the area is defective, a determination is made as to “frequent occurrence of bits” for each of the set recognition areas (step S8).
6). This part is a part where the data amount dependence of the processing is large and the processing time is extremely long unless an appropriate algorithm is used. Details of the processing will be described later.
If the criterion of “bit occurrence failure” is satisfied, it is named “bit occurrence failure” (step S87) and stored in the storage device 42 together with the recognition area coordinates. Next, when it is not determined in step S86 that the bit is frequently occurring, it is determined whether or not fail bits are arranged on the X-direction line for each of the recognition areas (step S88). Those satisfying this are determined as “X-direction line failure” (step S
89), and store it in the storage device 42 together with the coordinates of the X direction line.

Next, it is determined whether or not fail bits are arranged on the Y-direction line for each of the recognition areas (step S9).
0). Those satisfying this are determined as “Y-direction line failure” (step S91), and are stored in the storage device together with the coordinates of the Y-direction line. Next, it is determined whether or not adjacent bits are defective for each recognition area (Step S).
92). Those satisfying this are determined as "adjacent defects" (step S93), and the storage device 4 stores the position coordinates of the adjacent defects.
Store it in 2. Finally, an “isolated point defect” is determined for each of the above-described recognition areas, and the position coordinates of the isolated point defect are stored in the storage device 4.
Store it in 2. "Isolated point failure" is defined as an isolated point when there is no other fail bit around the relevant fail bit (step S94). Here, "surrounding" is defined. If it is appropriately set, for example, around 5 bits or around 10 bits according to a product or a process, those that satisfy this are defined as isolated point defects (step S9).
5).

If it does not belong to any of the above, it is determined to be other (step S96), and the storage device 42 together with its position coordinates
To memorize. Here, in steps S81 and S82, a process of counting the number of fail bits for each set recognition area and for each line is included. The number of lines is set for each type of analysis target and for each type. Since it is determined by the recognition area, the calculation amount can be predicted in advance. Further, the calculation amount for a specific type is almost constant.

Next, at step S86, "Bit failure"
Will be described with reference to FIG. First, the processing device 41 calculates the X calculated for each recognition area as described above.
A histogram (FIG. 10) is created for the direction fail bit number FN (x) (step S861). This histogram shows the frequency of appearance (the number of lines that appeared) with respect to the number of fail bits (FN (x)) in the line for each recognition area. Next, the processing device 41 obtains a threshold value Thx for each of the set confirmation areas based on the following (Equation 1) (step S862). Thx = √ ((M / N) FNtotal) (Equation 1) where M is the number of bits in the y direction in each recognition area,
N is the number of bits in the x direction in each recognition area. F
Ntotal is calculated in step S83.

Next, the processing device 41 counts the number of fail bits FNx equal to or smaller than Thx in the histogram (step S863). The reason why the number of fail bits FNx equal to or smaller than Thx is counted in the above histogram is that ThN
This is because a value of x or more is determined as “area failure”. Then, the processing device 41 determines whether or not FNx / Fntotal is equal to or more than a desired value (Th) (the lower limit in the X direction for determining that there is a frequent bit failure) (step S).
864). If FNx / Fntotal is the desired value (Th)
In the following cases, the process proceeds to step S88 without determining that the bit is frequently occurring. Here, M and N appearing in the expression (1) are the numbers of bits in the Y direction and the X direction in the recognition area, respectively, as shown in FIG. Therefore, FNtota
l does not exceed M × N. Thx is 0 to M
And Thy takes a number from 0 to N.

The processing device 41 creates a histogram for the number of fail bits FN (y) in the Y direction calculated for each recognition area as described above by the same processing (step S865). Next, the processing device 41 obtains the threshold value Thy for each of the set confirmation areas based on the following (Equation 2) (step S866). Thy = √ ((N / M) FNtotal) (Equation 2) where M is the number of bits in the y direction in each recognition area,
N is the number of bits in the x direction in each recognition area. F
Ntotal is calculated in step S83.

Next, the processing device 41 counts the number of fail bits FNy equal to or less than Thy in the histogram (step S867). And the processing device 41
Is determined whether FNy / Fntotal is equal to or greater than a desired value (Th) (the lower limit value in the Y direction for determining the occurrence of multiple bits failure) (step S868). If FNy /
If Fntotal is equal to or smaller than the desired value (Th), the process proceeds to step S88 without determining that the bit is frequently occurring. As described above, FNx / Fntotal and FNy
If both / Fntotal are equal to or greater than Th, it is determined to be "bit multiple failure" (step S867), and is stored in the storage device 42 together with the coordinates of the recognition area. According to such a method, the processing device 41 such as a CPU can recognize the “bit multiple occurrence failure mode” within a fixed time without depending on the number of generated fail bits.

Therefore, the relationship between the capacity of the computational resources 41 used for processing and the processing time does not largely depend on the generated data. That is, even if bit failures occur frequently, the processing time can be made substantially constant. Therefore, it is possible to set the computer resources 41 necessary for incorporating these recognition processes within the touchdown time. Specifically, the number of CPUs for performing parallel processing in the processing device 41 can be determined. By doing so, FBM measurement and analysis preparation can be performed in parallel. As a result, even if the FBM data is incorporated into a normal product characteristic test, the analysis results can be smoothly provided without accumulation of measurement results waiting for analysis preparation.

If one analysis system according to the present invention is installed for each prober in the test process, acquisition of fail bit data of all product wafers and preparation for analysis can be performed.
It can be performed without disturbing mass production tests. Of course, the analysis resources may be connected by a network, a bus, or the like to share computation resources, data management resources, and the like. If this is possible, it is easy to compare the inspection result of the foreign substance inspection and the appearance inspection during the manufacturing process with the fail bit data. However, conventionally, in order to collect fail bit data, a target wafer is extracted and measured after a mass production test is completed. According to the present invention, the fail bit data of all the wafers is automatically collected, so that it is not necessary to extract and test the wafer of interest. In addition, connecting this analysis system to some probers is sufficiently significant. In this case, a lot for which the data of the foreign substance inspection or the appearance inspection is to be compared with the data of the fail bit may be tested by a prober to which the present system is connected.

As described above, if the "multiple bit failure mode" can be recognized in the failure classification WS4, it is advantageous in performing the analysis in the analysis WS5. That is, in the failure classification WS4, the FBM output device 3
Test result (good / bad information for each bit) received from
Is subjected to a physical conversion process in step S412, and the fail bit data subjected to the physical conversion process is set in a chip unit set for each chip in step S413 or for each recognition area subdivided in the chip, Failure classification processing such as “area failure mode”, “bit multiple failure mode”, “X direction line failure mode”, “Y direction line failure mode”, “adjacent failure mode”, and “isolated point failure mode” is performed. , Sequential wafer units,
Further, the data is stored in the storage device 42 in lot units. In step S414, since the rendering preparation processing is performed on the failure classification data and stored in the storage device 42, the failure classification data can be displayed on the display device 43, and the network 6 can be connected to the analysis WS5. By providing the information via the display, the analysis WS5 can also display and output the information on the display device.

As described above, in the defect classification WS4, the “area defect mode” is set for each recognition area subdivided into chips or each chip set for each chip.
Since failure classification processing such as “bit multiple failure mode”, “X-direction line failure mode”, “Y-direction line failure mode”, “adjacent failure mode”, and “isolated point failure mode” has been performed, analysis WS5 In advance, if a defect phenomenon estimated as a cause is associated and taught in advance for each classification pattern, when the defect classification processing data is provided, analysis is performed for each classification pattern, and the cause is estimated as a cause. It is possible to find out the defective phenomenon to be performed. In any case, the analysis WS5 determines the defect classification W
Since the defect classification data for each recognition area in the chip from S4, particularly the area defect data and the bit frequent defect data can be provided in units of wafers or lots, an alarm is immediately displayed in units of wafers or lots. The output means can be used to take measures to eliminate the cause of the failure in the semiconductor manufacturing process, thereby improving the yield of semiconductors. In particular, if it is classified as “area failure”, the analysis WS5
It is possible to analyze the operation of the entire area and the failure of the part that controls the I / O, and as a result, the cause of the occurrence can be easily estimated. In addition, "bit multiple failure" is a defect different from "isolated point failure" due to individual crystal defects and transistor operation failure, and is also a different cause from "region failure". can do. As a result, when estimating the cause of the defect in the analysis WS5, the accuracy can be improved.

By discriminating and classifying “frequent bit failures” into “area failures”, “adjacent failures”, and “isolated point failures” as described above, it is possible to classify erroneously or without sorting. As a result, it is possible to immediately find out the lack of uniformity of the processing in the process, which is the true cause of the "frequent occurrence of defective bits", without spending more time than necessary. . In other words, by setting “frequent bit failures” as a new classification pattern, it is possible to improve the correspondence between the classification result of the failure mode classified by the failure classification WS4 and the estimation of the cause of the failure in the analysis WS5. First, when managing the transition of defective bits on a wafer, if there are many defective bits in the past, the number will be several hundred thousand or several million as described above. Since the normal isolated point failure occurrence level is about several hundreds, it is meaningless to put the failure bit occurrence numbers on those wafers on the same control chart or transition chart. Therefore, when a bit failure occurs, the data of the corresponding wafer is deleted from the control chart and the transition chart, and when calculating various statistics (average, standard deviation, etc.), it is not included in the calculation. In this way, the decision to exclude from management and analysis was arbitrary or made without clear criteria, so the results of the processing could not be said to be sufficiently reliable.

Therefore, this time, based on the above-mentioned clear criteria, the defect classification WS4 recognizes the bit frequent defect mode and corrects the number of isolated point defects (the number of bit defects). As a result, for example, the analysis WS5 receives the data of the bit frequent failure mode or the like from the failure classification WS4 via the network 6 to thereby provide, for example, a transition diagram (for a lot unit or a wafer unit) as shown in FIG. (The transition of the number of occurrences of bit defects). By the way, as shown in FIG. 13, even if one-bit defects caused by crystal defects, minute foreign matter, and the like increase from a normal level and happen to overlap with such frequent occurrences of bit defects, they are separately generated for each recognition area. Since it is classified into “bit occurrence failure” and “isolated point failure”, it is possible to prevent the user from being overlooked. In this method, in the analysis WS5, it is possible to detect a case where the number of 1-bit defects caused by crystal defects, minute foreign matters, and the like is increased in an area other than the area where the multiple bit failure occurs. In such a case, it is important to review the management standards and inspection methods for crystal defects at the time of acceptance, and to investigate the cause of the generation of minute foreign matter.

In the analysis WS5, it is also possible to manage the number of areas where bit failures occur frequently. This can be managed, for example, with the transition diagram of FIG.
When bit failures occur frequently, so-called remedy is impossible in many cases (the number of redundant lines is insufficient), so that the defective products are directly replaced with defective products. Therefore, the fact that there are many chips in which bit failures occur frequently means that the number of chips to be paid out is reduced. This is inconvenient in various aspects, such as securing profits or meeting customer delivery dates, so it is necessary to take prompt measures. In the case of the frequent occurrence mode of the bit failure, the cause often occurs in the transistor forming step and the capacitor forming step, and it is important to review the process. As described above, the output of the fail bit data from the tester 2 and the following processing unit are performed for each touchdown. However, the same embodiment as described above can be realized also for each wafer. However, since data is generated in bursts for each wafer, the network 6 needs to have a transfer capability capable of withstanding the data. Further, the analysis by the user in the analysis WS5 becomes possible after the processing time of substantially one wafer has elapsed since the end of the fail bit measurement in the tester 2.

[0043]

According to the present invention, a recognition area divided for each chip or within a chip is set, and each recognition area is classified at least by "area failure" and "bit frequent failure". Therefore, it is possible to obtain all the fail bit data of a desired semiconductor device without hindering a test in mass production, and to perform a failure analysis. According to the present invention, a recognition area divided for each chip or divided within a chip is set,
Since each recognition area is classified into at least “area failure” and “bit frequent failure”, the number of occurrences of bit failure can be accurately grasped. As a result, a failure countermeasure for a production line can be accurately taken. This makes it possible to manufacture an efficient and high-yield semiconductor device.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram showing one embodiment of a semiconductor failure analysis system according to the present invention.

FIG. 2 is a configuration diagram illustrating an example of a defect classification WS illustrated in FIG. 1;

FIG. 3 is a diagram for explaining a format of data output from the tester shown in FIG. 1;

FIG. 4 is a diagram for explaining a macro procedure performed by the defect classification WS and the analysis WS shown in FIG. 1;

FIG. 5 is a view for explaining a processing procedure of an analysis preparation part to be processed by the defect classification WS shown in FIG. 1;

FIG. 6 is a diagram for explaining synchronization between a tester and a defect classification WS.

FIG. 7 is a schematic diagram illustrating an example of a bit frequent failure.

8 is a diagram for specifically explaining the procedure of the defect classification process shown in FIG.

FIG. 9 is a diagram for specifically explaining a procedure of judging a frequent bit failure shown in FIG. 8;

FIG. 10 is a diagram showing a histogram relating to the number of fail bits for each line used for determination of a bit frequent failure;

FIG. 11 is a diagram showing the size of a recognition area.

FIG. 12 is a diagram showing a transition regarding the number of occurrences of bit defects.

FIG. 13 is a diagram showing a transition regarding the number of occurrences of bit failures including a bit failure occurrence;

FIG. 14 is a diagram showing a transition regarding the number of occurrences of the bit frequent failure area.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Prober, 2 ... Tester, 3 ... FBM output device, 4 ...
Failure classification WS, 5 ... analysis WS, 6 ... network, 41
... Processing device (CPU), 42 ... Storage device, 43 ... Output device such as display device, 44 ... Input device.

Continuing from the front page (72) Inventor Shuichi Horisaki 292, Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside Hitachi, Ltd.Production Technology Laboratory (72) Inventor Jun Nakazato 292, Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture, Ltd. F-term in Hitachi, Ltd. Production Technology Laboratory (reference) 2G032 AA07 AB20 AE09 AE10 AE12 AF01 4M106 AA01 BA01 CA00 CA41 CA50 DA15 DJ20 DJ21 DJ27 DJ38 5B018 GA03 GA05 HA32 KA01 NA02 QA13 RA02 RA03 RA11 5L106 DD25 DD26

Claims (11)

[Claims] 1. A tester means for acquiring fail bit data from a semiconductor device, and a physical conversion for receiving the fail bit data obtained by the tester means and rearranging the layout order of the semiconductor device, and performing the physical conversion. Based on the failed bit data, it is determined whether or not a bit failure occurs frequently for each recognition area set for the semiconductor device, and information of the determined recognition area where the bit failure occurs frequently is determined. A semiconductor failure analysis system for analyzing failures of the semiconductor device based on the analysis means. 2. Tester means for acquiring fail bit data from a semiconductor device, and receiving the fail bit data acquired by the tester means, performing physical conversion for rearranging the semiconductor device in the layout order, and performing the physical conversion. Based on the failed bit data, it is determined whether or not a bit failure occurs frequently for each recognition area set for the semiconductor device, and the determined number of recognition areas where the bit failure occurs frequently is determined. A semiconductor failure analysis system, comprising: analysis means for counting and analyzing the failure of the semiconductor device based on information on the number of recognition areas in which the counted bit failures occur frequently. 3. A tester means for obtaining fail bit data from a semiconductor device, and a physical conversion for receiving the fail bit data obtained by the tester means and rearranging the layout order of the semiconductor device, and performing the physical conversion. On the basis of the fail bit data obtained, the semiconductor device is classified into at least an area defect and a bit frequent defect for each of the recognition areas set for the semiconductor device, and information of the categorized area defect and the recognition area of the bit frequent defect is obtained. A semiconductor failure analysis system for analyzing failures of the semiconductor device based on the analysis means. 4. A tester means for obtaining fail bit data from a semiconductor device, and a physical conversion for receiving the fail bit data obtained by the tester means and rearranging the layout order of the semiconductor device, and performing the physical conversion. Based on the fail bit data obtained, at least for each recognition area set for the semiconductor device is classified into at least an area defect, a frequent bit failure, a line failure, an adjacent failure, and an isolated point failure. A semiconductor failure analysis system, comprising: analysis means for performing a failure analysis of a semiconductor device based on information of a recognition area of a bit failure and information of a line failure, an adjacent failure, and an isolated point failure. 5. A tester means for obtaining fail bit data from a semiconductor device, and receiving the fail bit data obtained by the tester means, performing a physical conversion for rearranging the semiconductor device in the layout order, and performing the physical conversion. Based on the failed bit data, at least for each of the recognition areas set for the semiconductor device, the semiconductor device is classified into at least an area defect, a bit frequent defect, a line defect, an adjacent defect, and an isolated point defect. A drawing process is performed so that information can be displayed, and a failure analysis of the semiconductor device is performed based on the information on the recognition areas of the classified area failure and the bit-frequent failure and information on the line failure, the adjacent failure, and the isolated point failure. A semiconductor failure analysis system, comprising: analysis means. 6. An obtaining step of obtaining fail bit data from a semiconductor device using a tester means, and receiving the fail bit data obtained in the obtaining step by using an analyzing means and rearranging the data in the layout order of the semiconductor device. The physical conversion is performed, and based on the fail bit data on which the physical conversion has been performed, it is determined whether or not a bit failure occurs frequently for each recognition area set for the semiconductor device. An analysis step of performing a failure analysis of the semiconductor device based on information of a recognition area where failures occur frequently. 7. An obtaining step of obtaining fail bit data from a semiconductor device using a tester means, and receiving the fail bit data obtained in the obtaining step by using an analyzing means and rearranging the order of the layout of the semiconductor device. The physical conversion is performed, and based on the fail bit data on which the physical conversion has been performed, it is determined whether or not a bit failure occurs frequently for each recognition area set for the semiconductor device. An analysis step of counting the number of recognition areas where defects occur frequently, and performing a failure analysis of the semiconductor device based on information on the number of recognition areas where the counted bit defects occur frequently. Semiconductor failure analysis method. 8. An obtaining step of obtaining fail bit data from a semiconductor device using a tester means, and receiving the fail bit data obtained in the obtaining step by using an analyzing means and rearranging the data in the layout order of the semiconductor device. A physical conversion is performed, and based on the fail bit data on which the physical conversion has been performed, at least a region defect and a bit frequent defect are classified for each recognition region set for the semiconductor device. And a analyzing step of performing a failure analysis of the semiconductor device based on information of a recognition area of the bit failure. 9. An obtaining step of obtaining fail bit data from a semiconductor device using a tester means, and receiving the fail bit data obtained in the obtaining step by using an analyzing means and rearranging the data in the layout order of the semiconductor device. The physical conversion is performed, and at least an area defect, a bit frequent defect, a line defect, an adjacent defect, and an isolated point defect are generated for each recognition area set for the semiconductor device based on the fail bit data subjected to the physical conversion. And an analysis step of performing a failure analysis of the semiconductor device based on the information of the recognition area of the classified area failure and the bit failure occurrence and the information of the line failure, the adjacent failure, and the isolated point failure. Characteristic semiconductor failure analysis method. 10. An acquiring step of acquiring fail bit data from a semiconductor device using a tester means, and receiving the fail bit data acquired in the income step by using an analyzing means and rearranging the data in the layout order of the semiconductor device. The physical conversion is performed, and at least an area defect, a bit frequent defect, a line defect, an adjacent defect, and an isolated point defect are generated for each recognition area set for the semiconductor device based on the fail bit data subjected to the physical conversion. The drawing process is performed so that information on the classified failure mode can be displayed. Further, the information on the recognition areas of the classified area failure and the bit frequent failure and the information of the line failure, the adjacent failure, and the isolated point failure. An analysis step of performing a failure analysis of the semiconductor device based on the information. 11. A method for manufacturing a semiconductor device, comprising manufacturing a semiconductor device by using the semiconductor failure analysis system according to claim 1, 2, 3, 4 or 5.