JP2003330993A5 - - Google Patents

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Publication number
JP2003330993A5
JP2003330993A5 JP2003104748A JP2003104748A JP2003330993A5 JP 2003330993 A5 JP2003330993 A5 JP 2003330993A5 JP 2003104748 A JP2003104748 A JP 2003104748A JP 2003104748 A JP2003104748 A JP 2003104748A JP 2003330993 A5 JP2003330993 A5 JP 2003330993A5
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JP
Japan
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attribute
package
value
models
selecting
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JP2003104748A
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English (en)
Japanese (ja)
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JP2003330993A (ja
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Priority claimed from US10/179,077 external-priority patent/US6711730B2/en
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Publication of JP2003330993A publication Critical patent/JP2003330993A/ja
Publication of JP2003330993A5 publication Critical patent/JP2003330993A5/ja
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JP2003104748A 2002-05-13 2003-04-09 複数の集積回路パッケージモデルからの信号ネット情報の合成 Withdrawn JP2003330993A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/179,077 US6711730B2 (en) 2002-05-13 2002-05-13 Synthesizing signal net information from multiple integrated circuit package models
US10/179077 2002-05-13

Publications (2)

Publication Number Publication Date
JP2003330993A JP2003330993A (ja) 2003-11-21
JP2003330993A5 true JP2003330993A5 (enExample) 2005-05-19

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Application Number Title Priority Date Filing Date
JP2003104748A Withdrawn JP2003330993A (ja) 2002-05-13 2003-04-09 複数の集積回路パッケージモデルからの信号ネット情報の合成

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US (2) US6711730B2 (enExample)
JP (1) JP2003330993A (enExample)

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JP6787045B2 (ja) * 2016-10-31 2020-11-18 富士通株式会社 検証支援プログラム、検証支援方法、および情報処理装置
US10565342B1 (en) * 2018-01-30 2020-02-18 Cadence Design Systems, Inc. Electronic circuit design editor with overlay of layout and schematic design features
US10726176B1 (en) * 2019-05-15 2020-07-28 Bqr Reliability Engineering Ltd. Method and apparatus for designing electrical and electronic circuits
CN117171833B (zh) * 2023-11-03 2024-02-02 商飞软件有限公司 一种信号逻辑图设计系统

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