JP2003330993A - 複数の集積回路パッケージモデルからの信号ネット情報の合成 - Google Patents

複数の集積回路パッケージモデルからの信号ネット情報の合成

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Publication number
JP2003330993A
JP2003330993A JP2003104748A JP2003104748A JP2003330993A JP 2003330993 A JP2003330993 A JP 2003330993A JP 2003104748 A JP2003104748 A JP 2003104748A JP 2003104748 A JP2003104748 A JP 2003104748A JP 2003330993 A JP2003330993 A JP 2003330993A
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Japan
Prior art keywords
net
package
attribute
signal
value
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Withdrawn
Application number
JP2003104748A
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English (en)
Japanese (ja)
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JP2003330993A5 (enExample
Inventor
Mark D Frank
マーク・ディ・フランク
William Bryson Mchardy
ウイリアム・ブライソン・マクハーディ
Peter Shaw Moldauer
ピーター・ショウ・モルダウアー
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HP Inc
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Hewlett Packard Co
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Publication date
Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Publication of JP2003330993A publication Critical patent/JP2003330993A/ja
Publication of JP2003330993A5 publication Critical patent/JP2003330993A5/ja
Withdrawn legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06Q—INFORMATION AND COMMUNICATION TECHNOLOGY [ICT] SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES; SYSTEMS OR METHODS SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES, NOT OTHERWISE PROVIDED FOR
    • G06Q40/00—Finance; Insurance; Tax strategies; Processing of corporate or income taxes
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Business, Economics & Management (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Accounting & Taxation (AREA)
  • Development Economics (AREA)
  • Economics (AREA)
  • Finance (AREA)
  • Marketing (AREA)
  • Strategic Management (AREA)
  • Technology Law (AREA)
  • General Business, Economics & Management (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
JP2003104748A 2002-05-13 2003-04-09 複数の集積回路パッケージモデルからの信号ネット情報の合成 Withdrawn JP2003330993A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/179,077 US6711730B2 (en) 2002-05-13 2002-05-13 Synthesizing signal net information from multiple integrated circuit package models
US10/179077 2002-05-13

Publications (2)

Publication Number Publication Date
JP2003330993A true JP2003330993A (ja) 2003-11-21
JP2003330993A5 JP2003330993A5 (enExample) 2005-05-19

Family

ID=29400862

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003104748A Withdrawn JP2003330993A (ja) 2002-05-13 2003-04-09 複数の集積回路パッケージモデルからの信号ネット情報の合成

Country Status (2)

Country Link
US (2) US6711730B2 (enExample)
JP (1) JP2003330993A (enExample)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6922822B2 (en) * 2002-07-19 2005-07-26 Hewlett-Packard Development Company, L.P. Verifying proximity of ground vias to signal vias in an integrated circuit
US7219322B2 (en) * 2004-04-27 2007-05-15 Hewlett-Packard Development Company, L.P. Multiple propagation speeds of signals in layered circuit apparatus
US20060076547A1 (en) * 2004-09-24 2006-04-13 Mentor Graphics Corp. Three-dimensional viewing and editing of microcircuit design
US7472368B2 (en) * 2005-03-24 2008-12-30 International Business Machines Corporation Method for implementing vertically coupled noise control through a mesh plane in an electronic package design
US7243314B2 (en) * 2005-04-14 2007-07-10 Inventec Corporation Window operation interface for graphically revising electrical constraint set and method of using the same
US7437690B2 (en) * 2005-10-13 2008-10-14 International Business Machines Corporation Method for predicate-based compositional minimization in a verification environment
US8849943B2 (en) * 2005-12-19 2014-09-30 Palo Alto Research Center Incorporated Using multi-resolution visual codes to facilitate information browsing in the physical world
US20070168372A1 (en) * 2006-01-17 2007-07-19 Baumgartner Jason R Method and system for predicate selection in bit-level compositional transformations
US7519938B1 (en) * 2006-10-05 2009-04-14 Xilinx, Inc. Strategies for generating an implementation of an electronic design
CA2786220C (en) * 2011-08-18 2020-02-18 Valydate Inc. Validation of circuit definitions
US8612913B1 (en) * 2012-12-21 2013-12-17 Synopsys, Inc. Automated approach to planning critical signals and busses
US10845780B2 (en) * 2015-04-24 2020-11-24 Hewlett-Packard Development Company, L.P. Method for setting printing properties of a three-dimensional object for additive manufacturing process
JP6787045B2 (ja) * 2016-10-31 2020-11-18 富士通株式会社 検証支援プログラム、検証支援方法、および情報処理装置
US10565342B1 (en) * 2018-01-30 2020-02-18 Cadence Design Systems, Inc. Electronic circuit design editor with overlay of layout and schematic design features
US10726176B1 (en) * 2019-05-15 2020-07-28 Bqr Reliability Engineering Ltd. Method and apparatus for designing electrical and electronic circuits
CN117171833B (zh) * 2023-11-03 2024-02-02 商飞软件有限公司 一种信号逻辑图设计系统

Family Cites Families (45)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05120373A (ja) 1991-10-30 1993-05-18 Mitsubishi Electric Corp 設計検証装置
US5349659A (en) 1992-01-23 1994-09-20 Cadence Design Systems, Inc. Hierarchical ordering of logical elements in the canonical mapping of net lists
US5396435A (en) 1993-02-10 1995-03-07 Vlsi Technology, Inc. Automated circuit design system and method for reducing critical path delay times
US5956257A (en) 1993-03-31 1999-09-21 Vlsi Technology, Inc. Automated optimization of hierarchical netlists
US5426591A (en) 1994-01-28 1995-06-20 Vlsi Technology, Inc. Apparatus and method for improving the timing performance of a circuit
US5608645A (en) 1994-03-17 1997-03-04 Vlsi Technology, Inc. Method of finding a critical path in a circuit by considering the clock skew
US5559718A (en) 1994-04-28 1996-09-24 Cadence Design Systems, Inc. System and method for model-based verification of local design rules
US5510998A (en) 1994-06-13 1996-04-23 Cadence Design Systems, Inc. System and method for generating component models
US5590049A (en) 1994-09-07 1996-12-31 Cadence Design Systems, Inc. Method and system for user programmable design verification for printed circuit boards and multichip modules
US5880967A (en) 1995-05-01 1999-03-09 Synopsys, Inc. Minimization of circuit delay and power through transistor sizing
US5726902A (en) 1995-06-07 1998-03-10 Vlsi Technology, Inc. Method and apparatus for characterizing timing behavior of datapaths for integrated circuit design and fabrication
US5825658A (en) 1995-09-14 1998-10-20 Vlsi Technology, Inc. Method and a system for specifying and automatically analyzing multiple clock timing constraints in a VLSI circuit
US5808896A (en) * 1996-06-10 1998-09-15 Micron Technology, Inc. Method and system for creating a netlist allowing current measurement through a sub-circuit
US5896300A (en) 1996-08-30 1999-04-20 Avant| Corporation Methods, apparatus and computer program products for performing post-layout verification of microelectronic circuits by filtering timing error bounds for layout critical nets
US6212666B1 (en) 1996-11-04 2001-04-03 Synopsys, Inc. Graphic representation of circuit analysis for circuit design and timing performance evaluation
US5995730A (en) 1997-05-23 1999-11-30 Lsi Logic Corporation Method for generating format-independent electronic circuit representations
US6182258B1 (en) 1997-06-03 2001-01-30 Verisity Ltd. Method and apparatus for test generation during circuit design
US6148432A (en) * 1997-11-17 2000-11-14 Micron Technology, Inc. Inserting buffers between modules to limit changes to inter-module signals during ASIC design and synthesis
US6189131B1 (en) * 1998-01-14 2001-02-13 Lsi Logic Corporation Method of selecting and synthesizing metal interconnect wires in integrated circuits
US6301578B1 (en) 1998-01-29 2001-10-09 Cadence Design Systems, Inc. Method of compressing integrated circuit simulation data
US6286128B1 (en) 1998-02-11 2001-09-04 Monterey Design Systems, Inc. Method for design optimization using logical and physical information
US6289491B1 (en) 1998-02-20 2001-09-11 Lsi Logic Corporation Netlist analysis tool by degree of conformity
US6263483B1 (en) 1998-02-20 2001-07-17 Lsi Logic Corporation Method of accessing the generic netlist created by synopsys design compilier
US6093214A (en) * 1998-02-26 2000-07-25 Lsi Logic Corporation Standard cell integrated circuit layout definition having functionally uncommitted base cells
US6308299B1 (en) 1998-07-17 2001-10-23 Cadence Design Systems, Inc. Method and system for combinational verification having tight integration of verification techniques
JP2002526908A (ja) 1998-09-30 2002-08-20 ケイデンス デザイン システムズ インコーポレイテッド ブロックをベースとする設計方法
US6247163B1 (en) 1998-10-13 2001-06-12 Cadence Design Systems, Inc. Method and system of latch mapping for combinational equivalence checking
US6233724B1 (en) 1998-10-30 2001-05-15 Micron Technology, Inc. Circuit synthesis time budgeting based upon wireload information
US6282693B1 (en) 1998-12-16 2001-08-28 Synopsys, Inc. Non-linear optimization system and method for wire length and density within an automatic electronic circuit placer
US6301693B1 (en) 1998-12-16 2001-10-09 Synopsys, Inc. Non-linear optimization system and method for wire length and delay optimization for an automatic electric circuit placer
US6324675B1 (en) 1998-12-18 2001-11-27 Synopsys, Inc. Efficient iterative, gridless, cost-based fine router for computer controlled integrated circuit design
US6253361B1 (en) * 1999-04-21 2001-06-26 Magma Design Automation, Inc. Generalized theory of logical effort for look-up table based delay models using capacitance ratio
US6311318B1 (en) 1999-07-13 2001-10-30 Vlsi Technology, Inc. Design for test area optimization algorithm
US6336206B1 (en) 1999-09-27 2002-01-01 Synopsys, Inc. Method and apparatus for structural input/output matching for design verification
US6637018B1 (en) * 1999-10-29 2003-10-21 Cadence Design Systems, Inc. Mixed signal synthesis behavioral models and use in circuit design optimization
JP3329323B2 (ja) 1999-12-22 2002-09-30 日本電気株式会社 波形なまり検証方法及び波形なまり検証装置
WO2001065424A2 (en) 2000-02-29 2001-09-07 Cadence Design Systems, Inc. Device level layout optimization in electronic design automation
US6629294B2 (en) 2000-03-10 2003-09-30 General Electric Company Tool and method for improving the quality of board design and modeling
US6651228B1 (en) * 2000-05-08 2003-11-18 Real Intent, Inc. Intent-driven functional verification of digital designs
US6631508B1 (en) * 2000-06-07 2003-10-07 Xilinx, Inc. Method and apparatus for developing and placing a circuit design
US6425113B1 (en) 2000-06-13 2002-07-23 Leigh C. Anderson Integrated verification and manufacturability tool
US6502224B2 (en) * 2001-04-12 2002-12-31 International Business Machines Corporation Method and apparatus for synthesizing levelized logic
US6651230B2 (en) * 2001-12-07 2003-11-18 International Business Machines Corporation Method for reducing design effect of wearout mechanisms on signal skew in integrated circuit design
US6567971B1 (en) * 2001-12-20 2003-05-20 Logicvision, Inc. Circuit synthesis method using technology parameters extracting circuit
US6925622B2 (en) * 2002-09-30 2005-08-02 Freescale Semiconductor, Inc. System and method for correlated clock networks

Also Published As

Publication number Publication date
US6711730B2 (en) 2004-03-23
US20030212980A1 (en) 2003-11-13
US20040143531A1 (en) 2004-07-22

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