JP2003324183A5 - - Google Patents

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Publication number
JP2003324183A5
JP2003324183A5 JP2002131505A JP2002131505A JP2003324183A5 JP 2003324183 A5 JP2003324183 A5 JP 2003324183A5 JP 2002131505 A JP2002131505 A JP 2002131505A JP 2002131505 A JP2002131505 A JP 2002131505A JP 2003324183 A5 JP2003324183 A5 JP 2003324183A5
Authority
JP
Japan
Prior art keywords
semiconductor device
substrate
semiconductor
chip
opening
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2002131505A
Other languages
English (en)
Japanese (ja)
Other versions
JP2003324183A (ja
Filing date
Publication date
Application filed filed Critical
Priority to JP2002131505A priority Critical patent/JP2003324183A/ja
Priority claimed from JP2002131505A external-priority patent/JP2003324183A/ja
Priority to US10/283,208 priority patent/US20030209808A1/en
Publication of JP2003324183A publication Critical patent/JP2003324183A/ja
Priority to US10/953,059 priority patent/US20050104211A1/en
Publication of JP2003324183A5 publication Critical patent/JP2003324183A5/ja
Pending legal-status Critical Current

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JP2002131505A 2002-05-07 2002-05-07 半導体装置 Pending JP2003324183A (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2002131505A JP2003324183A (ja) 2002-05-07 2002-05-07 半導体装置
US10/283,208 US20030209808A1 (en) 2002-05-07 2002-10-30 Semiconductor device having semiconductor chips mounted on package substrate
US10/953,059 US20050104211A1 (en) 2002-05-07 2004-09-30 Semiconductor device having semiconductor chips mounted on package substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002131505A JP2003324183A (ja) 2002-05-07 2002-05-07 半導体装置

Publications (2)

Publication Number Publication Date
JP2003324183A JP2003324183A (ja) 2003-11-14
JP2003324183A5 true JP2003324183A5 (cg-RX-API-DMAC7.html) 2005-09-29

Family

ID=29397351

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002131505A Pending JP2003324183A (ja) 2002-05-07 2002-05-07 半導体装置

Country Status (2)

Country Link
US (1) US20030209808A1 (cg-RX-API-DMAC7.html)
JP (1) JP2003324183A (cg-RX-API-DMAC7.html)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7247932B1 (en) * 2000-05-19 2007-07-24 Megica Corporation Chip package with capacitor
US6825567B1 (en) * 2003-08-19 2004-11-30 Advanced Semiconductor Engineering, Inc. Face-to-face multi-chip flip-chip package
JP4591886B2 (ja) * 2004-07-21 2010-12-01 ローム株式会社 半導体装置を用いた電源回路装置
JP2008187050A (ja) * 2007-01-30 2008-08-14 Toshiba Corp システムインパッケージ装置
US8237289B2 (en) 2007-01-30 2012-08-07 Kabushiki Kaisha Toshiba System in package device
JP4705070B2 (ja) * 2007-05-01 2011-06-22 セイコーインスツル株式会社 半導体装置、その製造方法、及び、表示装置の製造方法、
US8227904B2 (en) 2009-06-24 2012-07-24 Intel Corporation Multi-chip package and method of providing die-to-die interconnects in same
JP2011192893A (ja) * 2010-03-16 2011-09-29 Zycube:Kk 半導体デバイスの実装方法
US8654538B2 (en) * 2010-03-30 2014-02-18 Ibiden Co., Ltd. Wiring board and method for manufacturing the same
US9129958B2 (en) * 2011-12-22 2015-09-08 Intel Corporation 3D integrated circuit package with window interposer
US10008475B2 (en) * 2012-09-27 2018-06-26 Intel Corporation Stacked-die including a die in a package substrate
US20150255411A1 (en) * 2014-03-05 2015-09-10 Omkar G. Karhade Die-to-die bonding and associated package configurations
US20190311983A1 (en) * 2016-12-27 2019-10-10 Intel Corporation Stacking multiple dies having dissimilar interconnect structure layout and pitch
US10667399B1 (en) * 2018-11-27 2020-05-26 Nokia Solutions And Networks Oy Discrete component carrier
US11721677B2 (en) 2018-12-27 2023-08-08 Intel Corporation Microelectronic assemblies having an integrated capacitor
US11881248B2 (en) * 2019-01-30 2024-01-23 Ultramemory Inc. Three-dimensional semiconductor module including system in a package (SIP) with improved heat dissipation efficiency
US20240079337A1 (en) * 2022-09-02 2024-03-07 Intel Corporation Microelectronic assemblies having power delivery routed through a bridge die

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW373308B (en) * 1995-02-24 1999-11-01 Agere Systems Inc Thin packaging of multi-chip modules with enhanced thermal/power management
EP1447849A3 (en) * 1997-03-10 2005-07-20 Seiko Epson Corporation Semiconductor device and circuit board having the same mounted thereon
US6150724A (en) * 1998-03-02 2000-11-21 Motorola, Inc. Multi-chip semiconductor device and method for making the device by using multiple flip chip interfaces
US6369444B1 (en) * 1998-05-19 2002-04-09 Agere Systems Guardian Corp. Packaging silicon on silicon multichip modules
US6228682B1 (en) * 1999-12-21 2001-05-08 International Business Machines Corporation Multi-cavity substrate structure for discrete devices
JP3677429B2 (ja) * 2000-03-09 2005-08-03 Ｎｅｃエレクトロニクス株式会社 フリップチップ型半導体装置の製造方法
US7247932B1 (en) * 2000-05-19 2007-07-24 Megica Corporation Chip package with capacitor
US6734539B2 (en) * 2000-12-27 2004-05-11 Lucent Technologies Inc. Stacked module package

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