JP2003324180A - Mounter for semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device wherein a semiconductor element is mounted on both sides of a multilayer circuit board having three-dimensional wiring using inner via holes, which enables high-speed operation and the reduction of size by using the ordinary stacked-layer structure of the semiconductor elements without employing a chip-on-chip structure. <P>SOLUTION: General-purpose semiconductor devices are mounted on both sides of the multilayer circuit board having three-dimensional wiring using the inner via holes so as to oppose each other with the multilayer circuit board between. Electrode terminals of individual semiconductor elements are connected via the three-dimensional wiring of the multilayer circuit board. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device formed by mounting semiconductor elements on both surfaces of a multilayer wiring board having a three-dimensional wiring using inner via holes.

[0002]

2. Description of the Related Art In order to miniaturize electronic equipment using semiconductor elements, semiconductor elements in which a plurality of electronic circuits are incorporated in a single semiconductor element have been developed. However, it is difficult to give all the functions to a single semiconductor element due to restrictions such as design rules, and it is often necessary to use a plurality of semiconductor elements. In such a case, in order to reduce the size and increase the speed, as shown in FIG. 19, a chip-on-chip configuration is used in which semiconductor elements are directly connected to each other by using electrode portions.
In the figure, 1 is a first semiconductor element, 2 is a first semiconductor element 1
Formed on the electrode terminals, 3 is a second semiconductor element, and 4 is a second semiconductor element.
2. The electrode terminals formed on the semiconductor element 3 of FIG. 10 are joints mainly made of a conductive metal material such as solder, and 11 is a cured insulating resin. In this way, by adopting the chip-on-chip configuration, the wiring length between the elements can be shortened, the transmission delay of electric signals can be reduced, the speed of the semiconductor device can be increased, and the semiconductor elements can be stacked. Therefore, the semiconductor device can be downsized.

[0003]

In such a chip-on-chip structure, when the first semiconductor element 1 and the second semiconductor element 3 are electrically connected via the joint portion 10, each semiconductor is connected. It is necessary to arrange the electrode terminals 2 and 3 of the element at positions facing each other. For this reason, a general-purpose semiconductor element cannot be used, and the electrode terminals 2, 3 are previously formed.
It is necessary to use a semiconductor device designed in consideration of the position of, and the design and development of the semiconductor device becomes indispensable separately. Further, since the positions of the electrode terminals 2 and 3 of the first and second semiconductor elements are limited, it may be difficult to reduce the size of the semiconductor device, which leads to a reduction in manufacturing yield. Therefore,
An object of the present invention is to provide a semiconductor device capable of high-speed operation and miniaturization by using a general-purpose semiconductor element without using a chip-on-chip structure. In particular, the electrode arrangement of the semiconductor element is an area array type C.
An object of the present invention is to provide a semiconductor device in which the wiring length does not become long and high-speed operation and miniaturization are possible even when a semiconductor element such as PU is used.

[0004]

As a result of intensive research, the inventors of the present invention have found that a general-purpose semiconductor device faces a multilayer wiring board having a three-dimensional wiring using inner via holes on both sides of the multilayer wiring board. It is possible to manufacture a miniaturized semiconductor device while maintaining high-speed operation of a semiconductor element by mounting the semiconductor device and connecting the electrode terminals to each other, in particular, by using such a three-dimensional wiring, The present invention has been completed by finding that even a semiconductor element having an area array type electrode arrangement can manufacture a semiconductor device without increasing the wiring length.

That is, according to the present invention, insulating layers made of a resin-impregnated fiber sheet and circuit pattern layers are alternately laminated, and the insulating layers are formed through a plurality of inner via holes penetrating each insulating layer. A multi-layer wiring board provided with three-dimensional wiring to which the circuit pattern layers provided on both sides are electrically connected, and at least first and second semiconductor elements face-down flip-chip mounted on both sides thereof. , A semiconductor device in which the electrode terminals of the respective semiconductor elements are connected to each other by the three-dimensional wiring. As described above, in the semiconductor device according to the present invention, the semiconductor element is face-down flip-chip mounted via the thin multilayer wiring board, so that a general-purpose semiconductor element is used to form a chip-on-chip structure. An approximately miniaturized semiconductor device can be formed.
In particular, in a multilayer wiring board, three-dimensional wiring using inner via holes is used. Therefore, the wiring connecting the semiconductor elements provided on both surfaces of the multilayer wiring board can be a three-dimensional three-dimensional wiring. It is possible to shorten the wiring length as compared with the case of using a normal wiring board in which wiring is routed and becomes a two-dimensional wiring. Therefore, by using the present invention, even when a general-purpose semiconductor element is used, as in the case of using the conventional chip-on-chip structure, the size of the semiconductor device is reduced and the delay of the electric signal due to the shortening of the wiring length is delayed. It is possible to speed up the operation of the device while preventing the above. In addition, since the multilayer wiring board is arranged between the semiconductor elements, stress is not applied to the other semiconductor element when each semiconductor element is attached or detached, and the occurrence of damage can be suppressed.

1 mounted on both sides of the multilayer wiring board
Alternatively, the projection planes of two or more semiconductor elements in the vertical direction on the multilayer wiring board preferably overlap. In this way, by mounting the semiconductor elements on both surfaces of the multilayer wiring board so that the projection planes in the vertical direction thereof overlap, the insulating substrate constituting the multilayer wiring board is impregnated with a thermosetting resin that has low rigidity and is easily warped. Even when it is formed from the above-mentioned fiber sheet, it is possible to reduce the warp of the multilayer wiring board 107 in the vertical direction (Z-axis direction).

Further, according to the present invention, by bending the multilayer wiring board on which the first and second semiconductor elements are mounted on both surfaces of a predetermined location respectively, the multilayer wiring board has the second semiconductor element. It is glued to cover the back of the
By flip-chip mounting the third semiconductor device so as to face the back surface of the second semiconductor element via the multilayer wiring board, the first, second, and third semiconductor elements are respectively attached. It is also a semiconductor device characterized by being laminated via a multilayer wiring board. By thus bending the thin multilayer wiring board and alternately stacking the semiconductor device and the multilayer wiring board, the semiconductor device can be downsized even when a large number of semiconductor elements are mounted.

Further, according to the present invention, the semiconductor device is further mounted on a mother multilayer wiring board having a circuit pattern on its surface, and the semiconductor device and the mother multilayer wiring board are connected by an electrical connecting means. It is also a mounted body of a semiconductor device. By mounting the semiconductor element on the mother multilayer wiring board, it becomes possible to form a high-density mounting body, and at the same time, the semiconductor device is manufactured in advance, and the quality and reliability are inspected.
By mounting only good semiconductor devices on the mother multilayer wiring board, it is possible to improve the productivity of the mounted body.

In the electrical connection means, the back surface of the second semiconductor element is adhered onto the mother multilayer wiring board, and the semiconductor device is mounted on the mother multilayer wiring board. It is preferable that the protruding electrode is sandwiched between the multilayer wiring board and the mother multilayer wiring board, and electrically connects the circuit pattern on the multilayer wiring board and the circuit pattern on the mother multilayer wiring board. . By using the protruding electrode as the electrical connecting means, it becomes possible to form the connecting means by utilizing the empty space between the multilayer wiring board of the semiconductor device and the mother multilayer wiring board, and to reduce the size of the semiconductor device package. Is possible.

In the electrical connection means, the back surface of the second semiconductor element is adhered onto the mother multilayer wiring board to bend the multilayer wiring board of the semiconductor device mounted on the mother multilayer wiring board. By doing so, it is preferable that the connecting means electrically connects the circuit pattern on the multilayer wiring board and the circuit pattern on the mother multilayer wiring board. This is because by bending the multilayer wiring board of the semiconductor device and forming the connecting means, it is possible to reduce the electrode forming step and reduce the production cost.

The electrical connecting means is a conductive support for electrically connecting to the wiring of the multilayer wiring board of the semiconductor device and for fixing the semiconductor device on the mother multilayer wiring board. , By fixing the semiconductor device on the mother multilayer wiring board through the conductive support, electrically connecting the wiring of the multilayer wiring board and the circuit pattern on the mother multilayer wiring board It is preferably a support. As described above, by using the semiconductor device including the conductive support such as metal electrically connected to the multilayer wiring board, the support can be handled like a QFP pin, and the mother multilayer wiring board can be used. This is because it is possible to easily attach and detach it on the top.

[0012] The electrical connection means is configured so that at least the first and second semiconductor elements are mounted on both surfaces of a predetermined location, respectively, and the multilayer wiring board is curved to cover the back surface of the second semiconductor element. By placing the semiconductor device on the mother multilayer wiring board so that the bonded multilayer wiring board contacts the mother multilayer wiring board, the circuit pattern on the multilayer wiring board and the mother multilayer wiring board are placed. It is preferable that the connecting means electrically connects the upper circuit pattern. By using such connecting means, connection using the lower region of the mounting surface of the semiconductor element becomes possible,
This is because the package of the semiconductor device can be downsized.

According to the present invention, the semiconductor device in which the semiconductor device and the multilayer wiring board are alternately laminated is placed on a mother multilayer wiring board having a circuit pattern on the surface thereof, and the multilayer wiring board of the semiconductor device is provided. It is also a mounted body of a semiconductor device, characterized in that the upper circuit pattern and the circuit pattern on the mother multilayer wiring board are electrically connected. This is because the semiconductor device can be mounted on the mother multilayer wiring board at a high density by using such a mounting body.

Further, according to the present invention, the electrode terminal of at least one semiconductor element of the first and second semiconductor elements is formed so as to be arranged in an area array. But also. In the multilayer wiring board according to the present invention, since the three-dimensional wiring using the inner via holes is used, the wiring connecting the semiconductor elements provided on both surfaces of the multilayer wiring board can be a three-dimensional three-dimensional wiring. Become. Therefore, the wiring is laid on the substrate plane,
The wiring length can be shortened as compared with a normal wiring board in which the wiring is two-dimensional. Therefore, it is effective when mounting a semiconductor element having a structure having electrode terminals not only in the peripheral portion of the semiconductor element but also in the vicinity of the central portion, such as a semiconductor element in which electrodes are arranged in an area array.

Further, according to the present invention, a first area is provided in which the electrode terminals are formed in an area array on each surface of the multilayer wiring board.
And a second semiconductor element in which the electrode terminals are formed in a peripheral shape are face-down flip-chip mounted, and between the electrode terminals of the semiconductor element,
It is also a semiconductor device characterized by being connected by the three-dimensional wiring. As described above, in the semiconductor device according to the present invention, the semiconductor element is flip-chip mounted face down through the thin multilayer wiring board. Therefore, the semiconductor element is flip-chip mounted to reduce the size of the semiconductor device. Can be formed. Further, since the three-dimensional wiring using the inner via holes is used in the multilayer wiring board, the wiring connecting the semiconductor elements provided on both surfaces of the multilayer wiring board can be three-dimensional wiring. Therefore, the wiring is laid out on the plane of the substrate, and the wiring length can be shortened as compared with the case of using an ordinary wiring board which is a two-dimensional wiring. Therefore, by using the present invention, it is possible to reduce the size of the semiconductor device even when a semiconductor element having electrodes arranged in an area array type is mounted. Further, by shortening the wiring length, it is possible to prevent the delay of the electric signal and increase the operating speed, and it is also possible to reduce the power consumption by reducing the resistance of the wiring.

Further, according to the present invention, a semiconductor element having the electrode terminals formed in an area array is flip-chip mounted face down on one surface of the multilayer wiring board, and the other surface of the multilayer wiring board is mounted. An electronic part is mounted on the semiconductor device, and the electrode terminal of the semiconductor element and the electrode terminal of the electronic part are connected by the three-dimensional wiring. As described above, in the semiconductor device according to the present invention, since the three-dimensional wiring using the inner via holes is used in the multilayer wiring board, semiconductor elements and electronic components such as bypass capacitors provided on both surfaces of the multilayer wiring board are used. Since the three-dimensional wiring can be connected to each other, the wiring can be laid out on the plane of the board, and the wiring length can be shortened as compared with the case of using a normal wiring board that is a two-dimensional wiring. Become. Therefore, it is possible to effectively remove noise components during high-speed driving. In particular, when connecting an electrode in the central portion of a semiconductor element in which electrodes are arranged in an area array and an electronic component, the wiring length can be significantly shortened as compared with the case where a conventional wiring board is used. Become.

The electronic component is preferably a bypass capacitor. When using a bypass capacitor as an electronic component, it is possible to effectively remove noise by the bypass capacitor by reducing noise in the wiring section by shortening the wiring length.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiment 1. FIG. 1 shows a semiconductor device according to a first embodiment of the present invention, and here shows a semiconductor device in which two semiconductor elements are mounted on one surface and one semiconductor element is mounted on the other surface. Figure 1 (a)
1A is a perspective view of the semiconductor device, and FIG. 1B is a cross-sectional view of the semiconductor device shown in FIG. In the figure, 101 is a first semiconductor element, 102 is an electrode terminal formed on the element formation surface of the first semiconductor element 101, and 103.
Is a second semiconductor element, 105 is a third semiconductor element, 10
4, 106 are electrode terminals formed on each semiconductor element,
107 is a multilayer wiring board, 108 is a circuit pattern on the surface layer formed on the multilayer wiring board, and 109 is an inner via hole. Further, 110 is the semiconductor element 101, 103, 105.
Reference numeral 111 is a joint portion that electrically connects the circuit pattern 108 on the surface layer of the multilayer wiring board 107 with an insulating thermosetting resin.

In the manufacturing process of the semiconductor device shown in FIG. 1, first, three semiconductor elements 101, 103 and 105 are prepared, and Au ball bumps are formed on the surfaces of the electrode terminals 102, 104 and 106 using a wire bonding device. After forming, the required amount of conductive adhesive is applied to the top of the. Such a conductive adhesive is made of a mixture of a powder of a conductive metal such as Ag, Cu and Ni and a resin. In this way, the semiconductor elements 101 and 103 on which the ball bumps of Au or the like are formed by attaching the conductive adhesive to the multilayer wiring board 107 are used.
On the front surface of the semiconductor element 105, the semiconductor elements 105 are sequentially face-down flip-chip mounted on the back surface of the multilayer wiring board 107 so as to face each other via the multilayer wiring board 107.
The heat treatment cures the adhesive and bonds it onto the multilayer wiring board 107.

Here, in FIG. 2 (a) (b) (e), the first
Of the bumps provided on the back surfaces of the semiconductor element 101, the second semiconductor element 103, and the third semiconductor element 105 of
2C and 2D show circuit patterns on the upper surface and the back surface of the multilayer wiring board 107 on which these semiconductor elements are mounted,
Show each. The bumps a1, a2, a3 ... Formed on the back surface of the first semiconductor element 101 and the bumps b1, b2, b3 ... Formed on the back surface of the second semiconductor element 103.
Are the electrodes x1, x2 on the upper surface of the multilayer wiring board 107,
, and x11, x12, x13, ... On the other hand, the bumps c1, c2, c3 ... Formed on the back surface of the third semiconductor element 105 are connected to the electrodes y1, y2, y3 ... On the lower surface of the multilayer wiring board 107. Furthermore, the electrodes x1 and y formed on the upper surface and the lower surface of the multilayer wiring board 107 are formed by the three-dimensional wiring of the multilayer wiring board 107.
1, x2 and y2, x3 and y3 ... Are electrically connected to each other. Therefore, by mounting the first and second semiconductor elements 101, 102 and the third semiconductor element 105 on both surfaces of the multilayer wiring board 107, the three-dimensional wiring of the multilayer wiring board 107 can be provided between the electrode terminals of each semiconductor element. It is possible to form a laminated structure similar to the conventional chip-on-chip structure by being electrically connected to each other. still,
By curing the conductive adhesive, the semiconductor elements 101, 103,
After fixing 105 on the multilayer wiring board 107, an electrical inspection is performed to confirm that each semiconductor element is a good product.

Next, the semiconductor elements 101, 103, 105
Insulating thermosetting resin 1 in the gap between the wiring board and the multilayer wiring board 107
After the filling with 11, the thermosetting resin 111 is completely cured by heat treatment to enhance mechanical strength and connection quality.
If the semiconductor element is judged to be defective in the electrical inspection, only the semiconductor element is removed and replaced with a new semiconductor element. At this time, the semiconductor element can be easily removed by adjusting the adhesive strength of the conductive adhesive to a necessary minimum. The adhesive strength is 3 × 10 6 to 30 × 10 6 N / bump.
About m2 is preferable.

The multilayer wiring board 107 is described in Japanese Patent Laid-Open No. 6-2.
No. 68345, an insulating substrate made of a resin-impregnated fiber sheet and a circuit pattern are alternately laminated, and a conductive inner via hole penetrating the insulating substrate and the circuit pattern are electrically connected to each other. A multilayer wiring board that forms a three-dimensional wiring connected to is used. In particular, the insulating substrate of the multilayer wiring board 107 is preferably composed of a fiber sheet such as glass cloth or aramid cloth impregnated with a thermosetting resin. This is because a fiber sheet impregnated with a thermosetting resin has a smaller Young's modulus than a wiring board using an inorganic substrate such as a ceramic as an insulating substrate, and therefore stresses applied to a mounted semiconductor element or a connecting portion are small. This is because it is reduced.
In addition, since the coefficient of thermal expansion can be reduced by including the filler such as glass cloth or aramid cloth, the thermal stress applied to the semiconductor element and the connecting portion can be reduced also by this. As described above, by using a fiber sheet such as a glass cloth or an aramid cloth impregnated with a thermosetting resin as the material forming the insulating substrate of the multilayer wiring board 107,
The stress applied to the semiconductor element and the connecting portion is reduced, and a high quality semiconductor device can be formed.

FIG. 3 is a plan view of the semiconductor device according to this embodiment as viewed from the first semiconductor element 101 side. In the figure, the same symbols as those in FIG. 1 are the same or corresponding parts. Indicates. As can be seen from FIG. 3, in the present embodiment, the projection surface of the semiconductor elements 101, 103 in the direction perpendicular to the wiring formation surface of the multilayer wiring board 107 (Z direction) is mounted on the back surface. 105 multilayer wiring board 1
The wiring formation surface of 07 at least partially overlaps the projection surface in the vertical direction. Semiconductor device 10
By arranging 1, 103, and 105 according to such a configuration, the semiconductor device according to the present invention has a configuration that is substantially symmetrical with respect to the Z direction with the multilayer wiring board 107 interposed therebetween. In this way, the semiconductor elements 101, 1 with the multilayer wiring board 107 sandwiched therebetween.
When 03 and 105 are arranged substantially symmetrically with respect to the Z direction, the insulating substrate of the multilayer wiring board 107 is formed from a fiber sheet impregnated with a thermosetting resin that has low rigidity and is easily warped. However, it is possible to reduce the warp in the Z-axis direction. As a result, the semiconductor device according to the present invention can be formed in a state with less warpage, so that it can be easily mounted on another wiring board and residual stress after mounting can be reduced.

As described above, in the present embodiment, the electrical connection between the first and second semiconductor elements 101 and 103 and the third semiconductor element 105 is made via the multilayer wiring board 107. The elements can be connected regardless of the arrangement of the electrode terminals formed on each semiconductor element. Therefore, it becomes possible to use a general-purpose semiconductor element as it is and to make a connection similar to the chip-on-chip system. Also,
Compared to the case where semiconductor elements are connected using a wiring board having a conventional structure in which normal through holes are formed to form interlayer connection, three-dimensional wiring using inner via holes is used when the multilayer wiring board 107 is used. Can be formed, the wiring density can be increased, and the degree of freedom in interlayer connection is increased, so that the wiring can be easily routed. Therefore, when wiring is performed between the same semiconductor elements, the use of the multilayer wiring board 107 reduces the number of insulating layers to be stacked and shortens the wiring length, so that the semiconductor device can be downsized and The wiring length is short, which is also advantageous in increasing the speed of the semiconductor device. Further, since the semiconductor elements are not directly connected to each other, it is possible to prevent damage to other semiconductor elements when one semiconductor element is attached or detached, for example, damage caused by stress applied to the lead portion of the semiconductor element.
Furthermore, the semiconductor elements 101, 1 are sandwiched by the multilayer wiring board 107.
When 03 and 105 are arranged substantially symmetrically with respect to the Z direction, the insulating substrate of the multilayer wiring board 107 is formed from a fiber sheet impregnated with a thermosetting resin that has low rigidity and is easily warped. Also, it is possible to reduce the warp of the multilayer wiring board 107 in the Z-axis direction. In the present embodiment, the bonding portion 110 of the semiconductor element is formed by using the Au ball bump formed on the electrode terminal of the semiconductor element and the conductive adhesive, but the bump is formed by plating other than the wire bonding method. It may be formed by using a method, and at that time, it may be made of a conductive material other than Au. Further, cream solder may be used instead of the conductive adhesive. Alternatively, a configuration using solder bumps such as the C4 process adopted by Motorola may be used. The bumps may be formed on the multilayer wiring board 107, and an anisotropic conductive film (ACF) or the like may be used instead of the bumps. However, when an anisotropic conductive film is used, the defective semiconductor element is replaced by locally heating the anisotropic conductive film as needed.

Embodiment 2. FIG. 4 is a sectional view of a semiconductor device package according to a second embodiment of the present invention.
In the figure, the same reference numerals as those in FIG. 1 indicate the same or corresponding portions,
Reference numeral 112 is a mother wiring board on which a semiconductor device is mounted, 113 is a circuit pattern formed on the surface layer thereof, and 114 is an Au for electrically connecting the multilayer wiring board and the mother multilayer wiring board.
It is a wire. The mounting body according to the present embodiment is shown in FIG.
As shown in FIG. 3, the semiconductor device including the multilayer wiring board 107 on which the semiconductor element 101 and the like judged to be non-defective by the electrical inspection is mounted on the mother multilayer wiring board 112 at a predetermined position.
After the back surface of the semiconductor element 105 is adhered and fixed on the mother multilayer wiring board 112 with an adhesive or the like, the Au wire 1
14 is used to connect the circuit pattern 108 on the surface of the multilayer wiring board 107 and the circuit pattern 113 as on the surface of the mother multilayer wiring board 112 to manufacture. According to the present embodiment, since a semiconductor device having high quality and less warpage in the Z-axis direction is mounted on the mother multilayer wiring board, it is possible to realize a semiconductor device mounting body with extremely high quality and productivity. It can be manufactured. Further, since the semiconductor elements 101, 103, 105 mounted on the semiconductor device have a structure of being stacked in the Z-axis direction, the area of the mother wiring board can be reduced, and the electronic device that needs to be downsized. Can be applied to. In FIG. 4, the Au wire 114 is used as an electrical connecting means between the multilayer wiring board 107 and the mother multilayer wiring board 112. However, instead of the Au wire 114, a T wire is used.
AB (Tape Automoted Bondin
g) or the like may be used. In particular, in the present embodiment, the multilayer wiring board 107 used in the semiconductor device and the mother wiring board 112 are made of the same material, so that the physical constants such as the expansion coefficient of both wiring boards are also the same. Therefore, the stress applied to the third semiconductor element 105 sandwiched between the two wiring boards is also reduced, so that the quality of the mounting body can be improved.

Embodiment 3. FIG. 5 is a sectional view of a semiconductor device package according to a third embodiment of the present invention.
In the figure, the same reference numerals as those in FIG. 4 indicate the same or corresponding portions.
In the mounting body according to the present embodiment, the semiconductor device is mounted on the mother multilayer wiring board 11 by the same method as in the second embodiment.
Mounted on 2. Here, since the film thickness of the multilayer wiring board 107 constituting the semiconductor device is, for example, about 200 μm and has elasticity to some extent, the multilayer wiring board 107 is curved to connect the multilayer wiring board 107 directly to the mother wiring board. It becomes possible. Therefore, as shown in FIG.
By bending the multilayer wiring board 107 of the semiconductor device mounted on the mother multilayer wiring board 112 and directly connecting the circuit pattern on the mother multilayer wiring board 112 and the circuit pattern on the multilayer wiring board 107, both wiring boards are connected. It is electrically connected to produce a semiconductor device package. As a result, Au
It is possible to reduce the connecting material such as wires,
It is possible to reduce the manufacturing process of the mounting body, and it is possible to supply the mounting body of the semiconductor device which is low in cost and high in productivity.

Fourth Embodiment FIG. 6 is a sectional view of a semiconductor device package according to a fourth embodiment of the present invention.
In the figure, the same reference numerals as those in FIG. 4 indicate the same or corresponding portions,
Denoted at 115 is an electrical junction such as a protruding electrode. In the mounting body according to the present embodiment, the semiconductor device is mounted on the mother multilayer wiring board 112 by the same method as in the second embodiment. Next, as a connecting means for connecting the multilayer wiring board 107 of the semiconductor device and the mother multilayer wiring board 112, a protruding electrode 115 as shown in FIG. 6 is used. Such protruding electrode 1
The configuration of 15 includes the semiconductor element 101 and the like and the multilayer wiring board 107.
The structure is the same as that of the joint portion 110 used for connection with, that is, after forming the Au ball bump on the circuit pattern on the mother multilayer wiring board 112, a necessary amount of conductive adhesive is applied to the top of the bump portion. The multi-layer wiring board 10 is attached on top of it.
By overlapping the circuit patterns on 7, both wiring boards are electrically connected. If there is an exposed terminal of the electrode terminals 102, 104 of the first or second semiconductor element 101, 103 that is not covered with the multilayer wiring board 107, connect a bonding layer 115 such as a protruding electrode to this. Is also good. As described above, according to the present embodiment, since it is possible to connect the two wiring boards by effectively using the narrow area between the semiconductor device and the mother multilayer wiring board 112, it is possible to connect the semiconductors on the mother multilayer wiring board 112. The device can be mounted at high density,
It becomes possible to cope with miniaturization of electronic devices.

Embodiment 5. FIG. 7 is a cross-sectional view of a semiconductor device package according to a fifth embodiment of the present invention.
In the figure, the same reference numerals as those in FIG. 4 indicate the same or corresponding portions,
Reference numeral 116 represents a conductive support. In the semiconductor device package according to the present embodiment, the multilayer wiring board 107 of the semiconductor device is used.
Conductive support 1 such as a metal frame electrically connected to
16 is used to mount the semiconductor device on the mother multilayer wiring board 112. First, as shown in FIG. 7, the conductive support member 116 is electrically connected by using solder or the like after sandwiching the circuit pattern 108 on the multilayer wiring board 107 at the end portion of the multilayer wiring board 107. And physical fixation. The semiconductor device is electrically connected to the mother multilayer wiring board 112 via the conductive support 116.
According to the present embodiment, a semiconductor device provided with the conductive support 116 is treated as if it were a QFP (Quad Flat P).
mother multilayer wiring board 1
It is possible to perform mounting on the semiconductor device 12, and it becomes easy to inspect and mount the semiconductor device, and to replace it when a defect occurs.

Sixth Embodiment FIG. 8 is a cross-sectional view of a semiconductor device package according to a sixth embodiment of the present invention.
In the figure, the same reference numerals as those in FIG. 4 indicate the same or corresponding portions.
In the present embodiment, as shown in FIG. 8, first semiconductor element 101 and second semiconductor element 103 are connected to multilayer wiring board 10
The semiconductor having a structure in which the multilayer wiring board 107 is mounted so as to be opposed to each other via a curved line, and the multilayer wiring board 107 is bonded to the back surface with an adhesive or the like so as to cover the back surface of the second semiconductor element. It is a device. Further, such a semiconductor device is mounted on the mother multilayer wiring board 112 so that the circuit pattern on the multilayer wiring board 107 is electrically connected to the circuit pattern on the mother multilayer wiring board 112.
By adopting such a structure, it is not necessary to separately provide an electrical connecting means between the semiconductor device and the mother multilayer wiring board 112, so that it is possible to reduce the electrode material and the manufacturing process, and to lower the semiconductor device. Since it serves as an electrical connection means, the surface area of the mother multilayer wiring board 112 can be effectively utilized, high-density mounting of semiconductor devices can be achieved, and electronic devices can be miniaturized.

Embodiment 7. FIG. 9 is a sectional view of a semiconductor device according to the seventh embodiment of the present invention. In the figure, the same reference numerals as those in FIG. 4 indicate the same or corresponding portions. In this embodiment, as shown in FIG. 9, the first and second semiconductor elements 101 and 103 are flip-chip mounted so as to face each other with the multilayer wiring board 107 interposed therebetween, and then the multilayer wiring board 107 is curved. Then, the multilayer wiring board 107 is bonded to the back surface of the second semiconductor element 103 using an adhesive or the like so as to cover the back surface of the second semiconductor element 103. Further, the third semiconductor element 105 is flip-chip mounted on the multilayer wiring board 107 adhered to the back surface of the second semiconductor element 103 so as to face the second semiconductor element 103 via the multilayer wiring board 107. . As described above, in the semiconductor device according to the present embodiment, since the three semiconductor elements 101, 103, and 105 are stacked and mounted by bending the multilayer wiring board 107, it is possible to effectively use the mounting space, and the electronic device can be used effectively. It is possible to minimize the equipment. In this embodiment, the semiconductor elements are stacked and mounted in three stages.
By bending 07, it is possible to carry out stacked mounting in more stages.

Embodiment 8. FIG. 10 is a cross-sectional view of a semiconductor device package according to the eighth embodiment of the present invention. In the figure, the same reference numerals as those in FIG. 4 indicate the same or corresponding portions. As shown in FIG. 10, the mounting body according to the present embodiment is laminated and mounted using the multilayer wiring board 107 in which the first, second, and third semiconductor elements are curved according to the seventh embodiment. The semiconductor device is mounted on the mother multilayer semiconductor 112, and the multilayer wiring board 107 and the mother multilayer wiring board 112 are electrically connected to each other. The electrical connection between the multilayer wiring board 107 and the mother multilayer wiring board 112 is further achieved by a circuit pattern on the multilayer wiring board 107 and a circuit pattern on the mother multilayer wiring board 112 which are adhered so as to cover the back surface of the third semiconductor element. Directly connect and. According to the present embodiment, since the lower portion of the semiconductor device is electrically connected, the mounting area of the mother multilayer wiring board 112 can be effectively used, the mounting efficiency is improved, and the semiconductor device is improved. Since it is possible to multi-layer, it is possible to further improve the mounting efficiency. As a result, it becomes possible to supply a semiconductor device package that is extremely advantageous for minimizing electronic equipment.

Ninth Embodiment FIG. 11 is a perspective view of a semiconductor device according to a ninth embodiment of the present invention, in which a semiconductor element 201 having electrode terminals arranged in an area array on the upper surface of a multilayer wiring board 105 and a peripheral on the back surface thereof. A semiconductor element 203 (not shown) having electrode terminals arranged in a circle is mounted. In addition, FIG.
2 is a sectional view taken along line II-II ′ of FIG. In the figure, 201 is a first semiconductor element, 202 is an electrode terminal arrayed and formed in an area array on the element formation surface of the first semiconductor element 201,
Reference numeral 203 is a second semiconductor element, and 204 is an electrode terminal arranged and formed in a peripheral shape on the element formation surface of the second semiconductor element 203. Further, 107 is a multilayer wiring board, 108 is a circuit pattern formed on the surface of the multilayer wiring board 107,
9 is an inner via hole. Reference numeral 110 is a joint portion that electrically connects the semiconductor elements 201 and 203 and the circuit pattern 108 on the surface of the multilayer wiring board 107, and 111 is an insulating thermosetting resin.

In the present embodiment, as shown in FIG.
A semiconductor element having an electrode array having a peripheral electrode structure and a semiconductor element having an area array electrode array are mounted on both surfaces of the multilayer wiring board 107. Such an area array-like electrode array is an electrode structure that has been widely adopted especially in high-performance integrated circuits such as CPUs in order to achieve high speed and low power consumption of semiconductor elements.
However, when a semiconductor element having such an area array-shaped electrode array is mounted on a conventional multilayer wiring, the wiring length drawn from the center electrode of the electrodes arranged in the area array becomes long, which speeds up the semiconductor element. Was hindering Therefore, in the present embodiment, the electrodes arranged in an area array are connected to other semiconductor elements through the inner via holes 109 formed in the multilayer wiring board 107, whereby the wiring length can be shortened. I am trying.

In the process of manufacturing the semiconductor device shown in FIG.
First, the semiconductor element 2 having an area array electrode structure
01 and a semiconductor element 203 having a peripheral electrode structure are prepared, Au ball bumps are formed on the respective electrode terminals 202 and 204 using a wire bonding device, and then a necessary amount is formed on the top of the bumps. Attach the conductive adhesive of. Such conductive adhesives are Ag, Cu, N
It is formed from a mixture of a powder of a conductive metal such as i and a resin. In this way, the semiconductor element 201 in which the ball bumps of Au or the like are formed by the conductive adhesive is the multilayer wiring board 1
On the other hand, the semiconductor element 203 is face-down flip-chip mounted on the back surface of the multilayer wiring board 105 so as to face each other via the multilayer wiring board 107, and the adhesive is applied by heat treatment. Hardened, multilayer wiring board 1
Bonded on both sides of 07.

FIG. 14A shows an electrode structure of the semiconductor element 201 having an area array electrode array.
The circuit pattern on the multilayer wiring board 107 in which the semiconductor element 201 concerning (b) is mounted is shown. Also, 205 is Au
Shows the ball bump of. As shown in FIG. 14B, by using the multilayer wiring board 107 having the inner via holes 109, even with respect to the circuit pattern in the central portion of the area array circuit pattern, the circuit pattern is provided immediately below or near the circuit pattern. By providing the inner via hole 109 and performing three-dimensional wiring, the wiring length can be shortened.
Further, FIG. 15A shows a circuit pattern 108 on the back surface of the multilayer wiring board 107 on which the semiconductor element 203 is mounted, and FIG. 15B shows an electrode structure of the semiconductor element 203 having a peripheral electrode arrangement. . Even in the semiconductor element having the area array electrodes, as in the semiconductor element having the peripheral electrodes, after the conductive adhesive is cured and the semiconductor elements 201 and 203 are fixed on the multilayer wiring board 107, the electrical The semiconductor inspection confirms that each semiconductor element is a good product.

Next, after filling the gap between the semiconductor elements 201, 203 and the multilayer wiring board with the thermosetting resin 107, the thermosetting resin 107 is completely cured by heat treatment to enhance the mechanical strength and the connection strength. Increase. If the semiconductor element is judged to be defective in the electrical inspection, only the semiconductor element is removed and replaced with a new semiconductor element. At this time, the semiconductor element can be easily removed by adjusting the adhesive strength of the conductive adhesive to a necessary minimum. The adhesive strength is preferably about 3 × 10 ⁶ to 30 × 10 ⁶ N / m ² per bump.

As described above, in this embodiment, in addition to the effect described in the first embodiment, the semiconductor element 201 of the area array electrode structure and the peripheral electrode structure of the flip-chip mounted on both surfaces are provided. Since the electrical connection with the semiconductor element 203 is made via the multilayer wiring board 105 having the inner via holes 109 formed therein, the wiring length can be shortened, and the semiconductor device can operate at high speed and have low power consumption. Becomes In particular, in a semiconductor element having an area array-shaped electrode array, the wiring length of the electrode terminal located near the central portion of the semiconductor element can be significantly shortened as compared with a semiconductor device using a conventional wiring board. Becomes
It should be noted that a general mounting technique other than the flip-chip mounting technique shown in the first embodiment or the like can be applied to the present embodiment. It is also possible to mount semiconductor elements having an electrode array in the form of area array on both surfaces of the multilayer wiring board 107.

Embodiment 10. FIG. 16 shows the first aspect of the present invention.
3 is a cross-sectional view of a semiconductor device package according to Embodiment 0. In the figure, the same reference numerals as those in FIG. 1 indicate the same or corresponding portions, 130 is a bypass capacitor, and 131 is an electrode terminal of the bypass capacitor 130. As described above, in the present embodiment, the semiconductor element 201 having the area array electrode array is mounted on the upper surface of the multilayer wiring board 107, while
One or more bypass capacitors 131 are mounted on the back surface of the multilayer wiring board 107.

FIG. 17A shows an electrode structure of the semiconductor element 201 having an area array electrode structure.
The circuit pattern on the multilayer wiring board 107 in which the semiconductor element 201 concerning (b) is mounted is shown. Also, 205 is Au
Shows the ball bump of. In addition, in FIG. 18A, the multilayer wiring board 1 on which the six bypass capacitors 131 are mounted is shown.
The circuit pattern 108 on the back side of 07 is shown in FIG.
The electrode structure of six bypass capacitors is shown. Although the number of bypass capacitors 131 is six in the present embodiment, it may be any number as required.

As described above, in the semiconductor device according to the present embodiment, as in the case of the ninth embodiment, by using the multilayer wiring board 107 having the inner via holes 109, an area array circuit pattern is formed. Even for the circuit pattern in the central portion, the inner via hole 109 is provided immediately below or in the vicinity of the circuit pattern to perform three-dimensional wiring, whereby the wiring length can be shortened, and the semiconductor device can operate at high speed and have low power consumption. Is possible.

In particular, since the bypass capacitor 131 is provided to reduce the noise of the semiconductor device, if the wiring between the bypass capacitor 131 and the semiconductor element 201 becomes long, noise generated by such wiring will be generated. Therefore, the effect of providing the bypass capacitor 131 is canceled out. Therefore, by connecting the bypass capacitor 131 and the semiconductor element 131 with the three-dimensional wiring including the inner via hole 109, the wiring length can be shortened and the noise of the semiconductor device can be reduced.

[0042]

As is apparent from the above description, in the semiconductor device according to the present invention, the semiconductor elements are mounted so as to face each other with the multilayer wiring board interposed therebetween, and the electrode terminals of the semiconductor element are mounted in a three-dimensional wiring board. Since they are connected to each other by wiring, the elements can be connected regardless of the arrangement of the electrode terminals of the semiconductor element, and general-purpose semiconductor elements can be used as they are and connection similar to the chip-on-chip method can be made. By doing so, it is possible to provide a miniaturized and faster semiconductor device.

Further, in the present invention, a multilayer wiring board is used in place of the ordinary printed wiring board, and the wiring length is increased in order to connect the semiconductor elements by the three-dimensional wiring using the inner via holes which can easily route the wiring. Can be shortened, delay in response speed due to increase in wiring length can be prevented, and the speed of the semiconductor device can be increased.

Further, since the semiconductor elements are not directly connected to each other, it is possible to prevent damage to other semiconductor elements when the one semiconductor element is attached or detached.

By mounting the semiconductor device on a mother multilayer wiring board, a high-density mounting body can be formed, which contributes to downsizing of electronic equipment.

Further, even when a semiconductor element having area array electrode terminals is flip-chip mounted by the face-down method, the wiring is performed through the multilayer wiring board 105 in which the inner via holes 109 are formed. The semiconductor device can be shortened, and the semiconductor device can have higher speed and lower power consumption.

In particular, in a semiconductor element having an area array-shaped electrode terminal array, the wiring length of the electrode terminals located near the central portion of the semiconductor element is greatly shortened as compared with a semiconductor device using a conventional wiring board. It becomes possible to do.

Further, by connecting the bypass capacitor and the semiconductor element with a three-dimensional wiring consisting of inner via holes, the wiring length can be shortened and the noise of the semiconductor device can be reduced.

[Brief description of drawings]

FIG. 1A is a perspective view of a semiconductor device according to a first embodiment of the present invention. (B) It is sectional drawing in II 'of FIG.1 (a).

2A, 2B, and 2E are arrangements of bumps formed on the semiconductor element according to the first embodiment of the present invention. (C) (d) Circuit patterns of the multilayer wiring board according to the first exemplary embodiment of the present invention.

FIG. 3 is a top view of the semiconductor device according to the first embodiment of the present invention.

FIG. 4 is a sectional view of a semiconductor device package according to a second embodiment of the present invention.

FIG. 5 is a cross-sectional view of a semiconductor device package according to a third embodiment of the present invention.

FIG. 6 is a cross-sectional view of a semiconductor device package according to a fourth embodiment of the present invention.

FIG. 7 is a cross-sectional view of a semiconductor device package according to a fifth embodiment of the present invention.

FIG. 8 is a cross-sectional view of a semiconductor device package according to a sixth embodiment of the present invention.

FIG. 9 is a sectional view of a semiconductor device according to a seventh embodiment of the present invention.

FIG. 10 is a sectional view of a semiconductor device package according to an eighth embodiment of the present invention.

FIG. 11 is a perspective view of a semiconductor device according to a ninth embodiment of the present invention.

12 is a cross-sectional view taken along the line II-II ′ of FIG.

FIG. 13 is an electrode array of a semiconductor element.

FIG. 14A is an electrode array of a semiconductor element having an electrode array in the form of an area array. (B) A circuit pattern of a multilayer wiring board on which a semiconductor element having an area array electrode array is mounted.

FIG. 15A is a circuit pattern of a multilayer wiring board on which a semiconductor element having a peripheral electrode array is mounted. (B) An electrode array of a semiconductor device having a peripheral electrode array.

FIG. 16 is a sectional view of a semiconductor device according to a tenth embodiment of the present invention.

FIG. 17 (a) is an electrode array of a semiconductor element having an electrode array in the form of an area array. (B) A circuit pattern of a multilayer wiring board on which a semiconductor element having an area array electrode array is mounted.

FIG. 18 (a) is a circuit pattern of a multilayer wiring board on which a bypass capacitor is mounted. (B) The electrode arrangement of the bypass capacitor.

FIG. 19 is a cross-sectional view of a conventional chip-on-chip semiconductor device.

[Explanation of symbols]

1, 101 first semiconductor element, 2, 102 electrode terminals formed on first semiconductor element, 3, 103 second semiconductor element, 4, 104 electrode terminals formed on second semiconductor element, 5, 105 Third semiconductor device, 6, 106
Electrode terminals formed on the third semiconductor element, 7, 107
Multilayer wiring board, 8,108 Circuit pattern on multilayer wiring board, 9,109 Inner via holes, 10,110,1
15 electrical junction, 11, 111 insulating substrate, 12,
112 mother multilayer wiring board, 13, 113 circuit pattern on mother multilayer wiring board, 114 Au wire, 11
6 conductive support, 130 bypass capacitor, 130
By-pass capacitor electrode, 201 first semiconductor element, 202 first semiconductor element area array electrode terminal, 203 second semiconductor element, 204 second semiconductor element peripheral electrode terminal, 205 ball bump.

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[Procedure amendment]

[Submission date] June 4, 2003 (2003.6.4)

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] Full text

[Correction method] Change

[Correction content]

[Document name] Statement

Patent application title: Semiconductor device mounting body

[Claims]

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device mounting body having semiconductor elements on both sides of a multilayer wiring board having a three-dimensional wiring using inner via holes.

[0002]

2. Description of the Related Art In order to miniaturize electronic equipment using semiconductor elements, semiconductor elements in which a plurality of electronic circuits are incorporated in a single semiconductor element have been developed. However, it is difficult to give all the functions to a single semiconductor element due to restrictions such as design rules, and it is often necessary to use a plurality of semiconductor elements. In such a case, in order to reduce the size and increase the speed, as shown in FIG. 19, a chip-on-chip configuration is used in which semiconductor elements are directly connected to each other by using electrode portions.
In the figure, 1 is a first semiconductor element, 2 is a first semiconductor element 1
Formed on the electrode terminals, 3 is a second semiconductor element, and 4 is a second semiconductor element.
2. The electrode terminals formed on the semiconductor element 3 of FIG. 10 are joints mainly made of a conductive metal material such as solder, and 11 is a cured insulating resin. In this way, by adopting the chip-on-chip configuration, the wiring length between the elements can be shortened, the transmission delay of electric signals can be reduced, the speed of the semiconductor device can be increased, and the semiconductor elements can be stacked. Therefore, the semiconductor device can be downsized.

[0003]

In such a chip-on-chip structure, when the first semiconductor element 1 and the second semiconductor element 3 are electrically connected via the joint portion 10, each semiconductor is connected. It is necessary to arrange the electrode terminals 2 and 3 of the element at positions facing each other. For this reason, a general-purpose semiconductor element cannot be used, and the electrode terminals 2, 3 are previously formed.
It is necessary to use a semiconductor device designed in consideration of the position of, and the design and development of the semiconductor device becomes indispensable separately. Further, since the positions of the electrode terminals 2 and 3 of the first and second semiconductor elements are limited, it may be difficult to reduce the size of the semiconductor device, which leads to a reduction in manufacturing yield. Therefore,
An object of the present invention is to provide a semiconductor device capable of high-speed operation and miniaturization by using a general-purpose semiconductor element without using a chip-on-chip structure. In particular, the electrode arrangement of the semiconductor element is an area array type C.
An object of the present invention is to provide a semiconductor device in which the wiring length does not become long and high-speed operation and miniaturization are possible even when a semiconductor element such as PU is used.

[0004]

According to a first aspect of the present invention, an insulating layer and a circuit pattern layer are laminated on both surfaces of the insulating layer through a plurality of inner via holes provided through the insulating layer. A multilayer wiring board provided with a three-dimensional wiring to which the circuit pattern layer is electrically connected; a first semiconductor element and a second semiconductor element; and a mother multilayer wiring board having a circuit pattern on the surface. The first semiconductor element is mounted on the upper surface of the multilayer wiring board, and the second semiconductor element is provided between the lower surface of the multilayer wiring board and the surface of the mother multilayer wiring board. The semiconductor element and the second semiconductor element are electrically connected to each other, and a short portion of the multilayer wiring board is curved toward the mother multilayer wiring board to thereby form a circuit pattern on the multilayer wiring board and the mother multilayer wiring board. Circuit pattern on wiring board And down a mounting body of the semiconductor device are electrically connected.

According to a second aspect of the present invention, an insulating layer and a circuit pattern layer are laminated, and the insulating layer and the circuit pattern layer are provided on both sides of the insulating layer through a plurality of inner via holes provided through the insulating layer. A multilayer wiring board having a three-dimensional wiring in which circuit pattern layers are electrically connected, a first semiconductor element and a second semiconductor element, a mother multilayer wiring board having a circuit pattern on the surface, and the multilayer wiring board And a protruding electrode for electrically connecting the mother multilayer wiring board, the first semiconductor element is mounted on the upper surface of the multilayer wiring board, and the second semiconductor element is the multilayer wiring board. The first semiconductor element and the second semiconductor element are electrically connected to each other between the lower surface and the surface of the mother multilayer wiring board, and the circuit pattern on the multilayer wiring board and the mother multilayer wiring board. The upper circuit pattern is A mounting body of the semiconductor device are electrically connected by the protruding electrodes.

As described above, in the semiconductor device according to the present invention, it is possible to form a miniaturized semiconductor device having a chip-on-chip structure by using a general-purpose semiconductor element. Therefore, by using the present invention, even when a general-purpose semiconductor element is used, the conventional chip-on-chip
As in the case of using the chip structure, it is possible to downsize the semiconductor device and speed up the element operation while preventing the delay of the electric signal due to the shortened wiring length. In addition, since the multilayer wiring board is arranged between the semiconductor elements, stress is not applied to the other semiconductor element when each semiconductor element is attached or detached, and the occurrence of damage can be suppressed. Also,
By mounting on a mother multilayer wiring board, it is possible to form a high-density package, and in addition to manufacturing semiconductor devices in advance, inspecting quality, reliability, etc., only good semiconductor devices are placed on the mother multilayer wiring board. It becomes possible to improve the productivity of the mounting body by mounting the mounting body on the mounting body. Further, by bending the multilayer wiring board of the semiconductor device and forming the connecting means, it is possible to reduce the electrode forming process and reduce the production cost. In addition, by using the protruding electrode as an electrical connecting means between the multilayer wiring board and the mother multilayer wiring board, it is possible to form the connecting means using an empty space between the multilayer wiring board of the semiconductor device and the mother multilayer wiring board. It becomes possible, and the mounting body of the semiconductor device can be downsized.

Further, the present invention is characterized in that the electrode terminals of at least one of the first and second semiconductor elements are formed so as to be arranged in an area array. But also. In the multilayer wiring board according to the present invention, since the three-dimensional wiring using the inner via holes is used, the wiring connecting the semiconductor elements provided on both surfaces of the multilayer wiring board can be a three-dimensional three-dimensional wiring. Become. Therefore, the wiring is laid on the substrate plane,
The wiring length can be shortened as compared with a normal wiring board in which the wiring is two-dimensional. Therefore, it is effective when mounting a semiconductor element having a structure having electrode terminals not only in the peripheral portion of the semiconductor element but also in the vicinity of the central portion, such as a semiconductor element in which electrodes are arranged in an area array.

Further, according to the present invention, the electrode terminals are formed in an area array shape on each surface of the multilayer wiring board.
And a second semiconductor element in which the electrode terminals are formed in a peripheral shape are face-down flip-chip mounted, and between the electrode terminals of the semiconductor element,
It is also a semiconductor device characterized by being connected by the three-dimensional wiring. As described above, in the semiconductor device according to the present invention, the semiconductor element is flip-chip mounted face down through the thin multilayer wiring board. Therefore, the semiconductor element is flip-chip mounted to reduce the size of the semiconductor device. Can be formed. Further, since the three-dimensional wiring using the inner via holes is used in the multilayer wiring board, the wiring connecting the semiconductor elements provided on both surfaces of the multilayer wiring board can be three-dimensional wiring. Therefore, the wiring is laid out on the plane of the substrate, and the wiring length can be shortened as compared with the case of using an ordinary wiring board which is a two-dimensional wiring. Therefore, by using the present invention, it is possible to reduce the size of the semiconductor device even when a semiconductor element having electrodes arranged in an area array type is mounted. Further, by shortening the wiring length, it is possible to prevent the delay of the electric signal and increase the operating speed, and it is also possible to reduce the power consumption by reducing the resistance of the wiring.

Further, according to the present invention, a semiconductor element having the electrode terminals formed in an area array is flip-chip mounted face down on one surface of the multilayer wiring board, and the other surface of the multilayer wiring board. An electronic part is mounted on the semiconductor device, and the electrode terminal of the semiconductor element and the electrode terminal of the electronic part are connected by the three-dimensional wiring. As described above, in the semiconductor device according to the present invention, since the three-dimensional wiring using the inner via holes is used in the multilayer wiring board, semiconductor elements and electronic components such as bypass capacitors provided on both surfaces of the multilayer wiring board are used. Since the three-dimensional wiring can be connected to each other, the wiring can be laid out on the plane of the board, and the wiring length can be shortened as compared with the case of using a normal wiring board that is a two-dimensional wiring. Become. Therefore, it is possible to effectively remove noise components during high-speed driving. In particular, when connecting an electrode in the central portion of a semiconductor element in which electrodes are arranged in an area array and an electronic component, the wiring length can be significantly shortened as compared with the case where a conventional wiring board is used. Become.

The electronic component is preferably a bypass capacitor. When a bypass capacitor is used as the electronic component, the noise of the wiring portion can be reduced by shortening the wiring length, so that the noise can be effectively removed by the bypass capacitor.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference Example 1 FIG. 1 shows a semiconductor device according to a first reference example of the present invention, in which two semiconductor elements are provided on one side and one semiconductor element is provided on the other side. 2A and 2B show semiconductor devices respectively mounted with. 1A is a perspective view of the semiconductor device, and FIG. 1B is a cross-sectional view of the semiconductor device shown in FIG. 10 in the figure
1 is a first semiconductor element, 102 is a first semiconductor element 10
1 is an electrode terminal formed on the element formation surface, 103 is a second semiconductor element, 105 is a third semiconductor element, 104, 10
Reference numeral 6 is an electrode terminal formed on each semiconductor element, 107 is a multilayer wiring board, 108 is a surface layer circuit pattern formed on the multilayer wiring board, and 109 is an inner via hole. Also,
Reference numeral 110 is a joint for electrically connecting the semiconductor elements 101, 103, 105 and the circuit pattern 108 on the surface layer of the multilayer wiring board 107, and 111 is an insulating thermosetting resin.

In the process of manufacturing the semiconductor device shown in FIG. 1, first, three semiconductor elements 101, 103 and 105 are prepared, and Au ball bumps are formed on the surfaces of the electrode terminals 102, 104 and 106 using a wire bonding device. After forming, the required amount of conductive adhesive is attached to the top of the. Such a conductive adhesive is made of a mixture of a powder of a conductive metal such as Ag, Cu and Ni and a resin. In this way, the semiconductor elements 101 and 103 on which the ball bumps of Au or the like are formed by attaching the conductive adhesive to the multilayer wiring board 107 are used.
On the front surface of the semiconductor element 105, the semiconductor elements 105 are sequentially face-down flip-chip mounted on the back surface of the multilayer wiring board 107 so as to face each other via the multilayer wiring board 107.
The heat treatment cures the adhesive and bonds it onto the multilayer wiring board 107.

Here, in FIG. 2 (a) (b) (e), the first
Of the bumps provided on the back surfaces of the semiconductor element 101, the second semiconductor element 103, and the third semiconductor element 105 of
2C and 2D show circuit patterns on the upper surface and the back surface of the multilayer wiring board 107 on which these semiconductor elements are mounted,
Show each. The bumps a1, a2, a3 ... Formed on the back surface of the first semiconductor element 101 and the bumps b1, b2, b3 ... Formed on the back surface of the second semiconductor element 103.
Are the electrodes x1, x2 on the upper surface of the multilayer wiring board 107,
, and x11, x12, x13, ... On the other hand, the bumps c1, c2, c3 ... Formed on the back surface of the third semiconductor element 105 are connected to the electrodes y1, y2, y3 ... On the lower surface of the multilayer wiring board 107. Furthermore, the electrodes x1 and y formed on the upper surface and the lower surface of the multilayer wiring board 107 are formed by the three-dimensional wiring of the multilayer wiring board 107.
1, x2 and y2, x3 and y3 ... Are electrically connected to each other. Therefore, by mounting the first and second semiconductor elements 101, 102 and the third semiconductor element 105 on both surfaces of the multilayer wiring board 107, the three-dimensional wiring of the multilayer wiring board 107 can be provided between the electrode terminals of each semiconductor element. It is possible to form a laminated structure similar to the conventional chip-on-chip structure by being electrically connected to each other. still,
By curing the conductive adhesive, the semiconductor elements 101, 103,
After fixing 105 on the multilayer wiring board 107, an electrical inspection is performed to confirm that each semiconductor element is a good product.

Next, the semiconductor elements 101, 103, 105
Insulating thermosetting resin 1 in the gap between the wiring board and the multilayer wiring board 107
After the filling with 11, the thermosetting resin 111 is completely cured by heat treatment to enhance mechanical strength and connection quality.
If the semiconductor element is judged to be defective in the electrical inspection, only the semiconductor element is removed and replaced with a new semiconductor element. At this time, the semiconductor element can be easily removed by adjusting the adhesive strength of the conductive adhesive to a necessary minimum. The adhesive strength is 3 × 10 ⁶ to 30 × 10 ⁶ N / m per bump.
^{About 2} is preferable.

The above-mentioned multilayer wiring board 107 is disclosed in JP-A-6-2.
No. 68345, an insulating substrate made of a resin-impregnated fiber sheet and a circuit pattern are alternately laminated, and a conductive inner via hole penetrating the insulating substrate and the circuit pattern are electrically connected to each other. A multilayer wiring board that forms a three-dimensional wiring connected to is used. In particular, the insulating substrate of the multilayer wiring board 107 is preferably composed of a fiber sheet such as glass cloth or aramid cloth impregnated with a thermosetting resin. This is because a fiber sheet impregnated with a thermosetting resin has a smaller Young's modulus than a wiring board using an inorganic substrate such as a ceramic as an insulating substrate, and therefore stresses applied to a mounted semiconductor element or a connecting portion are small. This is because it is reduced.
In addition, since the coefficient of thermal expansion can be reduced by including the filler such as glass cloth or aramid cloth, the thermal stress applied to the semiconductor element and the connecting portion can be reduced also by this. As described above, by using a fiber sheet such as a glass cloth or an aramid cloth impregnated with a thermosetting resin as the material forming the insulating substrate of the multilayer wiring board 107,
The stress applied to the semiconductor element and the connecting portion is reduced, and a high quality semiconductor device can be formed.

FIG. 3 is a plan view of the semiconductor device according to the present reference example as viewed from the first semiconductor element 101 side. In the figure, the same reference numerals as those in FIG. 1 designate the same or corresponding parts. Show. As can be seen from FIG. 3, in this reference example, the projection surface of the semiconductor elements 101 and 103 in the direction perpendicular to the wiring formation surface of the multilayer wiring board 107 (Z direction) is the semiconductor element 105 mounted on the back surface. The multilayer wiring board 107 has a structure in which it at least partially overlaps the projection surface in the direction perpendicular to the wiring formation surface. Semiconductor elements 101, 103, 1
By arranging 05 in such a configuration, the semiconductor device according to the present reference example has a configuration that is substantially symmetrical with respect to the Z direction with the multilayer wiring board 107 interposed therebetween. In this way, the semiconductor elements 101, 103, 105 are sandwiched by the multilayer wiring board 107.
Are arranged substantially symmetrically with respect to the Z direction, even when the insulating substrate of the multilayer wiring board 107 is formed from a fiber sheet impregnated with a thermosetting resin that has low rigidity and is easily warped, It is possible to reduce warpage in the Z-axis direction. Thereby, the semiconductor device according to the present reference example,
Since it can be formed in a state with less warpage, it can be easily mounted on another wiring board, and residual stress after mounting can be reduced.

As described above, in this reference example, the electrical connection between the first and second semiconductor elements 101 and 103 and the third semiconductor element 105 is made via the multilayer wiring board 107. The elements can be connected regardless of the arrangement of the electrode terminals formed on each semiconductor element. Therefore, it becomes possible to use a general-purpose semiconductor element as it is and to make a connection similar to the chip-on-chip system. Further, as compared with the case where semiconductor elements are connected using a wiring board having a conventional structure in which normal through holes are formed to form interlayer connections, inner via holes are used when the multilayer wiring board 107 is used. Since three-dimensional wiring can be formed, the wiring density can be increased, and the degree of freedom in interlayer connection is increased, the wiring can be easily routed. Therefore, when wiring between the same semiconductor elements, the use of the multilayer wiring board 107 reduces the number of layers of insulating layers to be laminated and shortens the wiring length.
The semiconductor device can be downsized, and the wiring length is short, which is also advantageous in increasing the speed of the semiconductor device. Further, since the semiconductor elements are not directly connected to each other, it is possible to prevent damage to other semiconductor elements when one semiconductor element is attached or detached, for example, damage caused by stress applied to the lead portion of the semiconductor element. Furthermore,
The semiconductor elements 101, 103, sandwiching the multilayer wiring board 107,
By arranging 105 substantially symmetrically with respect to the Z direction, even when the insulating substrate of the multilayer wiring board 107 is formed from a fiber sheet impregnated with a thermosetting resin having small rigidity and easily warping, It is possible to reduce the warp of the multilayer wiring board 107 in the Z-axis direction. In this reference example, the bonding portion 110 of the semiconductor element is formed by using the Au ball bump formed on the electrode terminal of the semiconductor element and the conductive adhesive. May be used, and in that case, a conductive material other than Au may be used. Further, cream solder may be used instead of the conductive adhesive. Alternatively, a configuration using solder bumps such as the C4 process adopted by Motorola may be used. The bumps may be formed on the multilayer wiring board 107, and an anisotropic conductive film (ACF) or the like may be used instead of the bumps. However, when an anisotropic conductive film is used, the defective semiconductor element is replaced by locally heating the anisotropic conductive film as needed.

Reference Example 2 FIG. 4 is a sectional view of a semiconductor device package according to a second reference example of the present invention. In the figure,
The same reference numerals as those in FIG.
Is a mother wiring board on which the semiconductor device is mounted, 113 is a circuit pattern formed on the surface layer thereof, and 114 is an Au wire for electrically connecting the multilayer wiring board and the mother multilayer wiring board. As shown in FIG. 4, the mounting body according to the present reference example has a semiconductor device including a multilayer wiring board 107 on which semiconductor elements 101 and the like, which are judged to be non-defective by an electrical inspection, are mounted on a mother multilayer wiring board 112. After fixing the back surface of the third semiconductor element 105 onto the mother multilayer wiring board 112 with an adhesive or the like at a position, the Au wiring 114 is used to fix the circuit pattern 108 on the surface of the multilayer wiring board 107 and the mother multilayer. Circuit pattern 11 such as the surface of wiring board 112
3 is connected and produced. According to the present reference example, since a semiconductor device having high quality and less warpage in the Z-axis direction is mounted on the mother multilayer wiring board, it is possible to manufacture a semiconductor device package having extremely high quality and productivity. Is possible. In addition, the semiconductor element 10 mounted on the semiconductor device
Since Nos. 1, 103, and 105 are laminated in the Z-axis direction, the area of the mother wiring board can be reduced,
It can be applied to electronic devices that require miniaturization.
In FIG. 4, the multilayer wiring board 107 and the mother multilayer wiring board 1 are shown.
Although the Au wire 114 was used as an electrical connecting means with the wire 12, instead of the Au wire 114, the TAB (T
Ape Automated Bonding) or the like may be used. In particular, in the present reference example, the materials of the multilayer wiring board 107 used in the semiconductor device and the mother wiring board 112 are the same, so that the physical constants such as the expansion coefficient of both wiring boards are the same. Therefore, the stress applied to the third semiconductor element 105 sandwiched between the two wiring boards is also reduced, so that the quality of the mounting body can be improved.

(First Embodiment) FIG. 5 is a cross-sectional view of a semiconductor device package according to a first embodiment of the present invention. In the figure, the same reference numerals as those in FIG. 4 indicate the same or corresponding portions. In the mounting body according to the present embodiment, the semiconductor device is mounted on the mother multilayer wiring board 112 by the same method as in the second reference example. Here, since the film thickness of the multilayer wiring board 107 which constitutes the semiconductor device is, for example, about 200 μm and has elasticity to some extent, the multilayer wiring board 107 is provided.
Can be curved to connect the multilayer wiring board 107 directly to the mother wiring board. Therefore, as shown in FIG. 5, the multilayer wiring board 107 of the semiconductor device mounted on the mother multilayer wiring board 112 is curved, and the mother multilayer wiring board 112 is bent.
By directly connecting the upper circuit pattern and the circuit pattern on the multilayer wiring board 107, both wiring boards are electrically connected to each other to fabricate a semiconductor device package. This allows
It is possible to reduce the amount of connecting material such as Au wire and also reduce the manufacturing process of the mounting body, and it is possible to supply the mounting body of the semiconductor device at low cost and with high productivity.

(Second Embodiment) FIG. 6 is a sectional view of a semiconductor device package according to a second embodiment of the present invention. In the figure, the same reference numerals as those in FIG. 4 indicate the same or corresponding portions, and 115 indicates an electrical connection portion such as a protruding electrode. In the mounting body according to the present embodiment, the semiconductor device is mounted on the mother multilayer wiring board 112 by the same method as in the second reference example. Next, as connecting means for connecting the multilayer wiring board 107 of the semiconductor device and the mother multilayer wiring board 112, as shown in FIG.
As shown in FIG. The structure of the protruding electrode 115 is the same as that of the semiconductor element 101 and the multilayer wiring board 1.
No. 07 has the same structure as that of the joint portion 110 used for connection with 07, that is, after the Au ball bump is formed on the circuit pattern on the mother multilayer wiring board 112, a necessary amount of the conductive adhesive is provided on the top of the bump. On the multi-layer wiring board 1
By overlapping the circuit pattern on 07, both wiring boards are electrically connected. If there is an exposed terminal of the electrode terminals 102, 104 of the first or second semiconductor element 101, 103 that is not covered with the multilayer wiring board 107, connect a bonding layer 115 such as a protruding electrode to this. Is also good. As described above, according to the present embodiment, since it is possible to connect the two wiring boards by effectively using the narrow area between the semiconductor device and the mother multilayer wiring board 112, it is possible to connect the semiconductors on the mother multilayer wiring board 112. The device can be mounted at high density,
It becomes possible to cope with miniaturization of electronic devices.

Reference Example 3 FIG. 7 is a sectional view of a semiconductor device package according to a third reference example of the present invention. In the figure,
The same reference numerals as those in FIG.
Indicates a conductive support. In the semiconductor device package according to the present reference example, the semiconductor device is mounted on the mother multilayer wiring board 112 by using the conductive support 116 such as a metal frame electrically connected to the multilayer wiring board 107 of the semiconductor device. To do. First, the conductive support 116 is, as shown in FIG.
At the end of the multilayer wiring board 107, the circuit pattern 108 on the multilayer wiring board 107 is sandwiched, and then electrical connection and physical fixing are performed using solder or the like.
The semiconductor device is electrically connected to the mother multilayer wiring board 112 via the conductive support 116. According to the present embodiment, the semiconductor device provided with the conductive support 116 is treated as if it were a QFP (Quad Flat Packa).
ge), it becomes possible to carry out mounting on the mother multilayer wiring board 112, and it becomes easy to inspect and mount the semiconductor device, and replace it when a defect occurs.

Reference Example 4 FIG. 8 is a sectional view of a semiconductor device package according to a fourth reference example of the present invention. In the figure,
The same reference numerals as those in FIG. 4 indicate the same or corresponding portions. In this reference example, as shown in FIG. 8, the first semiconductor element 101 and the second semiconductor element 103 are mounted so as to face each other with the multilayer wiring board 107 interposed therebetween, and the multilayer wiring board 107 is further curved. Thus, the semiconductor device has a structure in which the multilayer wiring board 107 is adhered to the back surface of the second semiconductor element with an adhesive or the like so as to cover the back surface of the second semiconductor element. Further, such a semiconductor device is mounted on the mother multilayer wiring board 112 so that the circuit pattern on the multilayer wiring board 107 is electrically connected to the circuit pattern on the mother multilayer wiring board 112. By adopting such a structure, the semiconductor device and the mother multilayer wiring board 11
Since it is not necessary to separately provide an electrical connecting means with the second device, it is possible to reduce the electrode material and the manufacturing process, and the lower portion of the semiconductor device serves as the electrical connecting means.
The surface area of the mother multilayer wiring board 112 can be effectively utilized, high-density mounting of semiconductor devices can be achieved, and electronic devices can be miniaturized.

Reference Example 5 FIG. 9 is a sectional view of a semiconductor device according to a fifth reference example of the present invention. In the figure, the same reference numerals as those in FIG. 4 indicate the same or corresponding portions. In this reference example,
As shown in FIG. 9, first and second semiconductor elements 101, 1
03 are flip-chip mounted so as to face each other with the multilayer wiring board 107 in between, and then the multilayer wiring board 107 is curved,
The multilayer wiring board 107 is bonded to the back surface of the second semiconductor element 103 with an adhesive or the like so as to cover the back surface of the second semiconductor element 103. Further, on the multilayer wiring board 107 adhered to the back surface of the second semiconductor element 103, the third wiring board 107 is provided so as to face the second semiconductor element 103 via the multilayer wiring board 107.
The semiconductor element 105 is flip-chip mounted. Thus, in the semiconductor device according to the present reference example, the multilayer wiring board 1
By bending 07, the three semiconductor elements 10
Since 1, 103, and 105 are stacked and mounted, the mounting space can be effectively utilized, and the electronic device can be minimized. In this reference example, the semiconductor elements are stacked and mounted in three stages, but by further bending the multilayer wiring board 107, it is possible to mount and stack in more stages.

Reference Example 6 FIG. 10 is a sectional view of a semiconductor device package according to a sixth reference example of the present invention. In the figure, the same reference numerals as those in FIG. 4 indicate the same or corresponding portions. As shown in FIG. 10, the mounting body according to the present reference example is a semiconductor in which the first, second, and third semiconductor elements are stacked and mounted using the curved multilayer wiring board 107 according to the seventh embodiment. The device is mounted on the mother multilayer semiconductor 112, and the multilayer wiring board 107 and the mother multilayer wiring board 112 are electrically connected and formed. Multilayer wiring board 107 and mother multilayer wiring board 1
The electrical connection with 12 is further made by directly connecting the circuit pattern on the multilayer wiring board 107 and the circuit pattern on the mother multilayer wiring board 112, which are adhered so as to cover the back surface of the third semiconductor element. According to this reference example, since electrical connection is made using the lower portion of the semiconductor device, the mounting area of the mother multilayer wiring board 112 can be effectively utilized, the mounting efficiency is improved, and the semiconductor device Since multiple layers are possible, it is possible to further improve the mounting efficiency. This allows
It becomes possible to supply a package of a semiconductor device, which is extremely advantageous for minimizing electronic equipment.

Reference Example 7 FIG. 11 is a perspective view of a semiconductor device according to Reference Example 7, in which a semiconductor element 201 having electrode terminals arranged in an area array on the upper surface of a multilayer wiring board 105 is provided on the back surface. Is mounted with a semiconductor element 203 (not shown) having electrode terminals arranged in a peripheral shape. FIG. 12 is a sectional view taken along line II-II ′ of FIG. 11. In the figure, 201 is a first semiconductor element,
Reference numeral 202 denotes electrode terminals arrayed and formed in an area array on the element formation surface of the first semiconductor element 201, 203 a second semiconductor element, and 204, peripherally arranged and formed on the element formation surface of the second semiconductor element 203. It is the electrode terminal.
Further, 107 is a multilayer wiring board, and 108 is a multilayer wiring board 107.
A circuit pattern 109 is formed on the surface of the inner via hole. 110 is a semiconductor element 201, 203
And a bonding portion for electrically connecting the circuit pattern 108 on the surface of the multilayer wiring board 107, and 111 is an insulating thermosetting resin.

In this reference example, as shown in FIG. 13, a semiconductor element having an electrode array having an electrode structure of a peripheral and a semiconductor element having an electrode array of an area array are mounted on both surfaces of a multilayer wiring board 107. To do. Such an area array-like electrode array is an electrode structure that has been widely adopted especially in high-performance integrated circuits such as CPUs in order to achieve high speed and low power consumption of semiconductor elements.
However, when a semiconductor element having such an area array-shaped electrode array is mounted on a conventional multilayer wiring, the wiring length drawn from the center electrode of the electrodes arranged in the area array becomes long, which speeds up the semiconductor element. Was hindering Therefore, in this reference example, the electrodes arranged in an area array are connected to other semiconductor elements through the inner via holes 109 formed in the multilayer wiring board 107, thereby making it possible to shorten the wiring length. There is.

In the process of manufacturing the semiconductor device shown in FIG.
First, the semiconductor element 2 having an area array electrode structure
01 and a semiconductor element 203 having a peripheral electrode structure are prepared, Au ball bumps are formed on the respective electrode terminals 202 and 204 using a wire bonding device, and then a necessary amount is formed on the top of the bumps. Attach the conductive adhesive of. Such conductive adhesives are Ag, Cu, N
It is formed from a mixture of a powder of a conductive metal such as i and a resin. In this way, the semiconductor element 201 in which the ball bumps of Au or the like are formed by the conductive adhesive is the multilayer wiring board 1
On the other hand, the semiconductor element 203 is face-down flip-chip mounted on the back surface of the multilayer wiring board 105 so as to face each other via the multilayer wiring board 107, and the adhesive is applied by heat treatment. Hardened, multilayer wiring board 1
Bonded on both sides of 07.

FIG. 14A shows an electrode structure of a semiconductor element 201 having an area array electrode array, and FIG.
The circuit pattern on the multilayer wiring board 107 in which the semiconductor element 201 concerning (b) is mounted is shown. Also, 205 is Au
Shows the ball bump of. As shown in FIG. 14B, by using the multilayer wiring board 107 having the inner via holes 109, even with respect to the circuit pattern in the central portion of the area array circuit pattern, the circuit pattern is provided immediately below or near the circuit pattern. By providing the inner via hole 109 and performing three-dimensional wiring, the wiring length can be shortened.
Further, FIG. 15A shows a circuit pattern 108 on the back surface of the multilayer wiring board 107 on which the semiconductor element 203 is mounted.
5 (b) shows an electrode structure of the semiconductor element 203 having a peripheral electrode array. Even in the semiconductor element having the area array electrodes, as in the semiconductor element having the peripheral electrodes, after the conductive adhesive is cured and the semiconductor elements 201 and 203 are fixed on the multilayer wiring board 107, the electrical The semiconductor inspection confirms that each semiconductor element is a good product.

Next, after filling the gaps between the semiconductor elements 201, 203 and the multilayer wiring board with the thermosetting resin 107, the thermosetting resin 107 is completely cured by heat treatment to enhance the mechanical strength and the connection strength. Increase. If the semiconductor element is judged to be defective in the electrical inspection, only the semiconductor element is removed and replaced with a new semiconductor element. At this time, the semiconductor element can be easily removed by adjusting the adhesive strength of the conductive adhesive to a necessary minimum. The adhesive strength is preferably about 3 × 10 ⁶ to 30 × 10 ⁶ N / m ² per bump.

As described above, in this reference example, in addition to the effect described in the above-mentioned reference example 1, the semiconductor element 201 having the area array electrode structure and the semiconductor element having the peripheral electrode structure which are flip-chip mounted on both surfaces are provided. Since electrical connection with 203 is made via the multilayer wiring board 105 having the inner via hole 109 formed therein, the wiring length can be shortened, and the semiconductor device can operate at high speed and have low power consumption. . In particular, in a semiconductor element having an area array-shaped electrode array, the wiring length of the electrode terminal located near the central portion of the semiconductor element can be significantly shortened as compared with a semiconductor device using a conventional wiring board. Becomes Note that general mounting techniques other than the flip-chip mounting technique shown in Reference Example 1 and the like can be applied to this reference example. It is also possible to mount semiconductor elements having an electrode array in the form of area array on both surfaces of the multilayer wiring board 107.

Reference Example 8 FIG. 16 is a cross section of a semiconductor device package according to an eighth reference example of the present invention. In the figure,
The same reference numerals as those in FIG.
Is a bypass capacitor, 131 is a bypass capacitor 1
30 electrode terminals. As described above, in this reference example, the semiconductor element 201 having the electrode array in the area array is mounted on the upper surface of the multilayer wiring board 107, while the multilayer wiring board 10 is mounted.
On the back side of 7, one or more bypass capacitors 1
31 is mounted.

FIG. 17A shows an electrode structure of a semiconductor element 201 having an area array electrode structure.
The circuit pattern on the multilayer wiring board 107 in which the semiconductor element 201 concerning (b) is mounted is shown. Also, 205 is Au
Shows the ball bump of. In addition, in FIG. 18A, the multilayer wiring board 1 on which the six bypass capacitors 131 are mounted is shown.
The circuit pattern 108 on the back side of 07 is shown in FIG.
The electrode structure of six bypass capacitors is shown. Although the number of the bypass capacitors 131 is six in this reference example, it may be any number as required.

As described above, in the semiconductor device according to the present reference example, as in the case of the reference example 7, the inner via hole 1 is formed.
By using the multilayer wiring board 107 provided with 09, the inner via hole 109 is provided immediately below or in the vicinity of the circuit pattern of the central portion of the area array circuit pattern to perform three-dimensional wiring. The wiring length can be shortened, and the semiconductor device can operate at high speed and consume low power.

In particular, since the bypass capacitor 131 is provided to reduce the noise of the semiconductor device, if the wiring between the bypass capacitor 131 and the semiconductor element 201 becomes long, noise generated by such wiring will be generated. Therefore, the effect of providing the bypass capacitor 131 is canceled out. Therefore, by connecting the bypass capacitor 131 and the semiconductor element 131 with the three-dimensional wiring including the inner via hole 109, the wiring length can be shortened and the noise of the semiconductor device can be reduced.

[0035]

As is apparent from the above description, in the semiconductor device mounting body according to the present invention, the elements can be connected to each other regardless of the arrangement of the electrode terminals of the semiconductor element. It is possible to provide a miniaturized and speeded up semiconductor device by making a connection similar to the chip-on-chip system by using it as it is.

Further, since the semiconductor elements are not directly connected to each other, it is possible to prevent damage to other semiconductor elements when the one semiconductor element is attached or detached.

By mounting the semiconductor device on a mother multilayer wiring board, a high-density mounting body can be formed, which can contribute to downsizing of electronic equipment.

Further, even when the semiconductor element having the area array electrode terminals is flip-chip mounted by the face-down method, the wiring is performed through the multilayer wiring board 105 in which the inner via holes 109 are formed. The semiconductor device can be shortened, and the semiconductor device can have higher speed and lower power consumption.

In particular, in a semiconductor element having an area array-shaped electrode terminal array, the wiring length of the electrode terminals located near the central portion of the semiconductor element is significantly shortened as compared with a semiconductor device using a conventional wiring board. It becomes possible to do.

Further, by connecting the bypass capacitor and the semiconductor element with a three-dimensional wiring composed of inner via holes, the wiring length can be shortened and the noise of the semiconductor device can be reduced.

[Brief description of drawings]

FIG. 1A is a perspective view of a semiconductor device according to a reference example of the present invention. (B) It is sectional drawing in II 'of FIG.1 (a).

2A, 2B, and 2E are arrangements of bumps formed on a semiconductor element according to a first reference example of the present invention. (C) (d) is a circuit pattern of the multilayer wiring board according to the first reference example of the present invention.

FIG. 3 is a top view of a semiconductor device according to a first reference example of the present invention.

FIG. 4 is a sectional view of a semiconductor device package according to a second reference example of the present invention.

FIG. 5 is a cross-sectional view of a semiconductor device mounting body according to the first embodiment of the present invention.

FIG. 6 is a cross-sectional view of a mounted body of a semiconductor device according to a second embodiment of the present invention.

FIG. 7 is a cross-sectional view of a semiconductor device package according to a third reference example of the present invention.

FIG. 8 is a cross-sectional view of a package of a semiconductor device according to a fourth reference example of the present invention.

FIG. 9 is a sectional view of a semiconductor device according to a fifth reference example of the present invention.

FIG. 10 is a sectional view of a semiconductor device package according to a sixth reference example of the present invention.

FIG. 11 is a perspective view of a semiconductor device according to a seventh reference example of the present invention.

12 is a cross-sectional view taken along the line II-II ′ of FIG.

FIG. 13 is an electrode array of a semiconductor element.

FIG. 14A is an electrode array of a semiconductor element having an electrode array in the form of an area array. (B) A circuit pattern of a multilayer wiring board on which a semiconductor element having an area array electrode array is mounted.

FIG. 15A is a circuit pattern of a multilayer wiring board on which a semiconductor element having a peripheral electrode array is mounted. (B) An electrode array of a semiconductor device having a peripheral electrode array.

FIG. 16 is a sectional view of a semiconductor device according to an eighth reference example of the present invention.

FIG. 17 (a) is an electrode array of a semiconductor element having an electrode array in the form of an area array. (B) A circuit pattern of a multilayer wiring board on which a semiconductor element having an area array electrode array is mounted.

FIG. 18 (a) is a circuit pattern of a multilayer wiring board on which a bypass capacitor is mounted. (B) The electrode arrangement of the bypass capacitor.

FIG. 19 is a cross-sectional view of a conventional chip-on-chip semiconductor device.

[Description of Reference Signs] 1, 101 First semiconductor element, 2, 102 Electrode terminals formed on the first semiconductor element, 3, 103 Second semiconductor element, 4, 104 Formed on second semiconductor element Electrode terminal, 5, 105 Third semiconductor element, 6, 106
Electrode terminals formed on the third semiconductor element, 7, 107
Multilayer wiring board, 8,108 Circuit pattern on multilayer wiring board, 9,109 Inner via holes, 10,110,1
15 electrical junction, 11, 111 insulating substrate, 12,
112 mother multilayer wiring board, 13, 113 circuit pattern on mother multilayer wiring board, 114 Au wire, 11
6 conductive support, 130 bypass capacitor, 130
By-pass capacitor electrode, 201 first semiconductor element, 202 first semiconductor element area array electrode terminal, 203 second semiconductor element, 204 second semiconductor element peripheral electrode terminal, 205 ball bump.

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Kazuyoshi Amami             1006 Kadoma, Kadoma-shi, Osaka Matsushita Electric             Sangyo Co., Ltd. (72) Inventor Yoshihiro Bessho             1006 Kadoma, Kadoma-shi, Osaka Matsushita Electric             Sangyo Co., Ltd.

Claims (9)

[Claims] 1. An insulating layer and a circuit pattern layer are laminated,
A multilayer wiring board having a three-dimensional wiring in which the circuit pattern layers provided on both surfaces of the insulating layer are electrically connected through a plurality of inner via holes provided through the insulating layer,
A first semiconductor element and a second semiconductor element; and a mother multilayer wiring board having a circuit pattern on a surface thereof, wherein the first semiconductor element is mounted on an upper surface of the multilayer wiring board, and the second semiconductor element is provided. The element is disposed between the lower surface of the multilayer wiring board and the surface of the mother multilayer wiring board, the first semiconductor element and the second semiconductor element are electrically connected, and the end portion of the multilayer wiring board is provided. A package of a semiconductor device, in which the circuit pattern on the multilayer wiring board and the circuit pattern on the mother multilayer wiring board are electrically connected by curving the board toward the mother multilayer wiring board. 2. An insulating layer and a circuit pattern layer are laminated,
A multilayer wiring board having a three-dimensional wiring in which the circuit pattern layers provided on both surfaces of the insulating layer are electrically connected through a plurality of inner via holes provided through the insulating layer,
A first semiconductor element and a second semiconductor element, a mother multilayer wiring board having a circuit pattern on the surface, and a protruding electrode for electrically connecting the multilayer wiring board and the mother multilayer wiring board The first semiconductor element is mounted on the upper surface of the multilayer wiring board, the second semiconductor element is disposed between the lower surface of the multilayer wiring board and the surface of the mother multilayer wiring board, and the first semiconductor element is mounted on the upper surface of the multilayer wiring board. A semiconductor device in which a semiconductor element and the second semiconductor element are electrically connected, and the circuit pattern on the multilayer wiring board and the circuit pattern on the mother multilayer wiring board are electrically connected by the protruding electrode. Implementation body. 3. The package of the semiconductor device according to claim 1, wherein the insulating layer is made of a resin-impregnated fiber sheet. 4. The semiconductor device package according to claim 1, wherein at least the first and second semiconductor elements are face-down flip-chip mounted. 5. The electrode terminal of at least one semiconductor element of the first and second semiconductor elements is formed so as to be arranged in an area array form. A packaged semiconductor device as described above. 6. A first semiconductor element and a second semiconductor element are flip-chip mounted face down on the multilayer wiring board, and the electrode terminals of the semiconductor element are connected by the three-dimensional wiring. Claim 1 or 2 characterized by the above.
A semiconductor device package according to item 1. 7. A semiconductor element having the electrode terminals formed in an area array is flip-chip mounted face down on one surface of the multilayer wiring board, and an electronic component is mounted on the other surface of the multilayer wiring board. 3. The packaged semiconductor device according to claim 1, wherein the electrode terminal of the semiconductor element and the electrode terminal of the electronic component are connected by the three-dimensional wiring. 8. The semiconductor device according to claim 7, wherein the electronic component is a bypass capacitor. 9. The projection plane in a direction perpendicular to the multilayer wiring board of one or more semiconductor elements mounted on both surfaces of the multilayer wiring board, respectively, is overlapped with each other.
A semiconductor device package according to item 1.