JP2003316663A - Method, system and program for data processing and for error detection and correction - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce a device scale and a processing scale, to improve reliability without causing overquality, to improve the degree of freedom of a configuration and processing, and to reduce the cost of an internal configuration by simplifying the internal configuration in a data processing error detection and correction system. <P>SOLUTION: A W/R and ECC (error correcting code) controller 20 selectively designates a storage region for detecting and correcting errors of a plurality of optional data amounts and a storage region not for detecting and correcting the errors in a memory device 50 on the basis of an instruction of a central control unit 10 and writes input data (write data). The written data are read, data for error detection and correction generated from the read data and the input data are associated with the written data, and designation for securing the storage region for detecting and correcting errors is performed to store the associated data. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for detecting and correcting an error occurring in a data reading / writing process on an information storage medium (which will be appropriately referred to as a memory device or simply a memory), a system thereof, and a program. .

[0002]

2. Description of the Related Art Conventionally, when the contents of a memory of this type are rewritten, the bit error is detected and the bit error is corrected to a correct value (abbreviated as bit error detection / correction process). ) Is an ECC method (Error Check and
Correct / ECC memory and memory support memory controller) are known.

In this system for performing data processing by the ECC method and bit error detection and correction (hereinafter referred to as "data processing error detection and correction system"), processing data and program code data (appropriately, these two data Is described as "normal data") and bit error detection / correction data are stored separately in separate memories.
Then, together with the processed data and the program code data, the bit error detection / correction data is read at the same time,
Bit error detection and correction processing are performed.

In this bit error detection and its correction processing,
If there is no bit error or the predetermined bit error rate is small, the correction is not performed.

In the description of this specification, the expression "bit error detection / correction processing" includes "when no correction is performed". However, in order to avoid complication of the description, except where necessary. , The notation is omitted.

[0006]

In such a conventional data processing error detection and correction system as described above, the following (1) and (2)
There was the inconvenience of (3). (1) Even for processed data in which bit errors are tolerated, or data and program code data with low importance on bit error content, bit errors equivalent to those of processed data and program code data with high importance on bit error content Equipped with a function capable of detection and correction. In other words, the conventional data processing error detection / correction system provides unnecessarily high reliability, which causes a cost increase. That is, the quality was excessive. (2) Storage of processing data and program code data,
The bit error detection / correction data is stored in separate memories, so that the two memories are mounted on a printed circuit board or the like. In other words, the reliability of the product is impaired due to the occurrence of a failure due to the mounting of the two memories in which the wiring is complicated. (3) Since the two memories are mounted on the printed circuit board or the like, the manufacturing cost is increased, and it is difficult to adopt the low cost product.

In order to solve the above problems, the present invention reduces the device scale and processing scale, does not cause excessive quality, improves reliability, and improves the degree of freedom in configuration and processing. However, it is an object of the present invention to provide a data processing and error detection / correction method, a system thereof, and a program that can reduce the cost.

Still another object of the present invention is to provide a data processing and error detection / correction method, a system thereof, and a program, the internal structure of which is further simplified and the cost can be further reduced.

[0009]

A first data processing and error detection / correction method of the present invention that achieves the above object is to write only input data and generate error detection / correction data for the written data. In a method of an apparatus for selectively performing and, in a substantially single storage means, a storage area that performs error detection and correction of a plurality of arbitrary data amounts and a storage area that does not perform error detection and correction are selected selectively. The method includes the step of writing input data by designation and the step of reading the written data by designating a storage area. When this reading is data from a storage area for error detection and correction, this data and the input data are read. And the step of generating the error detection and correction data from the above, and the generated error detection and correction data is associated with the data read from the storage area for performing the error detection and correction. And, and a step of storing performing designated to secure a storage area for error detection and correction of any amount of data.

Further, in a method in an apparatus for selectively performing error detection correction or non-error detection correction on read data, error detection and correction of a plurality of arbitrary data amounts in substantially one storage means. Read out the data by selectively specifying the storage area that performs the error detection and the storage area that does not perform the error detection and correction, and the step of reading the error detection and correction data stored in association with the read data. And correcting the data based on the read error detection and correction data.

In the above invention, normal data (process data, program code data), bit error detection and correction, or non-bit error detection and correction data storage is performed for a storage area having an arbitrary data amount in one storage device. Areas can be allocated.

As a result, (1) there is no need to provide separate storage devices for normal data and for bit error detection and correction data as in the conventional example, the configuration is simplified, and the device scale and processing scale are increased. It is reduced. (2) Bit error detection and correction can be performed only on process data and program code data that have a high degree of importance (reliability requirement) on the content of bit errors. In other words, since the bit error detection / correction process is not performed on the process data or the program code data having a low degree of importance on the bit error content, excessive quality can be avoided. That is, a data storage area for non-bit error detection and correction is provided. (3) By providing one storage device and simplifying the implementation, the influence from hardware (implementation configuration) failure is reduced as compared with the case where different storage devices are implemented as in the conventional example. , Its reliability is improved. (4) Since a storage area for bit error detection and correction and a storage area for non-bit error detection and correction can be assigned to the storage device, the degree of freedom in configuration and processing (in other words, design) is improved.

A second data processing and error detection / correction method of the present invention that achieves the above object is an apparatus for selectively writing input data and selectively generating error detection / correction data for the written data. In the method of (1), the input data is selected by substantially designating a storage area in which a plurality of preset fixed data amounts are subjected to error detection / correction and a storage area not subjected to error detection / correction in substantially one storage means. A step of writing, a step of reading the written data by designating a storage area, a step of generating error detection and correction data from the input data and the data from the storage area in which error detection and correction are performed, and this generation The error detection / correction data thus obtained is associated with the data read from the storage area for error detection / correction,
And a step of storing in a fixed data amount storage area for error detection and correction.

Furthermore, in a method in a device for selectively performing error detection correction or non-error detection correction on read data, a plurality of preset fixed data amounts in substantially one storage means are provided. And a step of reading data by selectively designating a storage area in which error detection and correction are performed and a storage area in which error detection and correction are not performed, and a step of reading out error detection and correction data stored in association with the stored data. Error correction is performed on the read data based on the read error detection and correction data.

In the above-described invention, normal data (processing data, program code data), bit error detection and correction, or non-bit error detection and correction are applied to a storage area having a fixed data amount of n in one storage device. Storage area can be allocated. Therefore, the internal structure is further simplified and the cost can be reduced.

This detail simplifies the writing and reading processes for the n fixed data amount storage areas. For example, unlike the case of specifying information (for example, an address number) including numerical values at the beginning and end of a storage area that changes for each arbitrary storage area, the configuration and processing do not become complicated. In other words, one piece of information (for example, a flag number) given in advance for each of n fixed data amount storage areas.
It only needs to be specified. Therefore, the configuration for specifying the storage area and the signal processing are simplified. That is, the internal structure is further simplified, the cost can be reduced, and it is easy to adopt it in a low-priced product.

The third data processing error detection / correction system of the present invention which achieves the above object selectively writes only input data and selectively generates error detection / correction data for the written data. A control device that outputs data for writing, receives read data, and instructs writing or reading,
Substantially one, a storage device having a storage area that performs error detection and correction of a plurality of arbitrary data amounts and a storage area that does not perform error detection and correction, and to the storage device based on an instruction from the control device, A write or read (W / R) error detection / correction device that performs one or both of the following (a) and (b) is provided. (A) Input data, which is data for writing from the control device, is selectively designated and written into a storage area that performs error detection and correction of a plurality of arbitrary data amounts and a storage area that does not perform error detection and correction, In addition, the error detection / correction data generated from the read data and the input data is stored in association with the written data by designating a storage area for error detection / correction.
(B) A plurality of arbitrary fixed data amounts are selectively designated for a storage area in which error detection and correction are performed and a storage area in which error detection and correction is not performed, and stored data and stored in association with this data The error detection / correction data that has been read is read out and the error is corrected.

Further, in a data processing error detection and correction system which selectively writes input data and selectively generates error detection and correction data for the written data, the data for writing is output, and , A storage device having a control device for receiving read data and instructing this writing or reading, a storage region for performing error detection and correction of a plurality of fixed data amounts, and a storage region for not performing error detection and correction And a writing or reading (W / R) error detection / correction device for performing one or both of the following (a) and (b) in the storage device based on an instruction from the control device. (A) In the storage device,
Input data, which is data for writing from the control device, is written by selectively designating a storage area for error detection and correction of a plurality of preset fixed data amounts and a storage area for which error detection and correction is not performed, and this writing is performed. The specified storage area is read and the read data is read, and the error detection and correction data is generated from the input data and the data from the storage area where the error detection and correction are performed. It is associated with the data read from and is stored in the storage area for error detection and correction.
(B) In the storage device, the data and the data are stored in association with the data by selectively designating a storage area in which a plurality of preset fixed data amounts are subjected to error detection and correction and a storage area in which the error detection and correction are not performed. The error detection and correction data that has been read is read, and the read data is corrected for errors based on the read error detection and correction data.

In the system of the above-mentioned invention, as in the method of the above-mentioned invention, the apparatus scale and the processing scale are reduced, the quality is not excessive, the reliability is improved, and the configuration and the processing are free. And the cost can be reduced. In addition, the internal structure is more simplified,
Cost reduction is possible.

A program of the present invention for achieving the above object is for causing a computer to execute one or both of the following (a) and (b). (A) A procedure of selectively designating a storage area in which a plurality of arbitrary data amounts are subjected to error detection / correction and a storage area in which no error detection / correction is performed, a procedure of writing input data in the designated storage area, and a writing The procedure for reading the read data and the error detection and correction data generated from the read data and the input data are associated with the written data, and the storage area for error detection and correction is specified. Procedure to remember. (B) A procedure for selectively designating a storage area in which a plurality of arbitrary fixed data amounts are subjected to error detection / correction and a storage area not subjected to error detection / correction, and the data stored by this designation and the data A procedure for reading the error detection and correction data stored in association with each other, and a procedure for performing error correction on the read data based on the error detection and correction data.

Further, the program of the present invention causes a computer to execute one or both of the following (a) and (b). (A) A procedure of selectively designating a storage area in which error detection and correction of a plurality of preset fixed data amounts are performed and a storage area in which error detection and correction is not performed, and a procedure of writing input data to the storage area according to this designation And a procedure for reading the written data by designating a storage area, and a procedure for generating error detection and correction data from the input data and the data in the case where the reading is from the storage area where error detection and correction are performed, The generated error detection / correction data is associated with the data read from the storage area for error detection / correction,
And the procedure of storing in the storage area for error detection and correction. (B) A procedure for selectively designating a storage area in which a plurality of preset fixed data amounts are subjected to error detection / correction and a storage area not subjected to error detection / correction, and data by this designation,
And a procedure for reading the error detection and correction data stored in association with this data, and a procedure for performing error correction on the read data based on the read error detection and correction data.

The program of the present invention can be provided by market distribution through downloading and installation from an information recording medium (package software or the like) or a communication network. Therefore, the present invention can be easily implemented by a microcomputer installed in various devices, and the versatility thereof is improved.

[0023]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the data processing and error detection / correction method, its system and program of the present invention will be described below with reference to the drawings.

It should be noted that the following configurations and arrangements are merely schematic ones so that the present invention can be understood. In addition, although preferred constitutional examples of the present invention will be described below, the composition of each constitution is merely a preferable example. Therefore, the present invention is not limited to the following embodiments and can be applied to various forms based on the present invention (in particular, the description of the claims).

(Structure of First Embodiment and Operation of Each Part) FIG. 1 is a block diagram showing the structure of the first embodiment of the present invention.

Referring to FIG. 1, this first embodiment
A central controller (corresponding to the controller of the invention) 10;
Writing / reading, error detection and correction (hereinafter W / R / E
Abbreviated as CC. It has a control device 20 (corresponding to the W / R error detection and correction device of the present invention) and a memory device (corresponding to the storage device of the present invention) 50 using a solid-state storage device.

Central controller 10 (CPU) and W / R · E
The CC control device 20 and the W / R / ECC control device 20 and the memory device 50 are connected by a bus line BUS1 and a bus line BUS2.

The central control unit 10 is, for example, for system control in a computer equipped with the central control unit 10, and writes data in the memory unit 50 and writes data in the memory unit 50 through the W / R / ECC control unit 20. The control to read the data is being executed.

The W / R / ECC controller 20 controls the central controller 10 to control the first embodiment (schematic operations (A) (B) (C) and (D) shown in FIG. 3).
To execute.

This central control unit 10 and W / R / ECC
The data from the central control unit 10 is written in the memory unit 50 under the control of the control unit 20, and the data written in the memory unit 50 under the control of the central control unit 10 and the W / R / ECC control unit 20. Is read.

The W / R / ECC control device 20 includes a register (1 ... n) (corresponding to a plurality of storage means of the present invention) 21.
A comparator (1 ... n) (corresponding to a plurality of comparison means of the present invention) 22, a control unit 23 using an MPU (Microprocessing Unit), an address generation unit 24, and a selector (1) 25. , A register D-R26, a bit error detection / correction data generation unit 27, a selector (2) 28, a register D-W29, a bit error detection / correction unit 30, and a selector (3) 40. .

The registers (1 ... n) 21 are used for the memory device 5.
Data processing (writing, reading) to 0 and information on the bit error detection and correction target storage area ((A) in FIG. 3)
(B) (C) and (D)) are preset.

The comparators (1 ... n) 22 are connected to the central controller 1
It outputs a comparison result signal obtained by comparing the address data from 0 and the data from each of the registers (1 ... N) 21 (this comparison will be described in detail later).

The control section 23 controls each section of the W / R / ECC control device 20 to correspond to the operation of the first embodiment (corresponding to (A) (B) (C) and (D) in FIG. Control information (corresponding to the program of the present invention) for this purpose is stored in advance.

The address generator 24 generates and outputs adjacent address data of the address data written in the memory device 50. The adjacent address data will be described later.

The selector (1) 25 is the central control unit 10.
Address data from or from adjacent address data from the address generator 24 is selected and output.

The register D-R26 is the central control unit 10.
Input data from is temporarily stored and output.

Bit error detection / correction data generator 27
Is data from the register D-R26 (central controller 1
(Input data from 0) and read data from the memory device 50 output from the register D-W29, bit error detection / correction data is generated and output.

The selector (2) 28 is the central controller 10
Or the bit error detection / correction data from the bit error detection / correction data generator 27 is selectively output.

The register D-W29 temporarily holds the data read from the memory device 50.

The bit error detection / correction unit 30 performs a bit error detection / correction process and outputs the data.

The selector (3) 40 outputs the read data from the memory device 50 or the bit error detection / correction processing data from the bit error detection / correction unit 30.

FIG. 2 is a diagram for explaining the storage area of the memory device 50 in the first embodiment.

Referring to FIG. 2, this memory device 50
Is a "bit error detection / correction target storage area" M1, ..., Which has a different arbitrary data amount as shown in (a).
Mn and "a storage area targeted for data not subjected to bit error detection and correction (hereinafter referred to as a non-bit error detection and correction target storage area)" m1, m2 ... mn.

Bit error detection / correction target storage area M1 ... M
For example, n is a storage area for processing data or program code data having a high degree of importance (reliability requirement) on the content of bit errors, and a non-bit error detection and correction target storage area m.
1, m2 ... mn are storage areas for processing data and program code data with a low degree of importance on bit error content. That is, it stores data that is not subjected to bit error detection and correction processing, and by providing and selecting these two types of storage areas, excessive quality can be avoided.

This bit error detection / correction target storage area M1
The following data (1), (2) and (3) of each Mn are preset in the registers (1 ... n) 21. (1) The start address data (address number) of the storage area to be written or read, and the end address are
It is not set here because it is determined by the address data in order to secure the data amount of the write target storage area described below. (2) In particular, address data (address value) for securing the data amount of the write target storage area (3) Data processing If only error detection or correction processing is performed, information that sets the level of correction processing This correction processing The level is a level of the correction process, for example, up to how many error bits are to be corrected. It should be noted that this correction level will be described in detail in the following description of the “error correction code”.

Based on the data of (1), (2) and (3), the central control unit 10 controls the W / R / ECC control unit 20.
Through this, it becomes possible to individually set writing and reading in the bit error detection and correction target storage areas M1 ... Mn, which are different data amounts in the memory device 50.

The storage areas of the memory device 50 not set in the registers (1 ... n) 21 are non-bit error detection / correction target storage areas m1, m2 ... mn.

Bit error detection / correction target storage area M1 ... M
As shown in FIG. 2B, n is a normal data area Da in which normal data (input data S15a in FIG. 1) is stored and a bit error detection / correction data area Db in which bit error detection / correction data is stored. It is divided into two storage areas.

The normal data here is, for example,
It is processing data or program code data in word processing and is distinguished from bit error detection / correction data.

In this data processing error detection and correction system, the normal data area Da is the direct data (only through control of the W / R / ECC controller 20) by the central controller 10 (for example, the input data 15a, the output). The data 16a) can be read and written. Also,
The central controller 10 cannot directly write (access) data to the bit error detection / correction data area Db, but can write data by access through the control of the W / R / ECC controller 20. There is.

(Overall Operation of First Embodiment) FIG. 3 is a block diagram showing a schematic operation of the first embodiment.

Referring to FIG. 3, in the first embodiment, the following general operation is performed. (A) Ordinary data area Da of bit error detection / correction target storage areas M1 ... Mn of arbitrary data amount in the memory device 50
One or both of (a) and (b), and (c) in the bit error detection and correction processing for (a) normal data writing processing to (a) normal data writing to (b) normal data area Da. One or both of the bit error detection and correction processing (B) (a) normal data read processing from the normal data area Da of an arbitrary data amount in the memory device 50,
(B) In the bit error detection / correction process for reading the normal data from the normal data area Da,
(B) One or both, further (c) One or both in bit error detection and correction processing (C) Non-bit error detection and correction target storage areas m1, m2 ...
Data writing process to mn (D) Non-bit error detection and correction target storage areas m1, m2 ...
Data reading process from mn Hereinafter, a detailed process centering on the control of the control unit 23 corresponding to the general operation will be described.

First, a processing procedure corresponding to the general operation (A) shown in FIG. 3 will be described.

FIG. 4 is a flow chart showing a procedure for writing normal data to the memory device 50 of the first embodiment (corresponding to the general operation of FIG. 3A).

Referring to FIGS. 1, 2 and 4, first,
The W / R / ECC control device 20 sends the central control device to the normal data area Da in any one of the bit error detection / correction target storage areas M1 ... Mn of the memory device 50 (the notation of "any" is omitted below). In the process of writing the input data (normal data) S15a from the central controller 10,
The control data S17a from step S1 is fetched and set (steps S1 and S2 in FIG. 4, hereafter, the notation of “FIG. 4” is omitted).

Next, the bit error detection and correction target storage from the address data S14a output from the central controller 10 and the register (any one of 1 ... n (the notation of "any one" is omitted below)) 21 Regions M1 ... Mn and
Setting information related to the normal data area Da ((A) in FIG. 3)
Information corresponding to the rough operation) is compared by a comparator (any one of 1 ... n (the notation of “any” is omitted below)) 22.

In this comparison, the address data S14a from the central control unit 10 is stored in the memory device 50 shown in FIG.
In the case where the address data (address value) of the normal data area Da shown in is shown, the comparison result signal is output from the comparator (1 ... N) 22, and the comparison result signal is fetched by the control unit 23 (step S3). , S4: YeS).

In step S4, the address data S1
When 4a is not the address data (address value) corresponding to the normal data area Da of the bit error detection / correction target storage areas M1 ... Mn (No), the processing ends.

Based on the determination in step S4 and the control data S17a from the central control unit 10, the control unit 23 recognizes that it is the data writing process to the normal data area Da of the memory device 50 and executes the subsequent control. (Step S5).

Next, the output data from the central control unit 10 is input through the bus line BUS1 as the input data S15a in the W / R / ECC control unit 20 to the control unit 23 which takes in the control data S17b from the central control unit 10. It is held in the register D-R26 by the control signal from (step S6).

In the following, "Bus line BUS
The description of "1" and its operation description are omitted. Similarly, in the following description, the "bus line BUS2" will not be described and its operation will be omitted.

After the processing of step S6, the selector (1) 25 receives the address data S14a from the central control unit 10 in response to the control signal from the control unit 23 and stores it in the memory unit 5.
It is output to 0 as address data S18a (step S7).

Further, output data from the central control unit 10 (input data S in the W / R / ECC control unit 20)
15a) is input to the selector (2) 28. The selector (2) 28 outputs the input data S15a to the memory device 50 as the write data S19a according to the control signal from the control unit 23 (step S8).

Next, the control section 23 outputs the control data S21a to the memory device 50. This control data S21a
In the memory device 50, the write data S19a
(The same as the input data S15a) is written as normal data in the normal data area Da in the bit error detection / correction target storage areas M1 ... Mn shown in FIG. 2 (step S
9).

Thereafter, in response to a control signal from the control unit 23, the address generation unit 24 generates adjacent address data of the address data S18a (S14a) written in the memory device 50 and outputs it to the selector (1) 25. The adjacent address data S18b is output and the selector (1) 25 outputs the adjacent address data S18b to the memory device 50 in response to a control signal from the controller 23 (step S10).

The adjacent address data S18b
Is specified to continuously perform the processing of the bit error detection / correction data area Db after the storage processing in the normal data area Da (write the bit error detection / correction data described below). To do. The adjacent address data S18b may be output from the central controller 10 to the memory device 50 through the selector (1) 25.

Next, the bit error detection / correction processing in the W / R / ECC control device 20 is performed (step S11: Yes).
S). In this process, first, the control data S21b from the control unit 23 reads the normal data from the normal data area Da in the bit error detection and correction target storage areas M1 ... Mn shown in FIG. 2 from the memory device 50.
(Step S12).

The normal data read from the memory device 50 is output to the W / R / ECC control device 20 as read data S20a, and the read data S20a is controlled by the register D-W29 from the control unit 23. The signal is held (step S13).

Then, the bit error detection / correction data generation section 27 is responsive to a control signal from the control section 23 to input data S15a from the central control unit 10 output from the register D-R26 and a memory output from the register D-W29. Based on the read data S20a from the device 50, a bit error with respect to the write data S19a (normal data) written this time in the memory device 50 is detected, and bit error detection / correction data for that correction is generated. (Step S14).

Generation of this bit error detection / correction data is performed by a known error correction code. For example,
In writing the input data S15a (write data S19a, normal data), a method of adding a redundant code for automatically correcting the bit error to the input data S15a is generally used. As the error correction code, the original input data S15a is divided into blocks having a constant data amount to perform error correction, or the original input data S15a.
A convolutional code for continuously performing error correction is known,
Since the number of correctable error bits is different, it is selectively adopted depending on the design conditions.

The number of error bits that can be corrected is described in "(3) Information for setting the level of correction processing when only bit error detection or correction processing is performed" described above. Stage, for example, the level of up to how many error bits are to be corrected ".

On the other hand, the address generator 24 is controlled by the controller 23.
Address signal 28c for storing the bit error detection and correction data corresponding to the writing to the memory device 50 is generated by the control signal from the memory device 50, and is output to the selector (1) 25. The address data 28c is output to the memory device 50 in response to the control signal from (step S15).

Then, the bit error detection / correction data generator 27 outputs the bit error detection / correction data generated by the control signal from the controller 23 to the selector (2) 28 as the write data S19b, and this selector (2)
28 is a control signal from the control unit 23, which is output to the memory device 50 and written in the bit error detection / correction data area Db (step S16).

After the writing is completed, the control section 23 sends a writing completion notification from the memory device 50 to the control data S21c.
(Step S17), the central controller 10
Then, the completion of writing the bit error detection and correction data in the memory device 50 is notified by the control data S17c (step S18).

Next, a processing procedure corresponding to the schematic operation (B) shown in FIG. 3 will be described.

FIG. 5 is a flowchart showing a processing procedure (corresponding to (B) of FIG. 3) of reading normal data from the memory device 50 of the first embodiment.

Referring to FIGS. 1, 2 and 5, first,
The W / R / ECC control device 20 fetches the control data S17d from the central control device 10 in the process of reading normal data from the normal data area Da of the bit error detection / correction target storage areas M1 ... Mn of the memory device 50. It is set (steps S21 and S22 in FIG. 5, hereafter, the notation of “FIG. 5” is omitted).

Next, the address data S14b from the central control unit 10 and the information on the normal data area Da in the bit error detection / correction target storage areas M1 ... Mn stored in the registers (1 ... N) 21 ((in FIG. 3). B) information corresponding to the general operation) is compared by the comparator (1 ... n) 22,
The control unit 23 takes in this comparison result signal (step S
23).

In this case, if the address value indicates the normal data area Da in the comparison (step S24: Ye
S), the comparison result signal of the corresponding type is sent to the comparator (1 ... n).
22 outputs to the control unit 23. Based on the comparison result signal and the control data S17e from the central controller 10, the control unit 23 recognizes that the data is read from the normal data area Da and executes the subsequent control processing (step S25).

The control unit 23 causes the selector (1) 25 to output the address data 14b from the central control unit 10 to the memory unit 50 as the address data S18d by the control signal, and then the control data S2 from the control unit 23.
1d allows the normal data area D of the bit error detection / correction target storage areas M1 ... Mn shown in FIG.
The normal data stored in a is read (steps S26 and S27).

Normal data read from the memory device 50 is sent to the W / R / ECC control device 20 as read data S20b, and the read data S20b is sent to the control signal from the control unit 23 by the register D-W29. It holds by (step S28).

Further, the address generation unit 24 has the control unit 2
Address data S18e of the bit error detection / correction data area Db, which is stored in association with the normal data read from the memory device 50 by the control signal from 3, is generated and output to the selector (1) 25. Selector (1)
25 is a memory device 5 according to a control signal from the control unit 23.
It is output to 0 (step S29).

In response to a control signal from the control unit 23, the memory device 50 reads out the bit error detection / correction data in the bit error detection / correction data area Db and outputs it to the register D-W29 as the read data S20c. It is held by the control signal from the controller 23 (steps S30 and S31).

Thereafter, the bit error detection / correction unit 30 performs the bit error detection / correction process in accordance with the control signal from the control unit 23, outputs the bit error detection / correction process data to the selector (3) 40, and the selector (3) 3) 40 outputs to the central controller 10 as output data S16b in response to the control signal from the control unit 23 (step S3).
2).

Thereafter, the central control unit 10 is informed by the control unit 23 that the normal data has been read out from the control data S17f.
Is notified by (step S33).

Next, a processing procedure corresponding to the general operation (C) shown in FIG. 3 will be described.

FIG. 6 is a flow chart showing a data write processing procedure (corresponding to the general operation of FIG. 3C) in the non-bit error detection / correction target storage areas m1, m2 ... mn in the first embodiment.

Referring to FIGS. 1, 2 and 6, first,
The W / R / ECC control device 20 writes data to any of the non-bit error detection / correction target storage areas m1, m2 ... mn (hereinafter, the notation of “any” is omitted) ((of FIG. 3). C) Corresponding to the general operation), the central controller 1
It is set by taking in the control signal 17g from 0 (FIG. 6).
Steps S41 and S42 in the middle, and the description of "FIG. 6" will be omitted hereinafter).

In this writing process, first, the address data S14c and the register (1 ...
n) the information about the non-bit error detection / correction target storage areas m1, m2 ... mn stored in (n) 21 (information corresponding to the general operation of (C) of FIG. 3) is compared by the comparator (1 ... N) 22. (Step S43).

In this comparison, when the address data 14c does not indicate the bit error detection / correction target storage areas M1 ... Mn (step S44: No), in other words, the non-bit error detection / correction storage areas m1, m2 ... mn. , The comparator (1 ... N) 22 outputs the comparison result signal to the control unit 23. Based on this comparison result signal and the control data S17h from the central control unit 10, the control unit 23
Are non-bit error detection / correction target storage areas m1, m2 ...
Recognize that writing to n (step S4
5).

The control section 23 causes the selector (1) 25 to output the address data S14c as the address data 18f to the memory device 50 in response to the control signal (step S46).

Further, the input data 15b from the central controller 10 is input to the selector (2) 28, and the selector (2) 28 outputs it as the write data 19c to the memory device 50 according to the control signal from the controller 23. (Step S47). In the memory device 50, the write data 19c is written in the non-bit error detection / correction target storage areas m1, m2 ... mn by the control data S21e from the control unit 23 (step S48).

After this writing is completed, the control unit 23 notifies the central controller 10 of the writing of the input data 15b by the control data S17i (step S4).
9).

Next, a processing procedure corresponding to the general operation (D) shown in FIG. 3 will be described.

FIG. 7 is a flow chart showing a data read processing procedure (corresponding to the general operation of FIG. 3D) from the non-bit error detection / correction target storage areas m1, m2 ... mn in the first embodiment. .

Referring to FIGS. 1, 2 and 7, first,
The W / R / ECC controller 20 performs a data read process to the non-bit error detection / correction target storage areas m1, m2, ... mn (corresponding to the schematic operation of FIG.
The control data S17j from step S21 is fetched and set (steps S61 and S62 in FIG. 7, hereafter, the notation of “FIG. 7” is omitted).

In this reading process, the central controller 10
From the address data 14d and the register (1 ... n) 21
Non-bit error detection and correction target storage area m stored in
Information about 1, m2 ... mn (information corresponding to the general operation of (D) in FIG. 3) is compared by the comparator (1 ... N) 22 (step S63).

In this comparison, if the address data 14d does not indicate the bit error detection / correction target storage areas M1 ... Mn (step S64: No), in other words, the non-bit error detection / correction storage areas m1, m2 ... mn. , The comparator (1 ... N) 22 outputs the comparison result signal to the control unit 23. By the comparison result signal and the control data S17k from the central controller 10, the control unit 23
Are non-bit error detection / correction target storage areas m1, m2 ...
Recognizing that reading is being performed from n, the subsequent control is executed (step S65).

The control section 23 transfers the address data 14d from the selector (1) 25 to the memory device 50 according to the control signal.
To output as address data S18g (step 66).

Further, the input data S15d from the central control unit 10 is inputted to the selector (2) 28, and the selector (2) 28 stores this input data S15d as the write data S19d in response to the control signal from the control section 23. The data is output to the device 50 (step S67).

In the memory device 50, the control data S21f from the controller 23 reads the data from the non-bit error detection / correction target storage areas m1, m2 ... mn (step S68).

After the completion of the reading, the control unit 23 notifies the central controller 10 of the completion of reading the data from the memory device 50 through the control data S17l (step S69).

(Advantages of First Embodiment) According to the first embodiment, one memory device 50 has bit error detection / correction target storage areas M1 ... Mn of arbitrary data amount (see FIG. 2).
In contrast, normal data (process data, program code data) and a storage area for bit error detection / correction or non-bit error detection / correction can be divided and assigned. That is, the normal data area Da and the bit error detection / correction data area Db are provided.

Therefore, it is not necessary to provide separate memories (for example, two memory devices 50) for normal data and for bit error detection and correction as in the conventional example, and the configuration is simplified and the device scale and The processing scale is reduced. Further, it becomes possible to perform the bit error detection and correction process only on the process data or the program code data having a high degree of importance (reliability requirement) on the bit error content. In other words, since the bit error detection / correction process is not performed on the process data or the program code data having a low degree of importance on the bit error content, excessive quality can be avoided. That is, the non-bit error detection / correction target storage areas m1, m2 ... mn in FIG. 2 are provided.

Furthermore, the simplified implementation by one memory device 50 reduces the influence from hardware (implementation configuration) failures as compared with the case where different memories are implemented as in the conventional example, Its reliability is improved. In addition, since the storage areas for data processing, error detection and correction, and non-bit error detection and correction can be assigned to the memory device 50, the degree of freedom in configuration and processing (in other words, design) is improved.

(Structure of Second Embodiment and Operation of Each Part) Next, a second embodiment will be described. In the following description of the second embodiment, the same components as those of the first embodiment are designated by the same reference numerals, and similar components are designated by similar reference numerals.

FIG. 8 is a block diagram showing the configuration of the second embodiment of the present invention.

Referring to FIG. 8, this second embodiment is
Central controller 10 and W / R / ECC controller 20A
And a memory device 50A.

Between the central control unit 10 and the W / R / ECC control unit 20A, and between the W / R / ECC control unit 20A and the memory unit 50A, the bus line BUS1 and the bus line BUS1 are provided as in the first embodiment. It is connected by the line BUS2.

The central controller 10 controls the writing / reading of data as in the first embodiment.

The W / R / ECC control device 20A operates under the control of the central control device 10 according to the second embodiment (see FIG.
0 (see (1), (2), (3) and (4)).

The memory device 50A is divided into n fixed data amounts (for example, divided into equal data amounts) as described with reference to FIG. 9 below, and various data writing and reading processes are performed here. Is performed as in the first embodiment.

In the W / R / ECC control device 20A, a register 31 (corresponding to one storage means of the present invention) and a comparator 32 (one of the present invention) arranged corresponding to the second embodiment are provided. (Corresponding to comparison means) and a control unit 23A are provided. Furthermore, an address generation unit 24 that operates in the same manner as in the first embodiment, a selector (1) 25, a register D-R 26, and a bit error detection and correction data generation unit 27.
, A selector (2) 28, a register D-W 29, a bit error detection / correction unit 30, and a selector (3) 40.

The register 31 stores information on the bit error detection and correction target storage area and the non-bit error detection and correction target storage area divided into n fixed data amounts of the memory device 50A (from (1) in FIGS. 9 and 10). (Information of (4)) is set in advance.

The comparator 32 outputs a comparison result signal obtained by comparing the address data from the central controller 10 with the data from the register 31 respectively.

The control section 23A controls each section of the W / R / ECC control device 20A to perform the operation of the second embodiment (see the schematic operations (1), (2), (3) and (4) in FIG. 10). ) Is executed and a control program therefor (corresponding to the program of the present invention) is stored.

The other parts from the address generator 24 to the selector (3) 40 operate similarly to the first embodiment. The overlapping description will be omitted.

FIG. 9 shows a memory device 50A of the second embodiment.
FIG. 3 is a diagram for explaining an internal storage area.

Referring to FIG. 9A, the memory device 50
The inside of A is divided into a plurality of fixed data amount storage areas (in this example, divided into n uniform data amounts). As in the first embodiment, each of the storage areas having a plurality of fixed data amounts is divided into a “bit error detection and correction target storage area” or a “non-bit error detection and correction target storage area” from area 0 to area n. The designation for this region 0 to region n is
It is preferable to specify by simple information such as a flag number, which corresponds to “specified by one piece of information given in advance for each storage area” in the present invention.

Further, as shown in FIG. 9 (b), the bit error detection / correction target storage areas 1, 2, ... Are the normal data area D1 in which the processing data and program code data are stored, as shown in FIG. 9 (b). It is divided into two storage areas of a bit error detection / correction data area D2 in which the bit error detection / correction data is stored.

In the data processing error detection and correction system, the normal data area D1 can be directly read and written by the central controller 10 (only through control of the W / R / ECC controller 20A). is there. Further, the central controller 10 cannot directly write (access) data to the bit error detection / correction data area D2, and data can be written by access through the control of the W / R / ECC controller 20A. Has become.

(Overall Operation of Second Embodiment) FIG. 10 shows the second operation.
It is a block diagram shown for explaining a schematic operation of an embodiment.

Referring to FIG. 10, in the second embodiment, a plurality of fixed data amount storage areas 0 of the memory device 50A are used.
~ N (divided into n storage areas of equal data amount),
The following general operations (1), (2), (3) and (4) are performed. (1) (a) Normal data write processing to any of the non-bit error detection and correction target storage areas 0 to n having a plurality of fixed data amounts in the memory device 50A, and (b) Bit error detection and correction processing for writing normal data At
One or both of (a) and (b), and one or both of (c) bit error detection and correction processing (2) Non-bit error detection and correction target storage areas 0 of a plurality of fixed data amounts of the memory device 50A (a) from either n
In the normal data read processing and (b) bit error detection and correction processing for normal data read, one or both of (a) and (b), and (c) one or both of the bit error detection and correction processing. (3) Data write processing to any of the non-bit error detection / correction target storage areas 0 to n (4) Data read processing from any of the non-bit error detection and correction target storage areas 0 to n Detailed processing focusing on the control of the control unit 23A will be described.

In the second embodiment, the processing procedure corresponding to (1) to (4) in FIG. 10 will be described with reference to FIGS. 4, 5, 6, and 7 of the first embodiment. The description will be given with reference again.

Referring to FIGS. 8 and 9, in the second embodiment, first, as a general operation (1) of FIG. 10, the W / R / ECC from the central control unit 10 to the normal data area D1 in the memory device 50A. When writing the data (input data S25a) via the control device 20, the address data S24a from the central control device 10 (this may be the flag numbers corresponding to the respective areas 0 to n) and stored in the register 31. The comparator 32 compares the information (bit (1) schematic operation in FIG. 10) regarding the bit error detection and correction processing in any one of the areas 0 to n of the fixed data amount (hereinafter, the description of “any” is omitted). To be done.

If the address data S24a indicates the bit error detection / correction target storage areas 1, 2, ... In this comparison, the control unit 23 is informed by the comparison result signal from the comparator 32.
It is recognized that A is a writing process to the bit error detection / correction target storage areas 1, 2, ... (FIG. 4 of the first embodiment).
(See steps S1 to S5).

After that, the processing is basically the same as that of the first embodiment. That is, the input data S25a is held in the register D-R26, and further the address data S2 is stored.
8a and write data S29a are output to the memory device 50A. After this, the memory device 50A changes the control data S
31a allows the write data S29a (input data S2
5a) is written to the normal data area D1 and the adjacent address data S28b is written to the memory device 50A.
Is output to (in step S6 of FIG. 4 of the first embodiment).
See S10).

After that, the bit error detection and correction processing is performed in the W / R / ECC control device 20, the data is read from the memory device 50A as the control data S31b, and the read data is set as the read data S30a in the register D. −
It is held at W29. Then, bit error detection / correction data is generated based on the input data S25a and the read data S30a, and the address data 28c and the write data S29b for this storage are output to the memory device 50A to complete the writing. Notify the control data S31
c, control data S27a is notified (see steps S11 to 18 in FIG. 4 of the first embodiment).

Next, a processing procedure corresponding to the general operation (2) of FIG. 10 will be described.

Referring to FIG. 8 and FIG. 9, the central control unit 10 performs W / R · E as a general operation (2) of FIG.
When reading data (input data S25a) from the bit error detection / correction target storage areas 1, 2, ... Of the CC control device 20A, information on the bit error detection / correction target storage areas 1, 2 ... From the addressless data 24b and the register 31. The comparison result signal obtained by the comparison of ((2) schematic operation of FIG. 10) is output from the comparator 32. Based on the comparison result signal and the control data S27b, the control unit 23A recognizes that the bit error detection / correction target storage areas 1, 2, ... Are being read (step S in FIG. 5 of the first embodiment).
21-S25).

After that, the processing is basically the same as that of the first embodiment. That is, the address data 28d is output to the memory device 50A. Furthermore, the control data S31d
By this, normal data is read from the memory device 50A, and the read data S30b is held in the register D-W29. Address data 28e for storing bit error detection and correction data corresponding to normal data is output to the memory device 50A. In addition, the memory device 50A
Data for bit error detection and correction from the register D-W2
9 holds (step S26 in FIG. 5 of the first embodiment).
~ S31).

Thereafter, bit error detection and correction processing is performed, and the output data S26a is output to the central controller 10. After this, the completion of reading the normal data is notified to the central controller 10 as control data S31e and control data S27c (step S31 in FIG. 5 of the first embodiment).
And S32).

Further, a processing procedure corresponding to the general operation (3) of FIG. 10 will be described.

Referring to FIGS. 8 and 9, in this writing process, first, the address data 24c and the register 31 are written.
Bit error detection and correction target storage area 1 stored in
Information regarding 2 ... (Schematic operation of (3) in FIG. 10) is compared, and by this comparison result signal and control data S27d,
Write to any of the non-bit error detection / correction target storage areas 0, ... N which is not the information of the bit error detection / correction storage area 1, 2, ... (Hereinafter, this “any” is omitted) Recognize (steps S41 to S45 in FIG. 6 of the first embodiment).

After that, the processing is basically the same as that of the first embodiment. That is, the address data 28f and the input data 25b are output to the memory device 50A, and the input data 29c is written in the non-bit error detection and correction target storage areas 0, ... N by the control data S31f. After this writing is completed, the central controller 10 is notified of the completion of writing through the control data S27e (steps S46 to S49 in FIG. 6 of the first embodiment).

Next, a processing procedure corresponding to the general operation (4) of FIG. 10 will be described.

With reference to FIGS. 8 and 9, in this data read processing, first, information regarding the address data 24d and the bit error detection and correction target storage areas 1, 2, ... Of the register 31 ((4) schematic operation in FIG. 10). Are compared, and the comparison result signal and the control data S27f from the central control unit 10 when the bit error detection and correction target storage areas 1, 2, ...
Therefore, the control unit 23 recognizes that the reading is from the non-bit error detection and correction target storage areas 0, ... N (steps S61 to S65 in FIG. 7 of the first embodiment).

After that, the processing is basically the same as that of the first embodiment. That is, the address data 28g and
Data is read from the memory device 50A by the control data S31g. After this reading is completed, the control unit 23
From the control data S27g to notify the central control unit 10 of the completion of reading (in FIG. 7 of the first embodiment,
Steps S66 to S69).

According to the second embodiment, normal data (process data, program code data, etc.) and bit data are stored in n memory areas of a fixed data amount (see FIG. 9) in one memory device 50A. Storage areas can be allocated for error detection and correction or non-bit error detection and correction.

In this case, the writing and reading processes for the n fixed data amount storage areas are simplified. For example, unlike the first embodiment, since the changing address number is not specified for the storage area having the arbitrary data amount, the processing is not complicated. In other words, it suffices to specify the storage area of the fixed data amount of n by only specifying the flag number. For this reason, the internal structure is further simplified, the cost can be reduced, and it is particularly easy to adopt in low-priced products.

(Structure of Third Embodiment and Operation of Each Part) Next, a third embodiment will be described. FIG. 11 is a block diagram showing the main configuration of the third embodiment.

Referring to FIG. 11, this third embodiment is a memory device 50 or 50A of the first or second embodiment.
The information recording device 70 corresponding to the above is arranged on the wired / wireless communication network 71. Further, the communication device 72 for connecting the line in the wired / wireless section of the wired / wireless communication network 71 is provided as the W / R / ECC control device 20, 20.
Connected to A and further wired / wireless communication network 71
Also, a communication device 73 for establishing a line connection with the communication device 72 is provided.

The communication devices 72 and 73 are, for example, a communication control device / modem, a digital termination device / terminal adapter, etc. in the case of a wired section, and in the case of a wireless section.
It is a wireless transmission / reception terminal.

The transmission method (communication protocol) of the wired / wireless communication network 71 is TCP / IP.
(Transmission Control Protocol / Internet Protoco
l) is preferable from the viewpoint of versatility.

(Overall Operation of Third Embodiment) First and Second
The information recording device 70 corresponding to the memory devices 50 and 50A of the embodiment, the communication device 73 of the wired / wireless communication network 71, the communication device 72 of the W / R / ECC control devices 20 and 20A, and the two-way communication thereof Processing similar to that of the first and second embodiments is performed.

In the third embodiment, it is possible to correct a bit error caused by a transmission error in the wired / wireless communication network 71. (Advantages of Third Embodiment) As described above, in the third embodiment,
Information recording device 70 and W / R / ECC control device 20, 20
A is connected to A via a wired / wireless communication network 71. For example, one information recording device 70 has a large number of W / Rs.
-The ECC control devices 20 and 20A can be accommodated, and the degree of freedom of configuration and processing can be improved and the system scale can be increased.

(Structure of Fourth Embodiment and Operation of Each Part) The fourth embodiment will be described below. FIG. 12 is a block diagram showing the main configuration of the fourth embodiment.

Referring to FIG. 12, the fourth embodiment is an application of the first or second embodiment to a distributed computer system, for example, a local area network (LAN) such as Ethernet (registered trademark). ,
A LAN server 80 corresponding to the central control unit 10;
Alternatively, the W / R / ECC control device 20 or 2 of the second embodiment
The W / R / ECC control device 81 corresponding to 0A and the memory device 50 corresponding to the memory device 50 or 50A of the first or second embodiment are connected to the LAN transmission line 83.

LAN server 80, W / R / ECC
L in each of the control device 81 and the memory device 82
The AN interface device is not shown.

(Overall Operation of Fourth Embodiment) In the fourth embodiment, the LAN server 80 executes the same processing as the central controller 10 of the first or second embodiment. For example, Remote Procedure Call Control (RPC)
dure Call) performs the same processing as in the first or second embodiment.

(Advantages of Fourth Embodiment) In the fourth embodiment, the LAN server 80 can be used also as the central control unit 10 in the first or second embodiment, and the configuration thereof is simplified. , Configuration and processing (configuration design)
The degree of freedom of is improved.

(Explanation of Modifications of Embodiment) In the first and second embodiments described above, two bus lines BUS are used.
1 and BUS2 are arranged, the bus lines BUS1 and BUS2 may be integrated into one bus line.

Further, in the above-mentioned first, second and fourth embodiments, description is made using one memory device 50, 50A, but "one" here is normal data and bit error detection and correction. Alternatively, it means that no separate information storage medium for storing each data for non-bit error detection and correction is arranged. That is, as the memory devices 50 and 50A, a configuration in which a plurality of information storage media are connected in order to simply increase the amount of stored data is also a single memory device 50 or 50.
Included in using 0A.

Further, in the above-described first to fourth embodiments, the control units 23 and 23A store programs for executing the control of the respective embodiments. This program is provided by an information recording medium such as a ROM or a CD-ROM when the control units 23 and 23A are configured by MPU, and the data processing error detection and correction is performed by downloading and installing from the wired / wireless communication network. System and peripherals (eg,
The local area network (LAN) shown in FIG.
It can also be implemented in the server).

In the first, second, and fourth embodiments, the semiconductor memory device has been described as the memory device 50 and the memory device 50A, but other types of information recording media may be used. For example, the operations of the first and second embodiments can be realized even with a hard disk device (HDD). In this case, a large amount of data can be processed as compared with the semiconductor memory device.

In the first to fourth embodiments, an example in which the data processing error detection and correction system is applied to a computer has been described, but an apparatus requiring a data processing error detection and correction system other than the computer system (for example, It is also applicable to a node such as a communication protocol converter on a communication network).

The above-described modifications and further modifications are design matters that can be easily created by those skilled in the art, and are all included in the present invention.

[0159]

As is apparent from the above description, according to the data processing and error detection / correction method, system and program thereof of the present invention, the device scale and the processing scale are reduced and excessive quality is prevented. In addition, the reliability is improved, the flexibility of the configuration and the processing is improved, and the cost can be reduced.

Further, according to the present invention, there is an effect that the internal structure is further simplified and the cost can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration in a first embodiment of the present invention.

FIG. 2 is a diagram for explaining a storage area of the memory device according to the first embodiment.

FIG. 3 is a block diagram for explaining a schematic operation of the first embodiment.

FIG. 4 is a flowchart showing a procedure of processing for writing normal data in the memory device according to the first embodiment.

FIG. 5 is a flowchart showing a processing procedure of reading normal data from the memory device of the first embodiment.

FIG. 6 is a flowchart showing a data write processing procedure to a non-bit error detection and correction target storage area of the first embodiment.

FIG. 7 is a flowchart showing a data read processing procedure from a non-bit error detection / correction target storage area of the first embodiment.

FIG. 8 is a block diagram showing a configuration of a second embodiment.

FIG. 9 is a diagram for explaining a storage area of the memory device according to the second embodiment.

FIG. 10 is a block diagram for explaining a schematic operation of the second embodiment.

FIG. 11 is a block diagram showing a main configuration of a third embodiment.

FIG. 12 is a block diagram showing a main configuration of a fourth embodiment.

[Explanation of symbols]

10 Central control unit 20, 20A, 81 W / R ECC controller 21,26,29,31 registers 22, 32 comparator 23, 23A control unit 24 Address generator 27-bit error detection / correction data generator 25, 28, 40 selector 30-bit error detection and correction unit 50,50A, 82 memory device 70 Information recording device 71 Wired / Wireless communication network 72,73 Communication device 80 LAN server

Claims (17)

[Claims] 1. A method in an apparatus for selectively writing only input data and generating error detection / correction data for the written data, wherein a plurality of arbitrary storage units in one storage means are substantially used. A step of writing input data by selectively specifying a storage area in which error detection and correction of a data amount is performed and a storage area in which error detection and correction is not performed; and a step of reading the written data by designating the storage area. When the read is data from a storage area for performing the error detection and correction, a step of generating error detection and correction data from this data and the input data, and the generated error detection and correction data, Corresponding to the data read from the storage area for performing the error detection and correction,
A method of data processing and error detection and correction, further comprising the step of: specifying and storing a storage area for performing error detection and correction of the arbitrary data amount. 2. A method in an apparatus for selectively performing error detection / correction or non-error detection / correction on read data, comprising: error detection / correction of a plurality of arbitrary data amounts in substantially one storage means. A step of reading data by selectively specifying a storage area for performing the error detection and a storage area for which the error detection and correction are not performed; and a step of reading error detection and correction data stored in association with the read data, And a step of correcting the read data based on the read data for error detection and correction, and a method of data processing and error detection and correction. 3. As a selective designation for the storage area in which the error detection and correction of the plurality of arbitrary data amounts are performed and the storage area in which the error detection and correction is not performed, designation is made by information including numerical values of the start and end of the storage area. The data processing and error detection / correction method according to claim 1 or 2. 4. A method in an apparatus for selectively writing input data and selectively generating error detection and correction data for the written data, which is preset in substantially one storage means. Writing input data by selectively designating a storage area that performs error detection and correction of a plurality of fixed data amounts and a storage area that does not perform error detection and correction; and a step of reading the written data by designating the storage area And a step of generating error detection and correction data from the input data and data from a storage area in which the error detection and correction are performed, and the generated error detection and correction data is subjected to the error detection and correction. Corresponding to the data read from the storage area,
And a step of storing in a fixed data amount storage area for performing the error detection and correction, and a method of data processing and error detection and correction. 5. A method in an apparatus for selectively performing error detection / correction or non-error detection / correction on read data, comprising a plurality of preset fixed data amounts in substantially one storage means. Reading data by selectively specifying a storage area for performing error detection and correction and a storage area for not performing error detection and correction; and reading out error detection and correction data stored in association with the stored data And a step of performing error correction on the read data based on the read data for error detection and correction, and a method of data processing and error detection and correction. 6. As a selective designation for a storage area that performs error detection and correction of a plurality of preset fixed data amounts and a storage area that does not perform error detection and correction, the storage area is substantially assigned in advance for each storage area. 6. The method of data processing and error detection and correction according to claim 4 or 5, wherein the method is specified by one piece of information. 7. The method according to claim 1, further comprising a step of notifying the end of the step.
Method of data processing and error detection and correction described in paragraph. 8. A data processing error detection and correction system that selectively writes only input data and generates error detection and correction data for the written data, and outputs data for writing, In addition, a control device that receives read data and instructs writing or reading, and a storage area that is substantially composed of one and that performs error detection and correction of a plurality of arbitrary data amounts and a storage area that does not perform error detection and correction are provided. A storage device having, and based on an instruction from the control device, with respect to the storage device,
A data processing error detection and correction system comprising: a write or read (W / R) error detection and correction device that performs one or both of the following (a) and (b): (A) Input data, which is data for writing from the control device, is selectively designated and written into a storage area in which a plurality of arbitrary data amounts are subjected to error detection / correction and a storage area in which error detection / correction is not performed. Further, the error detection / correction data generated from the read data and the input data is stored in association with the written data by designating a storage area for performing the error detection / correction. (B) A plurality of arbitrary fixed data amounts are selectively designated for a storage area in which error detection and correction are performed and a storage area in which error detection and correction is not performed, and stored data and stored in association with this data The error detection / correction data that has been read is read out and the error is corrected. 9. A data processing error detection and correction system which selectively writes only input data and selectively generates error detection and correction data for the written data, and outputs data for writing, and A controller for receiving read data and instructing the writing or reading, and a storage area for performing error detection and correction of a plurality of fixed data amounts,
Substantially one storage device having a storage area that does not perform error detection and correction, based on an instruction of the control device, to the storage device,
A data processing error detection and correction system comprising: a write or read (W / R) error detection and correction device that performs one or both of the following (a) and (b): (A) Data to be written from the control device by selectively designating a plurality of preset fixed data amounts in the storage device that perform error detection and correction and storage regions that do not perform error detection and correction The input data is written, the written data is read by designating the storage area, and the data is read from the storage area where the error detection and correction is performed and the input data is used for error detection and correction. Is generated, is associated with the data read from the storage area for performing the error detection and correction, and is stored in the storage area for performing the error detection and correction. (B) In the storage device, the data and the data are associated with each other by selectively designating a storage area that performs error detection and correction of a plurality of preset fixed data amounts and a storage area that does not perform error detection and correction. The stored error detection / correction data is read, and the read data is error-corrected based on the read error detection / correction data. 10. The W / R error detection / correction device is provided with a storage area in the storage device that performs error detection / correction of a plurality of arbitrary data amounts, a storage area that does not perform error detection / correction, and error detection / correction. A plurality of storage means for storing information including numerical values at the beginning and end of the storage area for individually specifying the data area and the error detection and correction data area in the storage area to be performed; A plurality of comparing means for comparing the information and the instruction from the control device to indicate which storage area the individual designation is, and outputting a comparison result signal for discriminating the data amount; The data processing error detection and correction system according to claim 8, further comprising: 11. The W / R error detection / correction device includes a storage area for performing error detection / correction of a plurality of fixed data amounts, a storage area for not performing error detection / correction, and data in a storage area for performing error detection / correction. Area and error detection / correction data area, one storage means for storing substantially one information given in advance, and the information from the storage means and the instruction from the control device are compared, and the individual 10. The data processing error detection and correction system according to claim 9, further comprising: one comparison unit that outputs a comparison result signal that determines which storage area is specified. 12. The control device, a storage device, and a W / R
10. The data processing error detection and correction system according to claim 8 or 9, wherein a bus line is connected to the error detection and correction device. 13. The storage device and the W / R error detection / correction device are provided with communication means for connecting a line between the storage device and the W / R error detection / correction device in a wired section or a wireless section. The data processing error detection and correction system according to claim 8 or 9. 14. In (a) the control device and the W / R error detection / correction device, and (b) in the W / R error detection / correction device and the storage device, one or both of the (a) and (b) is local. 10. The data processing error detection and correction system according to claim 8 or 9, wherein the data processing error detection and correction system comprises a transmission unit including an area network, and the control unit is a communication control unit in the transmission unit. 15. The data processing error detection and correction system according to claim 8, wherein the storage device is a device having a semiconductor storage element or an information recording medium. 16. A program for causing a computer to execute one or both of the following (a) and (b). (A) A procedure for selectively designating a storage area in which a plurality of arbitrary data amounts are subjected to error detection / correction and a storage area in which no error detection / correction is performed, and a procedure for writing input data in the designated storage area, A procedure for reading the read data, and specifying the data for error detection and correction generated from the read data and the input data to be associated with the written data and to secure a storage area for performing the error detection and correction. Procedure to go and memorize. (B) A procedure of selectively designating a storage area in which a plurality of arbitrary fixed data amounts are subjected to error detection / correction and a storage area in which no error detection / correction is performed, and by this designation, the stored data and the data A procedure for reading the error detection and correction data stored in association with each other, and a procedure for performing error correction on the read data based on the error detection and correction data. 17. A program for causing a computer to execute one or both of the following (a) and (b): (A) A procedure for selectively designating a storage area for error detection and correction of a plurality of preset fixed data amounts and a storage area for which error detection and correction is not performed, and a procedure for writing input data to the storage area by this designation And a procedure of reading the written data by designating the storage area, and generating error detection and correction data from the input data and the data when the reading is from the storage area for performing the error detection and correction. A procedure and a procedure of associating the generated error detection and correction data with the data read from the storage area for performing the error detection and correction, and storing the data in the storage area for performing the error detection and correction. (B) A procedure for selectively designating a storage area in which a plurality of preset fixed data amounts are subjected to error detection / correction and a storage area in which error detection / correction is not performed, data by this designation, and correspondence with this data And a procedure for reading the stored error detection and correction data and correcting the read data based on the read error detection and correction data.