JP2003309190A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a semiconductor device having good transistor characteristics by forming an oxide film having different thicknesses at ends of active regions in NMOS and PMOS regions of the device. <P>SOLUTION: In a method of manufacturing the semiconductor device, the semiconductor device provided with the PMOS and NMOS regions is formed by forming an oxide film on a substrate and a polycrystalline silicon film only on the surface of the oxide film in the NMOS region. Then, silicon nitride films are formed on surfaces of the polycrystalline silicon films in the NMOS region and the oxide film in the PMOS region, and trenches are formed by etching the silicon nitride film, polycrystalline silicon film, oxide film, and substrate. In addition, heat treatment is performed by heating the substrate. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device. More specifically, the present invention relates to an element isolation technique for forming an element isolation region on a substrate of a semiconductor device.

[0002]

2. Description of the Related Art LOCOS (Local Oxid) has been known as an element isolation technique for forming an isolation region on a substrate.
ation of Silicon) separation is widely used. The isolation region is used for isolation between elements in order to eliminate electrical interference between elements formed on the substrate. In LOCOS, a pattern is formed on a Si ₃ N ₄ film that is an oxidation resistant film in each element formation region, and using this as a mask, the silicon substrate is selectively thermally oxidized to form an oxide film, which is then separated. Used as a region.

However, in LOCOS, at the edge of the Si ₃ N ₄ film used as a mask, there is a problem that bird's beak occurs and the element formation region is made small because oxidation proceeds laterally.

Therefore, as an alternative technique to the LOCOS method, STI (Shallow Trench Isol) is used.
Atio; shallow trench isolation) technology is drawing attention. This is because a trench is formed in a silicon substrate by etching, and CVD (Chemical Vapor Depos
It is embedded in SiO ₂ and CM
P (Chemical and Mechanical)
The isolation region is formed by flattening by polishing.

However, in the STI, the electric field is concentrated at the end of the STI, so that the threshold voltage of the local transistor at the end is lowered, and therefore a transistor having a high threshold voltage and a transistor having a low threshold voltage are connected in parallel. In such a state, an inverse narrow channel effect or a kink in the subthreshold region appears. Also,
As a result, off-leakage current increases in a transistor having a narrow gate width.

In order to solve such a problem, silicon is etched using a mask having a polycrystalline silicon film inserted between a silicon nitride film and a silicon oxide film, and then thermal oxidation is performed to separate it. There is a method of forming a region. FIG. 6 is a schematic cross-sectional view for explaining each step in forming a conventional isolation region, and FIG. 7 is a flowchart for explaining a conventional method for forming an isolation region. Further, FIG. 8 shows a semiconductor device including a PMOS region and an N region.
FIG. 8A is a schematic cross-sectional view showing a MOS region, and FIG.
The NMOS region, FIG. 8B shows the PMOS region.

As shown in FIG. 6A, the silicon substrate 2
Then, the silicon oxide film 4, the polycrystalline silicon film 6, and the silicon nitride film 10 are stacked (steps S52 to S56).

Next, as shown in FIG. 6B, a resist is applied to the surface of the silicon nitride film 10 to form a resist film, and the resist film is exposed and developed to form a resist pattern ( Step S58). After that, the silicon nitride film 10, the polycrystalline silicon film 6, and the silicon oxide film 4 are sequentially etched using the resist pattern as a mask (steps S60 to S64).

Next, as shown in FIG. 6C, the silicon substrate 2 is etched using the silicon nitride film 10, the polycrystalline silicon film 6 and the silicon oxide film 4 as a mask (step S66) to form the trench 14. Form. Next, FIG.
As shown in (d), thermal oxidation is performed (step S6).
8).

As described above, by inserting the polycrystalline silicon film 6 between the silicon nitride film 10 and the silicon oxide film 4, the polycrystalline silicon film 6 is oxidized together with the silicon substrate 2 during thermal oxidation. Can be made. Therefore, S
Since the gate oxide film in the vicinity of the TI upper end portion 16 can be rounded to have a substantial thickness, it is possible to suppress the concentration of the electric field.

However, as shown in FIG. 8A, the CMO
The channel region of NMOS in S is p-type doped with B or the like. On the other hand, as shown in FIG. 8B, the channel region in the PMOS region is an n-type semiconductor doped with As or the like.

Therefore, after a certain heat treatment process, the distribution of impurities in the lateral direction (gate width direction) in the channel region is different. That is, on the side of the B-doped NMOS region, after a certain amount of heat treatment, the concentration at the channel end becomes thinner than that at the channel center, and if the gate oxide film is uniform, The threshold voltage at the end is lower than that at the part. Therefore, the reverse narrow channel effect occurs in the NMOS region.

On the other hand, on the side of the PMOS region doped with As, after a certain heat treatment process, segregation occurs toward the channel end portion with respect to the channel center portion, and the concentration of As increases, so that the gate oxide film is formed. If it is uniform, the voltage at the end portion rises with respect to the center portion of the channel.
Therefore, a narrow channel effect occurs in the PMOS region.

Therefore, when the STI and its peripheral shape are the same, the lateral impurity distribution in each channel in the NMOS region and the PMOS region is different. Therefore, NM
The OS region and the PMOS region have different degrees of narrow channel and reverse narrow channel effects.

[0015]

As described above,
According to the conventional method, the thickness of the gate oxide film near the STI upper end portion 18 can be substantially increased. Therefore, the reverse narrow channel effect at the upper end of the STI is suppressed. However, in the NMOS area and the PMOS area,
It is difficult to suppress the inverse narrow channel effect and the narrow channel effect caused by heat treatment.

Accordingly, the present invention is directed to the NMOS region, PMO
It is an object of the present invention to propose an improved method for manufacturing a semiconductor device for the purpose of realizing a transistor in which the reverse narrow channel effect and the narrow channel effect are suppressed in the S region.

[0017]

According to the method of manufacturing a semiconductor device of the present invention, in the method of forming a semiconductor device having a PMOS region and an NMOS region, an oxide film forming step of forming an oxide film on a substrate, and the NMOS. Forming a polycrystalline silicon film on the surface of the oxide film only in a region, and forming a polycrystalline silicon film on the surface of the oxide film in the NMOS region and the oxide film in the PMOS region.
A silicon nitride film forming step of forming a silicon nitride film,
The method includes an etching step of etching the silicon nitride film, the polycrystalline silicon film and the oxide film, a trench forming step of etching the substrate to form a trench, and a heat treatment step of heating the substrate.

Further, in the method for manufacturing a semiconductor device according to the present invention, in the step of forming the polycrystalline silicon film, a step of forming a polycrystalline silicon film on the surface of the oxide film, and a resist film on the surface of the polycrystalline silicon film. And patterning the resist film, etching using the resist film as a mask to selectively remove only the polycrystalline silicon film on the PMOS region side, and removing the resist film And a process.

Further, in the method of manufacturing a semiconductor device according to the present invention, instead of the polycrystalline silicon film, a polycrystalline silicon film into which impurities are implanted is used.

In the method of manufacturing a semiconductor device according to the present invention, an amorphous silicon film is used instead of the polycrystalline silicon film.

Further, in the method of manufacturing a semiconductor device according to the present invention, an amorphous silicon film in which impurities are implanted is used instead of the polycrystalline silicon film.

[0022]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. In the drawings, the same or corresponding parts are designated by the same reference numerals, and the description thereof will be omitted or simplified.

Embodiment. 1A to 1E are schematic cross-sectional views for explaining each step of forming a trench in a silicon substrate of a semiconductor device in an embodiment of the present invention. In addition, FIGS. 2A to 2E are schematic views for explaining the step of forming a gate after forming a trench in this embodiment. Also, FIG.
3A and 3B are schematic cross-sectional views showing a transistor portion of a semiconductor device formed in this embodiment, FIG. 3A is a cross-sectional view, and FIG. 3B is a top view. is there. 4 and 5 are flow charts for explaining the method for forming the semiconductor device of the present invention.
Shows a step of forming a trench in a substrate, and FIG. 5 shows a step of forming a gate thereafter. 1 to 5 below
A method of forming the isolation region in this embodiment will be described with reference to.

First, as shown in FIG. 1A, a silicon oxide film 4 is formed on the surface of a silicon substrate 2 (step S2), and a polycrystalline silicon film 6 is further formed on the surface of the silicon oxide film 4. It is formed (step S4). Here, the silicon oxide film 4 is formed by thermal oxidation to a thickness of about 10 to 20 nm, and the polycrystalline silicon film 6 is formed by LPCVD.
A film having a thickness of about 50 to 100 nm is formed by (reduced pressure CVD).

Next, a resist is applied to the surface of the polycrystalline silicon film 6 to form a resist film 8 (step S
6), exposure and development processing is performed to form the resist film 8
Is patterned (step S8). This allows
The resist film 8 on the PMOS region side is removed, leaving only the resist film 8 on the NMOS region. Then, the polycrystalline silicon film 6 is etched using the resist film 8 as a mask (step S10). As a result, as shown in FIG. 1B, the polycrystalline silicon film in the PMOS region is removed, and the polycrystalline silicon film 6 is left only in the NMOS region.

Next, the resist film 8 on the polycrystalline silicon film 6 is removed (step S12). Then LPCVD
To form the silicon nitride film 10 (step S1
4), the silicon nitride film 10 is planarized by CMP (step S16). Thus, as shown in FIG. 1C, the silicon oxide film 4 in the PMOS region and the NM
A silicon nitride film 10 is formed on the polycrystalline silicon film 6 in the OS region. Here, the silicon nitride film 10
Are formed to have a thickness of about 200 to 300 nm in the PMOS region.

Next, a resist film 12 is applied on the silicon nitride film 10 and exposed and developed to form a resist pattern (step S18).
Using the resist film 12 having this resist pattern as a mask, the silicon nitride film 10 is etched (step S20), and then the polycrystalline silicon film 6 and the silicon oxide film 4 are etched (step S20).
22-S24). Thus, as shown in FIG. 1D, a hard mask of a laminated film including the silicon nitride film 10, the polycrystalline silicon film 6 and the silicon oxide film 4 is formed.

Next, as shown in FIG. 1E, the silicon substrate 2 is etched using the laminated film as a mask to form trenches 14 (step S26). Here, the trench 14 is an opening having a width of 0.2 μm.

Next, as shown in FIG. 2A, the silicon oxide film is heat-treated (step S28). As a result, the exposed portions of the silicon substrate 2 and the polycrystalline silicon film 8 are oxidized, and the silicon oxide film 16 is formed on the inner wall of the trench 14 and the side surface of the polycrystalline silicon film 8. At this time, in the vicinity of the upper end portion 18 of the trench in the NMOS region, the shape is rounded up and down. Also, the PMOS
In the region 18 near the upper end of the trench, only the lower portion has a shape with rounded corners.

Next, as shown in FIG. 2B, for example,
The oxide film 2 is formed in the trench 14 by high density plasma CVD.
0 is embedded (step S30), and flattening is performed by the CMP method (step S32). At this time, the silicon nitride film 10 serves as a stopper.

Subsequently, as shown in FIG. 2C, the nitride film 10 and the polycrystalline silicon film 6 are removed by wet etching (step S34). After that, Figure 2
As shown in (d), the silicon oxide film 16 is removed by etching (step S36). At this time, the flat portion of the silicon oxide film 16 is removed, but the trench 14
In the vicinity of the upper end portion 18, since the silicon oxide film 16 is thicker due to the rounded corners, the difference in thickness causes
The silicon oxide film 16 remains.

Next, as shown in FIG. 2E, the silicon oxide film 22 is formed again by thermal oxidation (step S38). Then, patterning is performed (step S4
0), and using this as a mask, well injection is performed (step S42). Subsequently, the silicon oxide film is removed, and the gate oxide film 24 is formed by thermal oxidation (step S46),
After forming the gate 26 (step S48) and the like, as shown in FIG.
A transistor portion of the semiconductor device is formed as shown in (a) and (b).

The structure of the silicon substrate in which the trench is formed as described above will be described with reference to FIG.
The silicon substrate 2 has an NMOS region and a PMOS region. In FIG. 2, the left side shows the NNOS region and the right side shows the PMOS region.

An oxide film 16 is formed on the surface of the silicon substrate 2 in both the NMOS region and the PMOS region.
Further, the trench 14 formed by the above method is provided between the NMOS region and the PMOS region. The trench 14 is a groove for forming STI later.

A polycrystalline silicon film 6 is formed on the surface of the silicon oxide film 16 in a portion of the NMOS region where the trench 14 is not formed. Since the silicon oxide film 16 is formed by thermal oxidation, it is formed in the exposed portion of the silicon substrate 2 and the exposed portion of the polycrystalline silicon 6. A silicon nitride film 10 is further formed on the surface of the polycrystalline silicon in the NMOS region.

On the other hand, in the PMOS region, the silicon nitride film 10 is formed on the surface of the oxide film 16 in the portion where the trench is not formed.

In the NMOS region and the PMOS region, the surface portion where the silicon nitride film 10 is formed is at the same height, but in the NMOS region, the polycrystalline silicon film 6 and the silicon nitride film 10 are laminated. On the other hand, in the PMOS region, only the nitride film 10 is formed. Therefore, the silicon nitride film 10 in the PMOS region is thicker than the silicon nitride film 10 in the NMOS region by the thickness of the polycrystalline silicon film 8 in the NMOS region.

The silicon oxide film 16 is formed by thermal oxidation after forming the trench. By this thermal oxidation, the corners are rounded near the upper end portion 18 of the trench 14. That is, in the NMOS region, in the vicinity of the upper end 18 of the trench 14, oxidation proceeds to both sides of the silicon substrate 2 and the polycrystalline silicon 6, so that the corners are rounded up and down. On the other hand, in the PMOS region, since the oxidation proceeds only to the silicon substrate 2 side, the corners are rounded only to the lower side.

By performing various steps on the silicon substrate in the state shown in FIG. 2A, the state in which the gate is formed as shown in FIG. 3A can be obtained. At this time, the silicon oxide film 16 portion is removed and a gate oxide film 24 is newly formed. However, even after such a process, since the rounded corner portion near the upper end 18 of the trench 14 is thicker than the other portions, the silicon oxide film 16 is left to some extent. Therefore, FIG.
As shown in FIG.
The corners 4 are rounded and formed thicker than the gate oxide film 24 in the PMOS region.

As described above, the NMOS region and P
In the MOS region, near the upper end 18 of the trench 14, that is,
Oxide films having different thicknesses can be formed at the ends of the active region. Therefore, it is possible to obtain trenches having different shapes in the NMOS region and the PMOS region.
While suppressing the concentration of the electric field at the edge of the
The reverse narrow channel effect in the region and the narrow channel effect in the PMOS region can be suppressed, and good transistor characteristics can be obtained.

In this embodiment, the NMO
In the process of leaving only the polycrystalline silicon in the S region, PM
The OS region was etched. However, the present invention is not limited to this, and polycrystalline silicon may be formed from the beginning in the NMOS region.

In this embodiment, the polycrystalline silicon film 6 is used as a part of the hard mask. However, the present invention is not limited to this, and amorphous silicon, polycrystalline silicon doped with impurities, amorphous silicon, or the like may be used. Further, these have a high oxidation rate and can be processed more rapidly.

The method of forming each film and the method of planarization are as follows.
The invention is not limited to the one described in this embodiment.

In this embodiment, for example,
By performing step S2, the oxide film forming step of the present invention is performed, for example, performing steps S4 to S12, the polycrystalline silicon film forming step is performed, and, for example, step S14 is performed. ,
A silicon nitride film process is performed, for example, step S2
The etching step is performed by performing steps 0 to S24, and the trench forming step is performed by performing step S26, for example.

Further, for example, in this embodiment,
By performing step S4, a step of forming a polycrystalline silicon film is performed, and for example, steps S6 to S
8 is performed to pattern the resist film, for example, step S10 is performed to selectively remove the polycrystalline silicon film, and step S12 is performed, for example. A step of removing the resist film is performed.

[0046]

As described above, according to the present invention, it is possible to form oxide films having different thicknesses at the end of the active region in the NMOS region and the PMOS region. Therefore, since different trench shapes can be obtained, the reverse narrow channel effect in the NMOS region, the PMOS
The narrow channel effect in the region can be suppressed, and favorable transistor characteristics can be obtained.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view for explaining each step of forming a trench in a silicon substrate of a semiconductor device in an embodiment of the present invention.

FIG. 2 is a schematic diagram for illustrating a step of forming a gate after forming a trench in the embodiment of the present invention.

FIG. 3 is a schematic cross-sectional view showing a transistor portion of a semiconductor device according to an embodiment of the present invention.

FIG. 4 is a flowchart for illustrating a method for forming a semiconductor device according to the embodiment of the present invention.

FIG. 5 is a flowchart for illustrating a method for forming a semiconductor device according to the embodiment of the present invention.

FIG. 6 is a schematic cross-sectional view for explaining each step in forming a conventional separation region.

FIG. 7 is a flowchart for explaining a conventional method of forming a separation region.

FIG. 8 is a schematic sectional view showing a PMOS region and an NMOS region of a semiconductor device.

[Explanation of symbols]

2 Silicon substrate 4 Silicon oxide film 6 Polycrystalline silicon film 8 Resist film 10 Silicon nitride film 12 Resist film 14 trench 16 Silicon oxide film 18 Near the top of the trench 20 oxide film 22 Silicon oxide film 24 Gate oxide film 26 gates 28 sources 30 drain

[Procedure amendment]

[Submission date] April 18, 2002 (2002.4.1)
8)

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be amended] Title of invention

[Correction method] Added

[Correction content]

Title: Method for manufacturing semiconductor device

Claims (5)

[Claims] 1. A method of forming a semiconductor device having a PMOS region and an NMOS region, the method comprising: forming an oxide film on a substrate; and forming a polycrystalline silicon film on the surface of the oxide film only in the NMOS region. Forming a polycrystalline silicon film, forming the polycrystalline silicon film in the NMOS region and the PM
A silicon nitride film forming step of forming a silicon nitride film on the surface of the oxide film in the OS region; an etching step of etching the silicon nitride film, the polycrystalline silicon film and the oxide film; and a step of etching the substrate. A method of manufacturing a semiconductor device, comprising: a trench forming step of forming a trench; and a heat treatment step of heating the substrate. 2. The step of forming a polycrystalline silicon film, the step of forming a polycrystalline silicon film on the surface of the oxide film, the step of forming a resist film on the surface of the polycrystalline silicon film, and patterning the resist film A step of performing etching using the resist film as a mask to selectively remove only the polycrystalline silicon film on the PMOS region side; and a step of removing the resist film. The method for manufacturing a semiconductor device according to claim 1. 3. The method for manufacturing a semiconductor device according to claim 1, wherein a polycrystalline silicon film into which impurities are implanted is used instead of the polycrystalline silicon film. 4. The amorphous silicon film is used in place of the polycrystalline silicon film.
A method of manufacturing a semiconductor device according to item 1. 5. The method of manufacturing a semiconductor device according to claim 1, wherein an amorphous silicon film into which impurities are implanted is used instead of the polycrystalline silicon film.