JP2003297975A - Substrate for mounting semiconductor and its producing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a substrate for mounting a semiconductor having mounting lands of solder ball or inner layer joint lands of multilayer structure where the wet area of the land and solder is large, having no angular structure becoming a stress concentrating point, having no irregularities of circuit on the semiconductor element mounting face and exhibiting excellent reliability of packaging and joint by preventing troubles of microvoids, and the like, in the underfilling or resin sealing process at the time of packaging. <P>SOLUTION: In the method for producing a substrate for mounting a semiconductor, conductor posts formed on a conductive frame are jointed to a substrate being jointed through a jointing metallic material and an adhesive layer and then lands are formed through a step for removing the conductive frame. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor mounting substrate and a method for manufacturing the same.

[0002]

2. Description of the Related Art In recent years, high-density integration and high-density mounting of electronic components have been advanced in response to demands for higher functionality, lighter, thinner, shorter and smaller electronic devices. Semiconductor devices used in these electronic devices are becoming smaller and have more pins.

With the miniaturization of semiconductor devices, there is a limit to miniaturization in conventional devices using a lead frame, and therefore, recently, semiconductor elements are mounted on a semiconductor mounting substrate. As a thing, BGA (Ball
Grid Array) and CSP (Chip Sca)
A new area mounting type device system such as a le package) has been introduced. In these semiconductor devices, a structure in which semiconductor elements are mounted on a semiconductor mounting substrate called an interposer is mainly used in order to rearrange the electrodes of the semiconductor elements in an area type and to match the pitch with the wiring terminals of the mounting substrate. Has become. As the interposer, a flexible printed board, a glass epoxy resin laminated board having a rigid property, or a ceramic laminated board is used.

The wiring of these interposers tends to have a high density, and a built-up multilayer wiring structure is adopted. The interposer having a multilayer wiring structure is
Generally, since the wiring layers formed on the insulating layer are stacked, the unevenness due to the conductor wiring pattern is formed on the mounting surface of the outermost semiconductor element. In this case, particularly in a wiring pattern with a narrow pitch, there is a problem that underfill injection at the time of flip chip mounting and micro voids generated in the resin sealing process lower the package reliability and mounting reliability of the semiconductor device. It could happen.

Further, a land for connecting a semiconductor element or a land for mounting on a substrate has a rectangular convex structure 101 as shown in FIG. 1A (FIG. 1B is an enlarged sectional view). (For example, refer to Patent Document 1.). In some cases, stress concentration due to thermal stress occurs at the joints mounted with solder balls, and disconnection defects may occur due to solder ball cracks. In addition, the land was sometimes roughened to increase the wetted surface area of the solder ball and the land. However, the exposed wiring pattern is also roughened, so that the wiring is particularly miniaturized. As a result, there is a problem that the possibility of disconnection failure increases.

On the other hand, by covering the wiring pattern with a solder resist, it becomes possible to reduce the unevenness of the wiring pattern on the semiconductor element mounting surface or the board mounting surface. In this case, a land for connecting a semiconductor element or a land for mounting on a substrate is generally formed by forming an opening in a solder resist (for example, refer to Patent Document 2). In this case, a rectangular concave structure 20 as shown in FIG.
1 (FIG. 2B is an enlarged cross-sectional view), and the solder resist surface, the side surface of the opening and the solder ball cannot be joined, so that the mounting surface area may be relatively small.

Also, the edge of the solder resist opening,
The joint interface of the solder balls may become a stress concentration point due to thermal stress, which may lead to a decrease in mounting reliability such as a crack in the solder joint. Further, it is undeniable that as the opening of the solder resist becomes finer, the solder ball may become defectively joined due to the residue of the resist.

From the viewpoint of stress relaxation of the joint portion, the land itself is often not provided with a stress relaxation function, and the shape and material of the underfill or the bump as a connection terminal is generally devised. Target. Further, in an interposer having a multi-layer wiring structure, the inner wiring layer layers may be electrically connected by soldering, but there is a problem in the joint reliability similar to the above.

[0009]

[Patent Document 1] Japanese Patent Laid-Open No. 3-71649 (FIG. 1)

[Patent Document 2] Japanese Unexamined Patent Publication No. 1-196843 (2nd paragraph, 1st paragraph)
(Fig. 2)

[0010]

SUMMARY OF THE INVENTION The present invention has a semiconductor element and a land for mounting to the outside or a land for inner layer interlayer bonding, and has a rectangular convex shape which becomes a stress concentration point at a conductor bonding portion. A semiconductor that does not have a rectangular concave structure due to the structure or solder resist, does not have circuit irregularities on the semiconductor element mounting surface, prevents underfill injection during mounting and micro voids in the resin sealing process, and has excellent mountability and reliability An object is to provide a mounting board.

[0011]

SUMMARY OF THE INVENTION The inventors of the present invention have proposed that a land connecting to a connection terminal of a semiconductor element or a mounting board has a specific shape, and a conductor post formed on a conductive frame is covered. It was found that a semiconductor mounting substrate having excellent mountability and reliability can be obtained by forming a land by transfer by joining to a joining substrate through an alloy material and an adhesive layer, and through the step of removing the conductive frame. The present invention has been completed.

That is, according to the present invention, (1) in a substrate having a land for connecting a semiconductor element on the surface, the land having the same arrangement as the external connection terminal of the semiconductor element has a concave sectional structure. Semiconductor mounting board,
(2) In a substrate having a land for connecting to the outside on the surface, the semiconductor mounting substrate having a recessed sectional structure in which the lands in the same arrangement as the connection terminals on the mounting substrate side,
(3) The semiconductor mounting substrate according to item (1) or (2), which has a wiring layer having a multi-layered structure inside and a land corresponding to an interlayer connection portion of the wiring layer has a concave sectional structure. ,
(4) The conductive frame on which the conductor posts are formed is joined to the substrate to be joined through the joining metal material and the adhesive layer,
A method for manufacturing a semiconductor mounting substrate, characterized in that the conductive frame is removed to form lands, (5) a step of roughening the conductive frame, and forming a plating resist on the surface of the conductive frame. And a step of forming an opening in the plating resist by a photolithography method,
Forming a conductor post A by electrolytically plating the opening with the conductive frame as a lead for electrolytic plating;
A step of removing the resist, a step of roughening the exposed surfaces of the conductive frame and the conductor posts A, a step of forming a second plating resist (plating resist B), and a step of forming a photo resist on the plating resist. A step of forming an opening including the conductor post A by a litho step, a step of forming a barrier metal and a conductor post B by electrolytic plating of the opening using the conductive frame as a lead for electrolytic plating, and the conductor A step of forming a bonding metal material layer on the exposed surface of the post B, and a step of peeling off the plating resist,
A step of forming an adhesive layer, and a separately manufactured substrate having a layer to be connected, via the adhesive layer, a portion to be joined of the substrate having the layer to be connected and the conductor post B to the metal material for joining. A method for manufacturing a semiconductor mounting substrate, comprising: a step of joining via a layer; and a step of removing the conductive frame and the conductor post A by etching, (6) The second plating resist is not peeled off. Which becomes a permanent resist (insulating layer), and in the step of forming an opening including the conductor post A in the plating resist, the manufacturing of the semiconductor mounting substrate described above in which the opening is formed by a photolithography process or a laser process. Method (7) roughening the conductive frame, forming a plating resist on the surface of the conductive frame, and opening the plating resist by a photolithography method. A step of forming a conductive post A by electrolytically plating the opening with the conductive frame as a lead for electrolytic plating, a step of removing the resist, the exposed conductive frame and conductive post The step of roughening the surface of A, the step of forming a second plating resist (plating resist B), and the conductor post A on the plating resist by a photolithography process.
Forming a barrier metal and a wiring layer by electroplating the opening using the conductive frame as a lead for electroplating; removing the plating resist B; Forming an insulating resin layer on the surface of the wiring layer and the conductive frame, processing a via hole reaching the wiring layer on the surface of the insulating resin layer, and forming a conductor post C by filling the via hole. Obtained from the above steps, a step of forming a bonding metal material layer on the exposed surface of the conductor post C, a step of forming an adhesive layer, a step of removing the conductive frame and the conductor post A by etching, A plurality of wiring layers having the conductor posts C (wiring layers with conductor posts C) and a wiring layer with a conductive frame having the conductor posts A obtained in the above step via the adhesive layer. A step of joining the portion to be joined and the conductor post C via the joining metal material layer, and a step of removing the conductive frame and the conductor post A of the wiring layer with the conductive frame by etching. A method for manufacturing a semiconductor mounting substrate, which is characterized.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings, but the present invention is not limited thereto.

3 to 8 are views for explaining an example of a method of manufacturing a semiconductor mounting substrate according to an embodiment of the present invention.

In the method for manufacturing a semiconductor mounting substrate of the present invention, first, the conductive frame 301 is roughened,
Next, the plating resist 302 is formed (FIG. 3A).
Any material may be used as the material of the conductive frame 301 as long as it has a function as a lead (cathode electrode) at the time of electrolytic plating and resistance to chemicals used and can be finally removed by etching. However, examples thereof include copper, copper alloy, 42 alloy, nickel, iron and the like. Further, as the chemical solution used for the roughening treatment, any material can be used as long as it can form a minute concavo-convex structure with respect to the material of the conductive frame 301. Examples are nitric acid-based and hydrogen peroxide. And sulfuric acid, ammonia compounds, and formic acid chemicals can be used. As the plating resist 302, for example, a via film 303 can be formed by laminating an ultraviolet-sensitive dry film resist on the conductive frame 301, pattern-sensitizing it with an exposure mask or the like, and then developing (FIG. 3 ( b)). As the exposure mask, a lith film, a glass dry plate, a chromium vapor deposition dry plate, or the like can be used. As the developing solution, an aqueous solution of potassium, sodium, or lithium carbonate or hydroxide, tetramethylammonium hydroxide, or the like can be used.

Next, using the conductive frame 301 as a lead for electrolytic plating, electrolytic plating is deposited from the bottom of the via to form a conductor post A304. Conductor post A30
Since the purpose of forming 4 is a mold for forming a land having a concave structure, a material that can be etched in the final step is desirable. For example, copper, copper alloy, 42 alloy, nickel, iron and the like can be mentioned, but if they are the same as the material of the conductive frame 301, they can be removed by etching at the same time, so that it is even more preferable from the viewpoint of process shortening.

Next, the plating resist 302 is peeled off.
As the chemical solution used for peeling, an aqueous solution of an alkali metal carbonate or hydroxide, a mixed solution of tetramethylammonium hydroxide, monoethanolamine, or the like can be used. In addition, there is a concern that the resist residue may be removed at the time of stripping, but it may be possible to remove it with an aqueous solution of potassium permanganate, dimethyl sulfoxide, or the like.

Next, a second plating resist (plating resist B) 305 is formed (FIG. 3E). At this time, the opening 30 is formed so that the conductor post A304 is exposed.
6 is processed. As a method of opening, a photolithography method, a laser method, a plasma method, or the like can be used, and a method suitable for the plating resist B305 can be selected. Next, the conductor post A304 exposed in the opening 306 and the surface of the conductive frame 301 are subjected to a roughening treatment to form a fine concavo-convex structure 307 (FIG. 3F). Next, the conductive frame 301 is used as a lead for electroplating to form the fine concavo-convex structure 30.
7. A barrier metal 308 is deposited on the surface of FIG.
(G)). The barrier metal 308 is formed after roughening is
In the final step, the conductive frame 301 and the conductor post A30
4 is a stop layer when etching away, and becomes the surface of the solder ball mounting land after exposure. Therefore, it is desirable to form the minute concavo-convex structure 307 from the viewpoint that the bonding strength can be secured by the increase of the mounting area and the anchor effect. Further, the material of the barrier metal 308 may be any as long as it achieves the above purpose. Examples are nickel, gold,
Examples thereof include tin, silver, tin-silver based solder, eutectic solder, and palladium, but gold is most preferable for reasons such as corrosion resistance. It should be noted that the conductor post A30 is added to the chemical liquid used when the conductive frame 301 is removed by etching.
If 4 is resistant, the barrier metal 308 can be omitted.

Next, a conductor post B is formed on the surface of the barrier metal 308 by using the conductive frame 301 as a lead for electrolytic plating.
401 is formed (FIG.4 (h)). Since the opening 306 of the resist B305 is filled by electrolytic plating, the tip shape of the conductor post B401 can be controlled more easily than in the conductive paste printing method. The material of the conductor post B401 may be any material as long as it is suitable for this manufacturing method, and examples thereof include copper, nickel, gold, tin, palladium, bismuth, and a composite system of these metal species. In particular, by applying copper, the conductor post B401 having excellent resistance characteristics can be obtained.

Next, a metal material layer 402 for bonding is formed on the surface (tip) of the conductor post B401 (FIG. 4).
(I)). Examples of the method of forming the bonding metal material layer 402 include a method of forming the conductive frame 301 as a lead for electrolytic plating by electrolytic plating, a method of forming by electroless plating, and a method of paste printing. In the method by printing, it is necessary to accurately align the screen mask for printing with the conductor post B401, but in the plating method, the bonding metal material layer 401 is not formed on the surface other than the surface of the conductor post B401. Therefore, it is easy to deal with miniaturization and high density of the conductor post B401. In particular, the method using electrolytic plating is preferable because it has a wider variety of metals that can be plated and the chemical solution is relatively easy to manage than the method using electroless plating. As a material of the bonding metal material layer 402, as shown in FIG.
As long as it can be alloyed and joined to the joined portion 504 of the separately manufactured wiring board (substrate having the connected layer) 503 shown in (h), it can be liquefied in a relatively low temperature region such as solder. What you do is suitable. Among solder, lead, tin,
It is preferable to use a solder composed of at least two kinds of silver, copper, bismuth, indium, zinc and gold. In recent years, in particular, the use of lead-free solder is very suitable from the viewpoint of environment. In FIG. 4 (i), the conductor post B40
Although the example of forming the bonding metal material layer 402 on the surface of No. 1 is shown, the bonding metal material layer 402 is intended to bond the conductor post B401 and the bonded portion 504,
The bonding metal material layer 402 may be formed on the bonded portion 504 side. Furthermore, the conductor post B401 and the joined portion 5
The metal material layer 402 for bonding may be formed on both surfaces of 04.

Next, when a photosensitive dry film is used as the plating resist B305, the plating resist B30
5 is peeled off, and an adhesive layer 403 is formed on the exposed surface of the conductor post 401 and the bonding metal material layer 402, whereby a conductor post layer 405 is obtained (FIG. 4 (j-1)). The adhesive layer 403 is formed by a method suitable for the resin form to be applied, and the resin ink is directly applied by a method such as printing or coating.
Alternatively, a dry film type resin is formed by a method such as laminating and pressing (normal pressure, vacuum). Further, when the plating resist B305 is a permanent resist, the plating resist B305 can be used as it is as an insulating layer between the conductor posts without peeling, and a shortening of the process can be expected. Further, when it is necessary to avoid a defect at the time of forming the adhesive layer due to a peeling residue which may be concerned as the pitch of the conductor posts becomes finer, the adhesive layer 404 is replaced with a plating resist B305 (which becomes a part of the insulating layer). The conductor post layer 406 is obtained by forming it on the surface of the metal layer for joining the conductor posts (FIG. 4 (j-
2)).

An example of an embodiment in which an interlayer joint portion of a substrate having a multilayer structure is formed by the method for manufacturing a semiconductor mounting substrate of the present invention will be described with reference to FIG.

First, after the conductor post A 504 and the second plating resist B 505 are formed (FIGS. 5A to 5D) by the same process as described above, a barrier metal 507 is formed in the opening 506 of the plating resist B 505. (Fig. 5
(E)). Here, the opening 506 is formed at a position corresponding to a desired wiring pattern. Next, the conductive frame 501 is used as a lead for electrolytic plating to form a barrier metal 5
The plated wiring layer 508 is formed on the surface of 07 (FIG. 5).
(F)). The material of the plated wiring layer 508 may be any as long as it is suitable for this manufacturing method.
For example, copper, nickel, gold, tin, palladium, bismuth, or a composite system of these metal species may be mentioned. Particularly, by applying copper, the plated wiring layer 508 having excellent resistance characteristics can be obtained.

Next, the plating resist B505 is peeled off,
A wiring layer 514 with a conductive frame is obtained (FIG. 5).
(G)). An insulating resin layer 509 is formed on the exposed surfaces of the plated wiring layer 508 and the conductive frame 501 (FIG. 5).
(H)). Next, a via hole is formed in the insulating resin layer 509 by using CO ₂ , UV laser or the like to form a conductor post C.
By forming 510, the bonding metal material 511, and the adhesive layer 512, the conductive framed wiring layer 515 is obtained (FIG. 5 (i)). The conductor post C510, the bonding metal material 511, and the adhesive layer 512 can be implemented in the same steps as described above. Next, the conductive frame 501 is removed by etching to obtain a wiring layer 513 with conductor posts C (FIG. 5 (j)).

As the resin forming the adhesive layers 403, 404 and 512, any resin can be used as long as it is suitable for the manufacturing method. For example, epoxy, phenol, bismaleimide, bismaleimide triazine,
Triazole, polycyanurate, polyisocyanurate, benzocyclobutene, polyamide, polyimide, polyamideimide, polyetherimide, polyesterimide, polyetheretherketone, polyphenylene sulfide, polyquinoline, polynorbornene, polybenzoxazole, polybenzimidazole, etc. Resins of can be used. These resins may be used alone or in combination of two or more.

The conductor post layers 601 and 602 (405 in FIG. 4) obtained by the above steps are aligned with the wiring board 603 prepared in advance (FIG. 6 (k)). The alignment is performed by the conductor post layers 601, 602 and the wiring board 60.
3, a method of reading and aligning a pre-formed positioning mark by an image recognition device, and a conductor post layer 6
01, 602 and the wiring board 603, a method of mechanically aligning by inserting guide pins for alignment into guide holes formed in advance (pin lamination) or the like can be applied. Also, the wiring board 603
May be a single layer or multiple layers, and can be used in the form of a film or a rigid.

Next, the conductor post layers 601 and 602 and the wiring board 603 are laminated. As a stacking method, for example, using a vacuum press, pressure is applied until the conductor post B604 is bonded to the bonded portion 607 of the wiring layer by the bonding metal material layer 606 via the adhesive layer 605, and further heating is performed. The adhesive layer 605 is heat-cured to form the conductor post layer 60.
1, 602 and the wiring board 603 can be bonded. Here, the conductor post layers can be laminated not only on the semiconductor mounting surface of the wiring board but also on the board mounting surface (FIG. 6).
(L)).

Next, the conductive frame 608 and the conductor post A609 of the conductor post layers 601 and 602 are removed by etching. The barrier metal 610 is the conductive frame 6
08 and the conductor post A609 have resistance to a chemical solution used for removing the conductor post A609 by etching, so that the conductor post B604 is not corroded or corroded. When the material of the conductive frame 608 and the conductor post A609 is copper and the material of the barrier metal 610 is nickel, tin, or various solders, a commercially available ammonia-based etchant can be used. In addition, the conductive frame 608 and the conductor post A6
When the material of 09 is copper and the material of the barrier metal 610 is gold or silver, most commercially available etchants can be used. Considering that the barrier metal 610 also serves as the mounting surface of the semiconductor element, gold is most preferable in terms of surface cleanliness, stability, and mounting reliability. In the case of gold, the roughening treatment of the surface becomes very difficult, but according to the manufacturing method of the present invention, the conductive frame 608 and the conductor post A609 are roughened before the gold plating as the barrier metal 610. Therefore, it is relatively easy to control the surface structure of gold plating by transfer.

In this way, the semiconductor mounting substrate 701 of the present invention is obtained, and the surface of the mounting portion has a barrier metal 702.
A land 703 having a concave cross-sectional structure is formed (FIG. 7 (m)).

Also, a plurality of wiring layers 80 with conductor posts C are provided.
1 (513 in FIG. 5), the conductive framed wiring layers 802 and 803 (514 and 515 in FIG. 5) manufactured by the same process as described above are aligned (FIG. 8 (k)) in the same process. The semiconductor mounting substrate 804 of the present invention is obtained by performing the stacking and the etching, and the land 805 having a concave cross-sectional structure whose surface is composed of the barrier metal 806 is formed in the mounting portion and the interlayer bonding portion of the inner layer. (Fig. 8 (m)).

It is most preferable to use solid phase-liquid phase bonding solder as the mounting material on the land, but it is more reliable to select a melting point lower than that of the bonding metal layer for reliability. It is even more suitable.

In the semiconductor mounting substrate of the present invention, after mounting the semiconductor element by solder ball connection or mounting the solder ball on the substrate mounting surface, and further, after the interlayer bonding, the land of the solder bonding portion is Since it has a larger joint area than the solder joint portion of the land, improvement in joint strength can be expected. Further, by transferring and forming the roughened shape on the concave cross-sectional structure, it is possible to obtain a larger bonding area and also to improve the bonding strength due to the anchor effect. In addition, since the fillet shape does not have a convex angular structure or a concave structure made of resin such as solder resist,
Almost no stress concentration due to mechanical stress can be expected to improve the reliability of the solder ball connection.

[0033]

EXAMPLES Hereinafter, the present invention will be described in more detail by way of examples, but the present invention is not limited thereto.

[Adjustment of Adhesive Varnish] 100 g of m, p-cresol novolac resin (manufactured by Nippon Kayaku Co., Ltd., PAS-1: trade name) and bisphenol F type epoxy resin (manufactured by Nippon Kayaku Co., Ltd., RE-404S: trade name) 140 g is dissolved in 60 g of cyclohexane, and 0.2 g of triphenylphosphine (manufactured by Kitako Chemical Co., Ltd.) as a curing catalyst.
Was added to prepare an adhesive varnish.

[Manufacturing Example 1 of Semiconductor Mounting Substrate] 70 μm thick electrolytic copper foil with roughened surface (Mitsui Mining & Smelting Co., Ltd.)
3EC-VLP: product name), a dry film resist (Tokyo Ohka Kogyo Co., Ltd., α430: product name) are laminated by atmospheric pressure roll lamination, and exposed using a chrome mask with a predetermined negative patterning. -Development was performed to form the plating resist A necessary for forming the conductor post A. Next, by using the electrolytic copper foil as a lead for electrolytic plating on the surface of the electrolytic copper foil where the opening of the plating resist A is exposed, the conductor post A is subjected to electrolytic copper plating under the conditions of a bath temperature of 25 ° C. and a cathode current density of 3 A / dm ^2. The plating thickness was 3 μm. Next, the plating resist A is peeled off using an aqueous sodium hydroxide solution, and then the plating resist B (AQ2558, trade name, manufactured by Asahi Kasei Co., Ltd.) is laminated by vacuum lamination to obtain a chromium mask having a predetermined negative patterning. It was exposed to light and developed to form a plating resist B necessary for forming the barrier metal and the conductor post B. Barrier metal bath temperature 65 ℃, cathode current density 0.5A /
Plating thickness is 1μm by electrolytic gold plating under the condition of dm ^2.
Was formed so that Furthermore, the conductor post B should have a bath temperature of 25
It was formed by electrolytic copper plating under the conditions of a temperature of 3 ° C. and a cathode current density of 3 A / dm ² to a plating thickness of 22 μm. Further, Sn is used as a metal layer for bonding on the surface of the obtained copper post.
/2.5Ag solder layer, bath temperature 22 ℃, cathode current density 2A
Plating thickness 5μ by electrolytic plating under the condition of / dm ²
It was formed so as to be m. Next, the plating resist B was peeled off using an aqueous sodium hydroxide solution, the above-mentioned adhesive varnish was applied to the exposed surface of the conductor post layer by screen printing, and dried at 80 ° C. for 20 minutes to form an adhesive layer. .
Next, read the positioning marks previously formed on the conductor post layer on which the connection layer is formed and on the layer to be connected of the flexible wiring board prepared separately from this, using the image recognition device, and align them. Then, after temporary pressure bonding at a temperature of 100 ° C., the copper post penetrates the adhesive and is solder-bonded to the portion to be joined of the flexible wiring board by heating and pressurizing at a temperature of 220 ° C. by a vacuum press. The conductor post layer and the layer to be connected adhered. Next, the electrolytic copper foil was removed using a ferric chloride-based etchant, and the semiconductor mounting substrate of the present invention could be obtained. FIG. 7 (n) shows a state (use example) in which the flip chip 704 is mounted and the solder balls 705 for external mounting are reflow mounted.

[Manufacturing Example 2 of Semiconductor Mounting Substrate] CFP-1121 (Sumitomo Bakelite Co., Ltd.) was used as the plating resist B.
Manufactured in the same manner as in Production Example 1 except that a permanent resist (which becomes a part of the insulating layer) was used.

[Manufacturing Example 3 of Semiconductor Mounting Substrate] A wiring layer is formed in the opening of the plating resist B after the formation of the barrier metal formed in the same process as in Manufacturing Example 1 with a bath temperature of 25 ° C. and a cathode current density of 3 A / After electrolytic copper plating under the condition of dm ² to form a plating thickness of 10 μm, the plating resist B is peeled off using an aqueous sodium hydroxide solution, and a polyimide resin is applied to the exposed wiring layer and the conductive frame surface. It was spread and applied to form an insulating resin layer. Next, UV-
YAG-Laser (Mitsubishi Electric Corp., ML605LD)
X: device name) was irradiated to form a via hole having a diameter of 40 μm. Next, the conductor post C was formed by electrolytic copper plating under the conditions of a bath temperature of 25 ° C. and a cathode current density of 3 A / dm ² so as to have a plating thickness of 15 μm. Further, a Sn / 2.5Ag solder layer as a metal layer for bonding is formed on the surface of the obtained copper post by electrolytic plating under the conditions of a bath temperature of 22 ° C. and a cathode current density of 2 A / dm ² to a plating thickness of 3 μm. So formed. Next, the above-mentioned adhesive varnish is applied to the surfaces of the conductor post C and the insulating resin layer by screen printing,
It dried at 20 degreeC for 20 minutes, and formed the adhesive layer. Next, the conductive frame was etched with a ferric chloride-based etchant, and a plurality of wiring layers with conductor posts C and wiring layer-containing conductive frames obtained in the same manner were laminated in the same manner as in Production Example 1. A semiconductor mounting substrate of the present invention was obtained. FIG. 8 (n) shows a state (use example) in which the flip chip 807 is mounted and the solder balls 808 for external mounting are reflow mounted.

[0038]

According to the present invention, a horizontal structure having no circuit unevenness on the mounting surface of a semiconductor element can be obtained, underfilling and defective filling of a sealing resin can be avoided, and mounting and inner layer bonding can be performed. Since the land is formed in a concave shape, the solder coating area increases and the anchor effect due to the roughened surface structure further increases the strength of the joint, so mounting reliability and joint reliability can be expected to improve. A substrate can be provided.
Further, since the cross-sectional shape of the joint does not have a rectangular convex structure or a concave structure formed by a solder resist, stress concentration due to thermal stress can be mitigated, and further mounting reliability can be expected.

[Brief description of drawings]

FIG. 1 is a cross-sectional view and an enlarged view showing an example of a rectangular convex structure of a land of a conventional technology.

FIG. 2 is a cross-sectional view and an enlarged view showing an example of a rectangular concave structure of a land according to a conventional technique.

FIG. 3 is a cross-sectional view showing an example of a method for manufacturing a semiconductor mounting substrate of the present invention.

FIG. 4 is a cross-sectional view (sequential to FIG. 3) showing an example of a method for manufacturing a semiconductor mounting substrate of the present invention.

FIG. 5 is a cross-sectional view showing an example of a method for manufacturing a semiconductor mounting substrate of the present invention.

FIG. 6 is a sectional view (continuation of FIG. 4) showing an example of a method for manufacturing a semiconductor mounting substrate of the present invention.

FIG. 7 is a cross-sectional view showing one example of a method for manufacturing a semiconductor mounting substrate of the present invention (continuation from FIG. 6) and a cross-sectional view showing an example of use obtained in an example.

FIG. 8 is a cross-sectional view showing one example of a method for manufacturing a semiconductor mounting substrate of the present invention (continuation from FIG. 5) and a cross-sectional view showing a use example obtained in the example.

[Explanation of symbols]

101 Corner-shaped convex land 201 Corner-shaped concave land 301, 501, 608 by solder resist Conductive frame 302, 502 Plating resist A 303, 503 Via 304, 504, 609 Conductor post A 305, 505 Plating resist B 306, 506 Opening 307 Micro uneven structure 308, 507, 610 Barrier metal 401, 604 Conductor post B 402, 511, 606 Bonding metal material layer 403, 404, 512, 605 Adhesive layer 405, 406, 601, 602 Conductor post layer 508 Plating wiring layer 509 Insulating resin layer 510 Conductor post C 513, 801 Conductor post C wiring layer 514, 515, 802, 803 Conductive frame wiring layer 603 Wiring board 607 Bonded portion 701, 804 Semiconductor mounting substrate 703, 805 Concave sectional structure Land 704, 807 Flip chip 705, 808 Solder ball

Claims (7)

[Claims] 1. A semiconductor-mounting substrate having a land for connecting a semiconductor element on a surface thereof, and the land having the same arrangement as an external connection terminal of the semiconductor element has a concave sectional structure. 2. The semiconductor mounting substrate according to claim 1, which has a land for connecting to the outside on the surface, and the land in the same arrangement as the connection terminal on the mounting substrate side has a concave sectional structure. 3. The semiconductor mounting substrate according to claim 1, further comprising a wiring layer having a multi-layered structure inside, and a land corresponding to an interlayer connection portion of the wiring layer has a concave sectional structure. 4. A conductive frame on which a conductor post is formed is bonded to a substrate to be bonded via a metal material for bonding and an adhesive layer, and the conductive frame is removed to form a land. Method for manufacturing a semiconductor mounting substrate. 5. A step of roughening the conductive frame,
A step of forming a plating resist on the surface of the conductive frame; a step of forming an opening in the plating resist by a photolithography method; and an electrolytic plating of the opening using the conductive frame as a lead for electrolytic plating. A step of forming the conductor post A by means of, and a step of peeling off the resist,
A step of roughening the exposed surfaces of the conductive frame and the conductor posts A, a step of forming a second plating resist (plating resist B), and a step of photolithographically forming the conductor posts A on the plating resist. For forming a barrier metal and a conductor post B by electrolytically plating the opening with the conductive frame as a lead for electrolytic plating, and for joining to the exposed surface of the conductor post B. The step of forming a metal material layer, the step of peeling off the plating resist, the step of forming an adhesive layer, and the step of forming a separately manufactured substrate having a layer to be connected with the layer to be connected via the adhesive layer. And a step of joining the joined portion of the substrate and the conductor post B via the joining metal material layer, and a step of removing the conductive frame and the conductor post A by etching. The method of manufacturing a semiconductor mounting substrate according to claim. 6. The second plating resist (plating resist B) is not removed and becomes a permanent resist, and in the step of forming an opening including the conductor post A in the plating resist, the opening is formed by a photolithography process or The method for manufacturing a semiconductor mounting substrate according to claim 5, which is formed by a laser process. 7. A step of roughening the conductive frame,
A step of forming a plating resist on the surface of the conductive frame; a step of forming an opening in the plating resist by a photolithography method; and an electrolytic plating of the opening using the conductive frame as a lead for electrolytic plating. A step of forming the conductor post A by means of, and a step of peeling off the resist,
A step of roughening the exposed surfaces of the conductive frame and the conductor posts A, a step of forming a second plating resist (plating resist B), and a step of photolithographically forming the conductor posts A on the plating resist. Forming a barrier metal and a wiring layer by electroplating the opening using the conductive frame as a lead for electroplating; removing the plating resist B; Forming an insulating resin layer on the surface of the wiring layer and the conductive frame, processing a via hole reaching the wiring layer on the surface of the insulating resin layer, and forming a conductor post C by filling the via hole. A step of forming a bonding metal material layer on the exposed surface of the conductor post C,
A step of forming an adhesive layer, a step of removing the conductive frame and the conductor posts A by etching, a plurality of wiring layers having conductor posts C obtained from the above steps (wiring layer with conductor posts C), and A step of joining the portion to be joined and the conductor post C via the adhesive metal layer and the conductive framed wiring layer having the conductor post A obtained in the step, and the conductive metal layer for joining; A method for manufacturing a semiconductor mounting substrate, comprising a step of removing the conductive frame and the conductor post A of the wiring layer with a conductive frame by etching.