JP2003296189A - Data writing method in cache system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To speed up the write-in processing of data to an actual memory through a cache memory. <P>SOLUTION: A CPU 10 performs a write-in address set and a data write-in number set in a writing area 21 within the actual memory 20, and successively, determines the cache part of the actual memory 30 which a cache memory 30 accesses as a cache hit area 31 based on a in-cache-0-clear instruction. The CPU 10 further repeatedly performs a write-in data set and a data write-in instruction until the write-in number is a value shown by the data write-in number set in write-in number determination. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data writing method in a cache system in which a CPU writes data to a real memory via a cache memory.

[0002]

2. Description of the Related Art As shown in FIG. 4, a system (cache system) 1 having a cache control mechanism includes a CPU 10 which is a central processing unit, a real memory 20 which is a large-capacity and low-speed storage medium, and this real memory. 20 and a cache memory 30 that can be accessed at a higher speed than the cache memory 20.
Data is written to the real memory 20 via 0.

The writing of data in such a cache system 1 is performed in the following procedure. CP
The U10 determines whether or not the contents of the real memory 20 are read into the cache memory 30 (that is, whether or not the address at which data is to be written hits the cache).

If the result of determination is that there is no cache hit (in the case of a cache miss hit), the CPU 1
0 sends a data write command to the cache memory 30. The cache memory 30 which has received this data write command transfers the contents of the address (contents of the write area 21) from the real memory 20 to the cache hit area 3
Take in 1 (fetch).

On the other hand, when the cache is hit (in the case of cache hit), the CPU 10 does not send a data write command to the cache memory 30. And CP
U10 writes and updates data in the cache memory 30. After that, when the cache is flushed, the written data is written to the real memory 20.

Further, the conventional memory access in the cache system 1 is performed in the procedure as shown in FIG. As shown in FIG.
The write address setting (step 100) and the data write number setting (step 101) in the write area 21 are performed.

Next, the CPU 10 judges the number of data writes (step 102). If the result of the judgment is that the number of data writes has not reached a predetermined value, then the write data set (step 103) and the data are written. A write command (step 104) is performed. After that, when the number of data writes reaches a predetermined value (step 102), this write is terminated.

By the way, a conventional technique for speeding up data writing in such a cache system is as follows.
Japanese Unexamined Patent Publication No. 3-296992 discloses a semiconductor memory device having a cache memory. In this semiconductor memory device with a built-in cache memory, an SRAM as a cache memory 30 is built in a DRAM chip which is an actual memory, and a part of the DRAM column address is used as the SRAM address so that the number of entries of a data block can be reduced. It achieves high-speed access by increasing the cache hit rate.

However, in the conventional semiconductor memory device with a built-in cache memory, since the DRAM which is the actual memory and the SRAM which is the cache memory are formed on the same chip, the SRAM for cache built in a certain chip is different. Could not be allocated to the chip. For this reason, for example, when the memory chip is accelerated only by the DRAM by the bank interleave structure or the like, the effect of the acceleration by the cache memory does not appear.

Therefore, another conventional technique that enables speeding up of data writing by the cache memory even when the memory chip is speeded up only by DRAM is disclosed in Japanese Patent Laid-Open No. 9-101917. Is disclosed as. In this cache memory control method, high-speed memory access is realized by making it possible to switch the address area targeted by the cache memory according to the type and configuration of the real memory.

[0011]

However, in the conventional cache memory control method, even when the CPU only wants to write data to the real memory via the cache memory (data write processing), the real memory Since the data is read from the cache memory to the cache memory (memory read), the data writing process is delayed.

Further, in the conventional cache memory control method, the content of the process for the memory area to which the data is written is selected on the basis of the information for distinguishing whether the cache is hit or not, and this is executed. By doing so, speeding up was realized, but if the information indicates a mishit, there was a problem that speeding up could not be realized without devising hardware.

The present invention has been made to solve the above problem, and speeds up the process of writing data to the real memory regardless of whether the cache hits in the memory area of the real memory. An object of the present invention is to provide a data writing method in a possible cache system.

[0014]

To achieve this object, a data writing method in a cache system according to claim 1 of the present invention is a cache in which a CPU writes data to a real memory via a cache memory. A method of writing data in a system,
This is a method in which after U determines the cache portion of the real memory to be accessed by the cache memory as a cache hit area, the data is written to the cache memory and the cache memory writes the data to the real memory by cache flush.

If such a method is used for writing data in the cache system, the CPU determines the cache portion of the real memory accessed by the cache memory as the cache hit area before writing the data in the cache memory. Even if it does not perform, the data can be written to the actual memory thereafter. Therefore, regardless of whether the cache hits in the memory area of the real memory,
It is possible to speed up the data writing process.

The data writing method in the cache system according to the second aspect is a method in which the CPU determines the cache hit area based on a 0 clear instruction in the cache. If the method of writing data in the cache system is such a method, the cache hit area is determined based on the in-cache 0 clear instruction, so that memory read is not required.
Data can be written to real memory. For this reason,
The time required for the data writing process can be shortened.

The data writing method in the cache system according to claim 3 is a method in which the CPU determines the cache hit area in another memory device instead of the cache memory. If such a method is used for writing data in the cache system, even if the cache hit area is determined in a memory device other than the cache memory, C
It is possible to speed up the data writing to the real memory by the PU.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. First, an embodiment of a cache system of the present invention will be described with reference to FIG. FIG. 1 is a block diagram showing the configuration of the cache system of this embodiment.

As shown in the figure, the cache system 1
Has a CPU 10, a real memory 20, and a cache memory 30. Here, CPU (Central Processing Unit)
Reference numeral 10 is a device that controls access to the cache memory 30.

The real memory 20 is a large-capacity and low-speed storage medium, and is a device for accessing data with the CPU 10. In this real memory 20, for example, D
RAM (Dynamic Random Access Memory) can be used. Further, as shown in FIG. 2, a writing area 21 is secured in the real memory 20. The writing area 21 is an area of the actual memory 20 for data access.

The cache memory 30 is a storage medium that can be accessed at a higher speed than the real memory 20, and is a CPU 1
Reference numeral 0 is a cache device when accessing data with the real memory 20. SRAM (static random access memory) can be used as the cache memory 30, for example.

A cache hit area 31 is secured in the cache memory 30, as shown in FIG. The cache hit area 31 is the writing area 2
This is a cache area in the cache memory 30 when a cache hit occurs at 1.

Next, the procedure of the data writing method in the cache system of this embodiment will be described with reference to FIGS. When data is written from the CPU 10 to the real memory 20, in the CPU 10, the cache portion of the real memory 20 accessed by the cache memory 30 is determined as the cache hit area 31. Then, from the CPU 10 to the cache memory 30,
Data is written and updated.

After that, when the cache is flushed,
The written data is written to the real memory 20. In the data writing method in the cache system according to the present embodiment as described above, the CPU 10 causes the cache hit area 31 to be irrespective of whether or not the contents of the real memory 20 are hit in the cache memory 30.
To confirm.

Next, the memory access operation in the cache system of this embodiment will be described with reference to FIG. The figure is a flowchart showing the operation of the cache system of the present embodiment. As shown in the figure,
In the CPU 10, the write address set in the write area 21 in the real memory 20 (step 10)
And the number of data writes (step 11) is performed.

Next, the CPU 10 determines whether or not the number of data writes has reached a predetermined value (step 12). If the result of determination is that the number of data writes has not reached the predetermined value, the CPU 10 subsequently outputs an in-cache 0 clear instruction (step 13).
Based on this in-cache 0 clear instruction, in the cache memory 30, the cache portion of the real memory 20 accessed by the cache memory 30 is determined as the cache hit area 31.

Then, in the CPU 10, a write data set (step 14) and a data write command (step 15) are performed. After that, when the number of data writes reaches a predetermined value (step 12), this data write process ends.

When the data writing process in the cache system is performed by such a method, when writing data to the real memory, the cache portion of the real memory accessed by the cache memory is determined as the cache hit area based on the in-cache 0 clear instruction. Therefore, there is no need to perform the conventional data fetching (fetching (fetching) data from the real memory to the cache memory). That is, since the cache hit area is determined regardless of whether the write area of the real memory has a cache hit or not, it is possible to speed up the data writing process to the real memory.

Next, the total operation time required for the data writing process in the conventional cache system and the present invention will be described. In the configuration of the cache system 1, the CPU 1 is used as a condition for calculating the total operation time required for data writing processing in the cache system.
0 is the operating clock of 100 MHz, the cache memory 30 is the CPU 10 and the same clock, and the real memory 20 is 7
Each has an access time of 0 ns.

In addition, one data write is 100,
000000/32 = 3,125,000 times (one cache line is 32 bytes), and the number of data to write is 100 MB (= 100,000,000b).
yte). Under these conditions, first, the total operation time required for the data writing process in the conventional cache system is calculated as follows.

(I) Total operation time required for data write processing in the conventional cache system (I-1) Program operation time in conventional memory access 5 [cycles] × 10 [ns] (100 [MHz]) ×
3,125,000 = 156.250 [ms]

(I-2) Read memory access time 70 [ns] × 100 [MB] = 7 [s]

(I-3) Write memory access time 70 [ns] × 100 [MB] = 7 [s]

(I-4) Total operation time required for data write processing in the conventional cache system 156.250 [ms] +7 [s] +7 [s] = 14.
15625 [s] 14 [s]

Next, the total operation time required for the data writing process in the cache system of the present invention is calculated as follows. (II) Total operation time required for data write processing in the cache system of the present invention (II-1) Program operation time in memory access of the present invention 6 [cycles] × 10 [ns] (100 [MHz]) ×
3,125,000 = 187.500 [ms]

(II-2) Read memory access time 70 [ns] × 0 [MB] = 0 [s]

(II-3) Write memory access time 70 [ns] × 100 [MB] = 7 [s]

(II-4) Total operation time required for data write processing in the cache system of the present invention 187.500 [ms] +0 [s] +7 [s] = 7.1
875 [s] 7 [s]

As a result of these calculations, the total operation time in the conventional cache system is about 14 [s], whereas the total operation time in the cache system of the present invention is about 7 [s]. That is, in the cache system of the present invention, memory access can be performed in about half the operation time as compared with the data write processing in the conventional cache system.

In the data writing process in the cache system of this embodiment, the cache hit area is determined on the cache device, but the cache device is not limited to the cache device. For example, other than the cache device. Memory device (hereinafter simply referred to as a memory device).

In this case, when the CPU 10 writes data to the real memory 20, the access portion of the real memory 20 accessed by the memory device is determined as a hit area on the memory device. Therefore, it is possible to write data to the real memory 20 regardless of whether the contents of the real memory 20 hit the memory device. Therefore, also in this case, the speed of the data writing process can be increased.

[0042]

As described above, according to the present invention, the CPU
When writing data from the memory to the real memory, the CPU
However, by determining the cache portion of the real memory to be accessed by the cache memory as the cache hit area, the cache memory does not need to fetch the data from the real memory, so that the data writing process can be speeded up.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a cache system of the present invention.

FIG. 2 is a block diagram showing an area configuration of a cache memory and a real memory in the cache system of the present invention.

FIG. 3 is a flowchart showing the operation of the cache system of the present invention.

FIG. 4 is a block diagram showing a configuration of a conventional cache system.

FIG. 5 is a flowchart showing the operation of a conventional cache system.

[Explanation of symbols]

1 cache system 10 CPU 20 real memory 21 Writing area 30 cache memory 31 cash hit area

Claims (3)

[Claims] 1. A data writing method in a cache system in which a CPU writes data to a real memory via a cache memory, wherein the CPU caches a cache portion of the real memory accessed by the cache memory. A method for writing data in a cache system, characterized in that the data is written to the cache memory after being determined as a hit area, and the cache memory writes the data to the real memory by cache flush. 2. The data writing method in a cache system according to claim 1, wherein the CPU determines the cache hit area based on an in-cache 0 clear instruction. 3. The data writing method according to claim 1, wherein the CPU determines the cache hit area in another memory device instead of the cache memory.