JP2003289108A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide the layout method of a semiconductor integrated circuit, configured by improving circuit characteristics by providing regularity in the hierarchical structure of each wiring. <P>SOLUTION: Emitter follower circuits 22 and 23 are disposed symmetric with respect to the center line of a differential amplifier 1. Thus, since eliminate an area where the wiring crosses is eliminated, wiring can be connected in a circuit block through one layer metal wiring 3 to a ground line Vss. Thus, it is possible to solve the problem of cross-talks due to crossing of the mutual wiring. Also, the length of wiring 6 and 7 between the differential amplifier 1 and the emitter follower circuits 22 and 23 can be made equal. Then, signal wirings between the circuit blocks are configured of two-layer metal wiring 4, and three-layer metal wiring 5 is assigned as a Vcc power line. Thus. realize a higher precision semiconductor integrated circuit can be realized. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more specifically, to a circuit configuration technique for improving circuit characteristics by giving a regularity to a hierarchical structure of each wiring in a hierarchical structure design including multilayer wiring. It is about.

[0002]

2. Description of the Related Art A circuit configuration of a conventional semiconductor integrated circuit will be described below with reference to the drawings. A differential amplifier frequently used in a bipolar linear integrated circuit will be described as an example.

As shown in FIG. 6A, in the differential amplifier 11, the emitters of a first transistor Q11 and a second transistor Q12 are connected in common to a constant current transistor Q13, and each of the transistors Q11, Q12 is connected. The basic structure is such that each collector is connected to the power supply potential Vcc through load resistors R11 and R12.

Transistors Q11 and Q12 which are input terminals
By amplifying the difference between the signals (Vin1, Vin2) applied between the bases of the transistors and extracting the output signals (Vout1, Vout2) from the collectors of the transistors Q11, Q12, the fluctuation factors of the respective transistors are canceled out. It is possible not to affect the output.

In such a differential amplifier 11, when the balance of each element is lost, the midpoint potential of the output shifts and desired circuit characteristics cannot be obtained. Therefore, the transistors Q11 and Q12 are not provided.
Care was taken to obtain the pairing of the characteristics of 1 and the pairing of the characteristics of the load resistors R11 and R12. Here, the pair property means that the characteristics of the elements forming the pair have the same property.

[0006]

However, in the above circuit configuration, sufficient attention is paid so that the paired characteristics of the pair of transistors Q11 and Q12 and the paired characteristics of the pair of load resistors R11 and R12 are matched. Despite being
When laying out a circuit pattern, for example, from left to right (or right to left) on the paper, according to the circuit design drawing
Along with this, when the respective semiconductor elements are sequentially arranged to form a desired circuit, there are the following problems.

That is, as shown in the circuit configuration diagram of FIG. 6A, the emitter follower circuits 42 and 43 connected to the pair of differential output terminals of the differential amplifier 11 are connected to the differential amplifier 1.
They were concentrated on one side (right side) of the drawing with respect to the center line of 1. Here, the emitter follower circuit 42 includes a transistor Q14, a constant current transistor Q16, and an emitter resistor R13 of the constant current transistor Q16.
Further, the emitter follower circuit 43 includes a transistor Q1.
5, constant current transistor Q17, constant current transistor Q
It is composed of 17 emitter resistors R14.

As a result, the pairing of the semiconductor integrated circuit composed of the differential amplifier 11 may be broken, and when connecting the circuit blocks to each other, an impedance offset may occur and the circuit characteristics may be deteriorated.

Further, as described above, the differential amplifier 1
1, an emitter follower circuit 42 connected to each output stage
Since 43 are concentrated on one side (right side) of the drawing with respect to the center position of the differential amplifier 11, as shown in FIG. 6B, for example, from the collector of the transistor Q11 to the transistor of the emitter follower circuit 42. The wiring 12 for inputting to the base of Q14 intersects with the wiring 13 for connecting the resistor R12 and the collector of the transistor Q12, and similarly the input from the collector of the transistor Q12 to the base of the transistor Q15 of the emitter follower circuit 43. The wiring 14 for making the emitter follower circuit 42
The wiring 15 for connecting the emitter of the transistor Q14 and the collector of the transistor Q16 intersects, and the wirings 12 and 14 and the wirings 13 and 15 need to be formed in different layers (above-mentioned). In the configuration, the wirings 13 and 15 are composed of one-layer wiring, and the wirings 12 and 14 are composed of two-layer wiring. When the wiring intersects in this way, high frequency characteristics deteriorate due to signal crosstalk. Moreover, since the wiring length is different from that of the wirings 12 and 14, the pairing property is lost. Therefore, when interconnecting the circuit blocks, the desired circuit characteristics may not be obtained due to the influence of the offset due to the impedance.

As described above, in the conventional integrated circuit, since each wiring forming the hierarchical structure does not have regularity (wiring purpose, pairing) for each wiring of each layer,
If it is expected that there will be an area where the wires intersect, each wire will be easily configured in a different layer.
It was a factor causing deterioration of circuit characteristics.

Further, in a semiconductor integrated circuit having a hierarchical structure, for the purpose of automatic designing, for example, a plurality of circuit blocks made of semiconductor elements are provided, and interconnection wiring connection is made within each circuit block and between each circuit block. When performing the wiring, for example, one layer of metal wiring is used for the horizontal wiring, two layers of metal wiring are used for the vertical wiring, and which layer wiring is to be allocated based on each wiring direction. Layout methods for semiconductor integrated circuits have also been proposed.

However, such wiring conditions (one-layer metal wiring is used for the horizontal wiring, and two wirings are used for the vertical wiring).
If the wiring is performed based on (for example, using a metal wiring of a layer), wiring that is originally connectable by one wiring will be connected by using a plurality of wiring layers, and the wiring structure will be complicated.

[0013]

Therefore, the present invention has a circuit block including a plurality of semiconductor elements and at least multilayer wiring for connection between the semiconductor elements, wherein metal wiring of each layer of the multilayer wiring is It is characterized by being assigned to each wiring use. As a result, it is possible to prevent such multilayer wiring from becoming complicated, and it is possible to improve the circuit characteristics.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of a semiconductor integrated circuit of the present invention will be described with reference to the drawings. Below, the differential amplifier 1 which is frequently used in the bipolar linear integrated circuit will be described as an example.

In FIG. 1, reference numeral 1 is a circuit block (a differential amplifier in this embodiment) composed of bipolar transistors, and a pair of emitter follower circuits 22 and 23 are connected to a pair of differential output terminals thereof. Here, the emitter follower circuits 22 and 23 are arranged so as to be line symmetrical with respect to the center line of the circuit block.

As a result, the emitter follower circuits 42 and 43 connected to the pair of differential output terminals of the differential amplifier 11 as in the conventional case (shown in FIG. 6) are asymmetric with respect to the center line of the differential amplifier. The pairing property is improved as compared with the configuration arranged at the position. Therefore, when the present invention is applied to a circuit configuration in which the signal is desired to have a pair property such as a differential amplifier, the characteristics of the semiconductor integrated circuit can be improved. In addition to the differential amplifier, there may be a circuit such as a filter, which is applicable to a semiconductor integrated circuit having a circuit configuration in which a pair of emitter follower circuits are connected to a pair of outputs of the circuit. is there.

As shown in the circuit configuration diagram of FIG. 1, the differential amplifier 1 has a constant current transistor Q3 in which the emitters of the first transistor Q1 and the second transistor Q2 are common.
And the collectors of the transistors Q1 and Q2 are connected to the power supply potential Vcc through load resistors R1 and R2, respectively.

Further, each transistor Q which is an input terminal
By amplifying the difference between the signals (Vin1, Vin2) applied between the bases of 1 and Q2 and extracting the output signals (Vout1, Vout2) from the collectors of the transistors Q1 and Q2,
It is possible to cancel the fluctuation factor of each transistor so as not to affect its output.

The respective emitter follower circuits 22 and 23 connected to the output of the differential amplifier 1 are arranged in line symmetrical positions with respect to the center line of the differential amplifier 1. Here, the emitter follower circuit 22 includes a transistor Q4 whose collector is connected to the base, a constant current transistor Q6 which supplies a constant current to the transistor Q4, and an emitter resistor R3 of the constant current transistor Q6. There is. Similarly, the emitter follower circuit 23 includes a transistor Q5 in which the collector of the transistor Q2 is connected to the base, a constant current transistor Q7 that supplies a constant current to the transistor Q5, and an emitter resistor R4 of the constant current transistor Q7. ing.

As described above, according to the present invention, the emitter follower circuits 22 and 23 are arranged at positions symmetrical with respect to the center line of the differential amplifier 1, respectively. Since there is no area where the wirings intersect with each other, the wirings in the circuit block and the ground line Vss can be connected by the one-layer metal wiring 3 as shown in the layout diagram of FIG. As a result, the problem of crosstalk due to the intersection of wirings can be solved. Also a differential amplifier 1
The lengths of the wires 6 and 7 between the emitter follower circuit and the emitter follower circuit can be made equal. Then, the signal wiring between the circuit blocks is composed of the two-layer metal wiring 4, and the three-layer metal wiring 5 can be assigned as the Vcc power supply line. Therefore, in constructing the layout method of the semiconductor integrated circuit having such a hierarchical structure, so,
A more highly accurate semiconductor integrated circuit can be realized.

Next, a second embodiment of the present invention will be described with reference to the drawings.

Here, in the second embodiment, an embodiment in which the present invention is applied to a Gilbert cell called a so-called double differential amplifier will be described.

FIG. 3 and FIG. 4 are a circuit configuration diagram and a layout diagram of the double differential amplifier 2. In this embodiment, the double differential amplifier 2 is composed of two stages of double differential amplifiers 2. That is, as shown in FIG. 3, the output signal (Vou
t1, Vout2) is the input signal of the second stage double differential amplifier 2 (the base of the input stage transistor Q6A is Vi
n3, Vin4) at the base of the input-stage transistor Q6B, both of which are continuously formed, and output signals (Vout3, Vout4) are output from the second-stage double differential amplifier 2.
In addition, in order to avoid duplicated description, the same components are denoted by the same reference numerals, and the description thereof will be omitted.

In FIG. 3, the emitters of the first transistor Q1A and the second transistor Q2A are commonly connected to the collector of the input stage transistor Q6A, and the emitters of the third transistor Q1B and the fourth transistor Q2B are commonly used. The collector of the input stage transistor Q6B is connected,
The input stage transistors Q6A and Q6B have the same emitter connected to the constant current transistor Q3, and the collectors of the transistors Q2A and Q1B are connected to the power supply potential Vcc through the load resistors R1A and R2A, respectively. I am trying. The collectors of the transistors Q1A, Q2A, Q1B and Q2B may be connected to the power supply potential Vcc via load resistors.

Input signal (Vin1, Vin2) from the input terminal
By amplifying the difference between the signals applied between the bases of the respective transistors Q6A and Q6B, and extracting the output signals (Vout1 and Vout2) from the collectors of the respective transistors Q2A and Q1B through the transistors Q4A and Q5A. It is possible to cancel out the fluctuation factors of so that the output is not affected.

The emitter follower circuits 31 and 32 connected to the differential output terminals are respectively arranged at positions symmetrical with respect to the center line (not shown) of the double differential amplifier 2. The semiconductor integrated circuit of the present invention is configured. Here, the emitter follower circuit 31 is composed of a transistor Q4A in which the collector of the transistor Q2A is connected to the base, a constant current transistor Q7 which supplies a constant current to the transistor Q4A, and an emitter resistor R9 of the constant current transistor Q7. The emitter follower circuit 32 is similarly composed of a transistor Q5A whose base is connected to the collector of the transistor Q1B, a constant current transistor Q8 which supplies a constant current to the transistor Q5A, and an emitter resistor R10 of the constant current transistor Q8.

In this way, the double differential amplifier 2 having the above structure
Then, each of the emitter follower circuits 31, 32 connected to the plurality of output stages is arranged at a position symmetrical with respect to the center line.
By arranging each of them, the pairing property of the circuit configuration is improved. Therefore, when it is applied to a circuit configuration where the signal is desired to have the pairing property, the characteristics of the semiconductor integrated circuit are improved. Can be achieved.

The resistors R5, R6, R7, and R8 are for trimming, and the trimming resistance element is also the differential amplifier 2.
It is placed at a position symmetrical with respect to the center line of. Thereby, even when using the trimming resistance element,
Since the pairing property can be maintained, the circuit characteristics are not deteriorated.

As described above, in the present invention, the emitter follower circuits 31 and 32 connected to the differential output terminals are arranged at positions symmetrical with respect to the center line of the double differential amplifier 2, respectively. As shown in the layout diagram of FIG. 4, the wiring in the circuit block can be connected by the one-layer metal wiring 3. Further, the signal wiring between the circuit blocks is composed of the two-layer metal wiring 4, and the three-layer metal wiring 5 can be assigned as the Vcc power supply line. In constructing the layout method of the semiconductor integrated circuit having a hierarchical structure, A highly accurate semiconductor integrated circuit can be realized.

In the first and second embodiments, the circuit blocks are interconnected so as to be bilaterally symmetrical,
The wiring 13 located in the lower layer as in the conventional case (shown in FIG. 6),
In order to avoid overlapping with the wiring 15, the wirings 12 and 14 are formed on the upper layers of the wirings 13 and 15, and
It is possible to improve the circuit characteristics of the semiconductor integrated circuit by avoiding the configuration in which the wiring lengths of 14 are different and forming these wirings in the same layer (the first-layer metal wiring 3).

However, the present invention is not limited to this, and the following lower layer wiring and upper layer wiring may coexist well. The layout diagram of the Gilbert cell shown in FIG. 5 is different from the layout diagram of the Gilbert cell shown in FIG.
The difference is that two-layer metal wirings 4a and 4b are used as wirings for connecting the collector of Q1B and the bases of transistors Q4A and Q5B.

That is, as shown in FIG. 5, the above-mentioned structure (collectors of transistors Q2A and Q1B and transistors Q4A and Q5B) is used.
Between the bases), the two-layer metal wirings 4a, 4b
However, even in the case of using the two-layer metal wirings 4a, 4 which are in contact with the lower-layer wiring (the first-layer metal wiring 3 in this embodiment) via the pair of through holes TH,
Since b is symmetrically configured with the same wiring length, it is possible to suppress the occurrence of offset due to impedance between wirings as in the conventional case, and improve the circuit characteristics of the semiconductor integrated circuit.

In addition, in each embodiment of the present invention, a semiconductor device including an active element such as a bipolar device or a MOS device, a Gilbert Cel such as a Mixer or an AGC circuit, etc.
l-structured semiconductor devices that require symmetry, semiconductor devices used in high-frequency regions, semiconductor devices used when using SiGe Process, satellite TV, terrestrial TV, cable TV, semiconductor devices for wireless LAN Also included are those used for etc.

[0034]

According to the present invention, the wiring for each layer has a regularity (wiring usage, pairing property, etc.), so that the conventional circuit blocks can be interconnected. In addition, it is possible to suppress the occurrence of offset due to impedance and improve the circuit characteristics of the semiconductor integrated circuit.

Further, since the power supply line is composed of the uppermost metal wiring which is wider than the other wirings, the impedance can be lowered and a more accurate semiconductor integrated circuit can be realized.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram showing a semiconductor integrated circuit according to a first embodiment of the present invention.

FIG. 2 is a layout diagram showing a semiconductor integrated circuit according to the first embodiment of the present invention.

FIG. 3 is a circuit configuration diagram showing a semiconductor integrated circuit according to a second embodiment of the present invention.

FIG. 4 is a layout diagram showing a semiconductor integrated circuit according to a second embodiment of the present invention.

FIG. 5 is a layout diagram showing a semiconductor integrated circuit according to a third embodiment of the present invention.

FIG. 6 is a diagram showing a conventional semiconductor integrated circuit.

[Explanation of symbols]

1 differential amplifier 2 double differential amplifier 3 1 layer metal wiring 4 2-layer metal wiring 5 3 layer metal wiring

Claims (6)

[Claims] 1. A circuit block including a plurality of semiconductor elements, and at least multi-layer wiring for connection between the semiconductor elements, wherein metal wiring of each layer of the multi-layer wiring is assigned to each wiring use. And a semiconductor integrated circuit. 2. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit has a plurality of circuit blocks, and these circuit blocks are connected to each other by a metal wiring of one of the layers of the multilayer wiring. 3. The multi-layered wiring is at least three-layered wiring, and among the three-layered wiring, the first layer is assigned to the ground line and the wiring in the circuit block, and the second layer is assigned to the wiring between the circuit blocks. The semiconductor integrated circuit according to claim 2, wherein the third layer is assigned to a power supply line. 4. The semiconductor integrated circuit according to claim 1, wherein a plurality of semiconductor elements of the circuit block are arranged in line symmetry with respect to a center line of the circuit block. 5. The circuit block includes a pair of differential transistors and a pair of emitter follower circuits to which differential amplified outputs of the differential transistors are supplied through a pair of metal wirings. 2. The semiconductor integrated circuit according to claim 1, wherein the wiring and the pair of emitter follower circuits are arranged in line symmetry. 6. The semiconductor integrated circuit according to claim 5, wherein the pair of differential transistors and the pair of emitter follower circuits are composed of bipolar transistors.