JP2003224438A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain desired circuit characteristics by realizing a layout arrangement, in which symmetry is taken into consideration for each semiconductor device constituting a circuit block. <P>SOLUTION: Emitter follower circuits 23 and 24 are arranged near a differential amplifier 21, and each emitter follower circuit is arranged at a position of line symmetry for the central line of the differential amplifier 21. Bipolar transistors Q<SB>24</SB>and Q<SB>25</SB>, constituting the emitter follower circuits 23 and 24, are arranged near bipolar transistors Q<SB>21</SB>and Q<SB>22</SB>constituting the differential amplifier 21, and the bipolar transistors Q<SB>24</SB>and Q<SB>25</SB>are arranged at direction of 90 degrees different from each other. According to this arrangement, crossing is eliminating among wiring inputted from the differential amplifier 21 to the emitter follower circuits 23 and 24, and symmetry for a differential amplifier 1 including the emitter follower circuits 23 and 24 is improved to enhance circuit characteristics, because of employing equal wiring length. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a technique for improving circuit characteristics by ensuring symmetry.

[0002]

2. Description of the Related Art The structure of a conventional semiconductor integrated circuit will be described below by taking a differential amplifier frequently used in a bipolar linear integrated circuit as an example.

As shown in FIG. 8, the differential amplifier 11
Is a first transistor Q11 and a second transistor Q12.
The basic structure is such that the emitter of is connected to the constant current transistor Q13 in common, and the collectors of the transistors Q11 and Q12 are connected to the power supply potential Vcc through the load resistors R11 and R12, respectively.

Transistors Q11 and Q12 which are input terminals
By amplifying the difference between the signals (Vin1, Vin2) applied between the bases of the transistors and extracting the output signals (Vout1, Vout2) from the collectors of the transistors Q11, Q12, the fluctuation factors of the respective transistors are canceled out. It is possible not to affect the output.

In such a differential amplifier 11, when the balance of each element is lost, the midpoint potential of the output shifts and desired circuit characteristics cannot be obtained. Therefore, the transistors Q11 and Q12 are not provided.
Care was taken to obtain the pairing of the characteristics of 1 and the pairing of the characteristics of the load resistors R11 and R12. Here, the pair property means that the characteristics of the elements forming the pair have the same property.

[0006]

However, in the above circuit configuration, sufficient attention is paid so that the paired characteristics of the transistors Q11 and Q12 and the paired characteristics of the load resistors R11 and R12 are obtained. Nevertheless, when laying out the circuit pattern, according to the circuit design drawing, for example, from left to right (or from right to left) on the paper,
The following problems have been encountered when arranging the semiconductor elements in order to form a desired circuit.

That is, as shown in the circuit configuration diagram of FIG. 8, a pair of emitter follower circuits 12 and 13 connected to a pair of differential output terminals of the differential amplifier 11 are connected to the differential amplifier 1.
They were concentrated on the right side of the center line of 1.

The emitter follower circuit 12 is composed of a transistor Q14, a constant current transistor Q16, and an emitter resistor R13 of the constant current transistor Q16. Further, the emitter follower circuit 13 includes a transistor Q
15, a constant current transistor Q17, and an emitter resistor R14 of the constant current transistor Q17.

Therefore, there is a problem that the symmetry of the semiconductor integrated circuit including the differential amplifier 11 is broken and desired circuit characteristics cannot be obtained. For example, the wiring length of the wiring input from the differential amplifier 11 to the base of the transistor Q14 of the emitter follower circuit 12 is different from the wiring length of the wiring input from the differential amplifier 11 to the base of the transistor Q15 of the emitter follower circuit 13, In some cases, the desired circuit characteristics could not be obtained due to the influence of the offset due to.

The wiring from the differential amplifier 11 to the emitter follower circuit 12 intersects the collector node of the transistor Q12 of the differential amplifier 11, and the wiring from the differential amplifier 11 to the emitter follower circuit 13 is an emitter follower. The emitter of the transistor Q14 of the circuit 12
It intersects with the node, which causes deterioration of high frequency characteristics.

[0011]

Therefore, a semiconductor integrated circuit of the present invention has a circuit block composed of a plurality of semiconductor elements and a pair of emitter follower circuits connected to the circuit block. The emitter follower circuit is characterized in that it is arranged in the vicinity of the circuit block and in line symmetry with respect to its center line.

As a result, there is no intersection between the wirings input from the output terminal of the circuit block to the emitter follower circuit, and the wiring lengths can be made equal, so that the symmetry of the circuit block including the emitter follower circuit is improved, The circuit characteristics can be improved.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit configuration diagram of the differential amplifier 21, and FIG. 2 is a layout diagram thereof. Although FIG. 1 is a circuit diagram, it also shows the physical arrangement of transistors and wirings.

As shown in FIG. 1, in the differential amplifier 21, the emitters of the first transistor Q21 and the second transistor Q22 are commonly connected to the constant current transistor Q23, and the collectors of the transistors Q21 and Q22 are connected to each other. Each of them is configured to be connected to the power supply potential Vcc through load resistors R21 and R22.

Transistors Q21 and Q22 which are input terminals
By amplifying the difference between the signals (Vin1, Vin2) applied between the bases of the transistors and extracting the output signals (Vout1, Vout2) from the collectors of the transistors Q21, Q22, the fluctuation factors of the respective transistors are canceled out. It is possible not to affect the output.

Then, the emitter follower circuits 22 and 23
Are connected to the collectors of the transistors Q21 and Q22, respectively. Here, the emitter follower circuit 22 includes a transistor Q24, a constant current transistor Q26, and an emitter resistor R23 of the constant current transistor Q26. Further, the emitter follower circuit 23 includes a transistor Q
25, a constant current transistor Q27, and an emitter resistor R24 of the constant current transistor Q27.

The emitter follower circuits 22 and 23
Are arranged in the vicinity of the differential amplifier 21 and are respectively arranged at positions symmetrical with respect to the center line of the differential amplifier 21.

More specifically, as shown in FIG. 2, the bipolar transistors Q24 and Q25 forming the emitter follower circuits 22 and 23 are arranged in the vicinity of the bipolar transistors Q21 and Q22 forming the differential amplifier 21, and The emitter-collector directions are arranged so as to differ by 90 degrees. Note that C, B, and E in FIG. 2 mean the collector, base, and emitter of the bipolar transistor, respectively.

By adopting such a circuit configuration, the crossings between the wirings input from the differential amplifier 21 to the emitter follower circuits 22 and 23 are eliminated, and the wiring lengths can be shortened and equalized. The symmetry of the differential amplifier 21 including 22 and 23 is improved, and the circuit characteristics can be improved.

Next, a second embodiment of the present invention will be described with reference to the drawings.

The second embodiment is an application of the present invention to a Gilbert cell called a so-called double differential amplifier.

FIG. 3 is a circuit configuration diagram of the double differential amplifier 2, and FIG. 4 is a layout diagram thereof. Note that FIG.
Although it is a circuit diagram, it also shows the physical arrangement of transistors and wiring. Further, C, B, and E in FIG. 4 are the collector, base, and emitter of the bipolar transistor, respectively, and resistors R1A and R2A for convenience.
Etc. are not shown.

The input stage transistor Q has the emitters of the first transistor Q1A and the second transistor Q2A in common.
The collector of 6A is connected, the emitters of the third transistor Q1B and the fourth transistor Q2B are made common, and the collectors of the input stage transistors Q6B are connected, and the emitters of the respective input stage transistors Q6A and Q6B are made common to make a constant current. The basic structure is such that it is connected to the transistor Q3 and the collectors of the transistors Q2A and Q1B are connected to the power supply potential Vcc through the load resistors R1A and R2A, respectively. The collectors of the transistors Q1A, Q2A, Q1B, and Q2B may be connected to the power supply potential Vcc via load resistors.

Transistors Q6A and Q6B which are input terminals
The difference between the signals (Vin1, Vin2) applied between the bases of the transistors is amplified, and the output signals from the collectors of the respective transistors Q2A, Q1B are transmitted via the emitter follower circuits 40, 41 (V
out1 and Vout2), it is possible to cancel the fluctuation factors of each transistor and prevent the output from being affected. The transistors Q7 and Q8 are
These are constant current transistors for the emitter follower circuits 40 and 41, respectively, and R5 and R6 are resistors.

Then, the emitter follower circuits 40 and 41
Are arranged in the vicinity of the double differential amplifier 2 and are arranged in line symmetry with respect to the center line (not shown) of the double differential amplifier 2.

More specifically, as shown in FIG. 4, the transistors Q4A, Q7, Q5A, Q8 constituting the emitter follower circuits 40, 41 are arranged in the vicinity of the double differential amplifier 2 and differ by 90 degrees. It is arranged in the direction.

As a result, it becomes possible to improve the symmetry of the circuit configuration, and when the present invention is applied to a circuit configuration in which the signal is desired to have symmetry like the double differential amplifier 2, a semiconductor is applied. The characteristics of the integrated circuit can be improved.

In particular, each emitter follower circuit 40, 41
By centrally arranging each of them in a line-symmetrical position in the vicinity of the double differential amplifier 2, the routing distance of the wiring from the double differential amplifier 2 to each of the emitter follower circuits 40 and 41 is shortened. Since it is possible to suppress an increase in the rate of occurrence of variations in signal transmission due to an increase in the wiring length of the circuit and to reduce the impedance, a circuit configuration in which the signal is desired to have symmetry like the double differential amplifier 2 concerned. When the present invention is applied to, the characteristics of the semiconductor integrated circuit can be improved.

Then, as shown in FIGS. 3 and 4, the constant current transistor Q of each of the emitter follower circuits 40 and 41.
Similarly, by arranging 7 and Q8 centrally in the vicinity of the differential amplifier 2, the symmetry of the semiconductor elements is further improved and the circuit characteristics can be improved.

The trimming resistors R7, R8, capacitors (not shown), etc. are arranged at positions symmetrical with respect to the center line of the double differential amplifier 2 so that the trimming resistance element and Since the symmetry can be maintained even when the capacitive element is used, the circuit characteristics are not deteriorated.

Next, a third embodiment of the present invention will be described with reference to the drawings.

As shown in FIG. 5, the differential amplifier 1 has a first
Of the transistors Q1 and Q2 are connected in common to the constant current transistor Q3, and the collectors of the transistors Q1 and Q2 are connected to load resistors R1 and R2, respectively.
Is connected to the power supply potential Vcc via. Note that FIG.
Although it is a circuit diagram, it also shows the physical arrangement of transistors and wiring.

In addition, each transistor Q which is an input terminal
Amplification of the difference between the signals (Vin1, Vin2) applied between the bases of 1 and Q2 and taking out the output signals (Vout1, Vout2) from the collectors of the transistors Q1 and Q2 causes variation factors of the transistors Q1 and Q2. Can be canceled so that the output is not affected.

A pair of emitter follower circuits 30 and 31 connected to the collectors of the transistors Q1 and Q2, which are a pair of differential output terminals of the differential amplifier 1, are provided in the vicinity of the differential amplifier 1 and have a difference. They are arranged at positions symmetrical with respect to the center line of the dynamic amplifier 1.

In addition, each emitter follower circuit 30, 31
The bipolar transistors Q4 and Q5 forming the differential amplifier are arranged in the same direction as the bipolar transistors Q1 and Q2 forming the differential amplifier 1. That is, the bipolar transistor Q4, which constitutes the emitter follower circuits 30 and 31,
The arrangement direction of the emitter, base, and collector of Q5 is the vertical direction of the paper surface, and the arrangement direction of the emitters, bases, and collectors of the bipolar transistors Q1 and Q2 forming the differential amplifier 1 is also the vertical direction of the paper surface.

In addition, each emitter follower circuit 30, 31
Of the bipolar transistors Q4 and Q5 forming the differential amplifier 1 have a different order arrangement from the emitter, base and collector of the bipolar transistors Q1 and Q2 forming the differential amplifier 1 (the vertical arrangement order is 180 degrees). It is placed in the inverted state). For example,
The bipolar transistor Q4 is arranged in the order of the emitter, the base and the collector from the top of the drawing, and the bipolar transistor Q1 is arranged in the order of the collector, the base and the emitter from the top of the drawing.

The above-described structure is similar to the structure shown in FIG. 1 of the first embodiment, in which the bipolar transistors Q24 and Q25 forming the emitter follower circuits are arranged in the same direction and the bipolar transistors Q21 and Q22 forming the differential amplifier 21. Compared to the case where the arrangement direction of the is different by 90 degrees, the manufacturing variation due to the mask shift or the like is easily absorbed, and the circuit characteristics can be further improved. That is, as in the configuration of the first embodiment, the bipolar transistor Q that constitutes each emitter follower circuit.
When the arrangement directions of 24 and Q25 and the arrangement directions of the bipolar transistors Q21 and Q22 forming the differential amplifier 21 are inverted by 90 degrees, mask shift occurs in two directions, the vertical direction and the horizontal direction. Only the mask shift in the direction occurs.

Next, a fourth embodiment of the present invention will be described with reference to the drawings.

Here, in the fourth embodiment, the present invention is applied to a Gilbert cell called a so-called double differential amplifier.

FIG. 6 is a circuit diagram of the double differential amplifier 2, and FIG. 7 is a layout diagram thereof. Note that C, B, and E in FIG. 7 are the collector, base, and emitter of the bipolar transistor, respectively, and resistors R1A, R2A, etc. are not shown for convenience. Further, FIG. 6 also shows a physical arrangement relationship of transistors and wirings.

Since the circuit configuration of the double differential amplifier 2 is the same as that of the second embodiment, its explanation is omitted.

In the present embodiment, the emitter follower circuits 40 and 41 connected to the collectors of the transistors Q2A and Q1B of the double differential amplifier 2 are located near the double differential amplifier 2 (in the present embodiment, the double differential amplifier 2). 2 as a position closer to 2 and above it, and a double differential amplifier 2
Of the bipolar transistors Q4A, Q5A and the differential amplifier 2 which are arranged in line symmetry with respect to the center line of each of the emitter follower circuits 40, 41.
The bipolar transistors Q1A, Q2A, Q1B,
Q2B is arranged in the same direction, its emitter, base,
The collectors are arranged in a state in which the vertical arrangement order is different, that is, the collectors are arranged in a state rotated by 180 degrees about the base.

As described above, according to the present invention, each emitter follower circuit connected to the differential output terminal is located in the vicinity of the double differential amplifier 2 and at a position symmetrical with respect to the center line of the double differential amplifier 2. By arranging 40 and 41 in a concentrated manner, the symmetry of the circuit configuration can be improved, and the present invention is applied to a circuit configuration in which the signal is desired to have symmetry like the double differential amplifier 2. In this case, the characteristics of the semiconductor integrated circuit can be improved.

In particular, each emitter follower circuit 40, 41
Are centrally arranged in line-symmetrical positions near the double differential amplifier 2 to reduce the wiring distance from the double differential amplifier 2 to each emitter follower circuit 40, 41, so While suppressing an increase in the variation occurrence rate of signal transmission due to an increase in wiring length,
Since the impedance can be reduced, the characteristics of the semiconductor integrated circuit can be improved when the present invention is applied to a circuit configuration in which the signal is desired to have symmetry like the double differential amplifier.

Then, as shown in FIG. 7A, the constant current transistors Q7 and Q8 of the emitter follower circuits 40 and 41.
Similarly, by arranging them in the vicinity of the double differential amplifier 2 in the same manner, the symmetry of the semiconductor elements can be further improved and the circuit characteristics can be improved.

At this time, the constant current transistors Q7 and Q8 are also arranged so as to face the same direction as the respective bipolar transistors Q1A, Q2A, Q1B and Q2B forming the double differential amplifier 2, so that the constant current transistors Q7 and Q8 can be arranged. Since the symmetry of each of the bipolar transistors Q1A, Q2A, Q1B and Q2B constituting the double differential amplifier 2 is improved, the circuit characteristics can be improved. Since the constant current transistors Q7, Q8 and the bipolar transistors Q1A, Q2A, Q1B, Q2B forming the double differential amplifier 2 have the same emitter, base, collector upper and lower arrangement order, the symmetry is further improved. Become.

Further, as shown in FIG. 7B, the bipolar transistors Q4A and Q5A constituting the emitter follower circuits 40 and 41 are also the bipolar transistors Q1A, Q2A, Q1B and Q2B constituting the double differential amplifier 2. The emitters, the bases, and the collectors may be arranged in the same direction and in the same vertical arrangement order. In this case, the semiconductor integrated circuit is in a state of being strongly resistant to manufacturing variations due to mask misalignment and the like.

In the circuit arrangement shown in FIG. 7A,
Each of the bipolar transistors Q1A, Q2A, Q1B, Q2B constituting the double differential amplifier 2 and each of the emitter follower circuits 40, 41 can be connected to the power supply potential Vcc at the shortest distance, which is more than that of the circuit shown in FIG. 7B. As a result, a semiconductor integrated circuit with low impedance can be realized.

In each of the above embodiments, the differential amplifier 1 and the double differential amplifier 2 are described as an example, but the present invention is not limited to this, and an emitter connected to a pair of output terminals like a filter. It can be widely applied to a semiconductor integrated circuit having a follower circuit.

In addition, in each of the embodiments of the present invention, a Gilbert Cel such as a semiconductor device including an active element such as a bipolar device or a MOS device, a Mixer, an AGC circuit or the like is used.
l-structured semiconductor devices that require symmetry, semiconductor devices used in high-frequency regions, semiconductor devices used when using SiGe Process, satellite TV, terrestrial TV, cable TV, semiconductor devices for wireless LAN Also included are those used for etc.

[0052]

According to the integrated circuit of the present invention, since the emitter follower circuit is arranged in the vicinity of the circuit block and in line symmetry with respect to the center line thereof, the wiring input from the output terminal of the circuit block to the emitter follower circuit is provided. Since there is no intersection between them and the wiring lengths are the same and can be shortened, the symmetry of the circuit block including the emitter follower circuit is improved, and the circuit characteristics can be improved.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram showing a semiconductor integrated circuit according to a first embodiment of the present invention.

FIG. 2 is a layout diagram showing a semiconductor integrated circuit according to the first embodiment of the present invention.

FIG. 3 is a circuit configuration diagram showing a semiconductor integrated circuit according to a second embodiment of the present invention.

FIG. 4 is a layout diagram showing a semiconductor integrated circuit according to a second embodiment of the present invention.

FIG. 5 is a circuit configuration diagram showing a semiconductor integrated circuit according to a third embodiment of the present invention.

FIG. 6 is a circuit configuration diagram showing a semiconductor integrated circuit according to a fourth embodiment of the present invention.

FIG. 7 is a layout diagram showing a semiconductor integrated circuit according to a fourth embodiment of the present invention.

FIG. 8 is a circuit configuration diagram showing a conventional semiconductor integrated circuit.

[Explanation of symbols]

21 differential amplifier 22,23 emitter follower circuit 2 double differential amplifier 40,41 emitter follower circuit

Claims (7)

[Claims] 1. A transistor having a circuit block composed of a plurality of semiconductor elements and a pair of emitter follower circuits connected to the circuit block, wherein a transistor forming the pair of emitter follower circuits is in the vicinity of the circuit block. And a semiconductor integrated circuit which is arranged in line symmetry with respect to its center line. 2. The emitter follower circuit includes a first transistor whose base is supplied with the output of the circuit block, and a second transistor which supplies a current to the first transistor. The semiconductor integrated circuit according to claim 1. 3. The semiconductor integrated circuit according to claim 1, wherein the transistors forming the emitter follower circuit are arranged in directions different from those of the transistors forming the circuit block by 90 degrees. 4. The semiconductor integrated circuit according to claim 1, wherein the transistors forming the emitter follower circuit are arranged in the same direction as the transistors forming the circuit block. 5. The emitter, the base and the collector of the transistor forming the emitter follower circuit are arranged in the reverse order of the emitter, the base and the collector of the transistor forming the circuit block. 4. The semiconductor integrated circuit according to 4. 6. The emitter, the base and the collector of the transistor forming the emitter follower circuit are arranged in the same order as the emitter, the base and the collector of the transistor forming the circuit block. The semiconductor integrated circuit described. 7. The semiconductor integrated circuit according to claim 1, wherein the circuit block is a differential amplifier.