JP2003289103A - Semiconductor device and semiconductor-mounting apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem wherein through-currents from another chip tend to flow to an output circuit, even at turning off of the power source of a chip itself at the mounting of a plurality semiconductor chips on the same package, and sharing the power source of the output circuits of these chips. <P>SOLUTION: The semiconductor device is added with a circuit for turning off a transistor configuring the output circuit of each semiconductor chip, for setting high impedance at the time of turning off a power source for an inside circuit of each semiconductor chip. This circuit can be realized by a using only simple device, such as an inverter. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device in which a plurality of semiconductor chips are mounted in the same package, and in particular, a semiconductor integrated device in which an output circuit of the chip when the power is turned off does not pass a through current. It is about circuits.

[0002]

2. Description of the Related Art In the case of a device having an internal power supply and an output power supply, both the internal power supply and the output power supply are turned off when the chip is not used, and only one of them is OF.
There is no F. However, as shown in FIG.
A device in which (two in FIG. 1) semiconductor chips A and B are mounted in the same package, each chip has individual internal power supplies VDD1 and VDD2, and an output power supply VDDQ1
When shared by both chips, the output power supply VDDQ1 remains ON because the output power supply is shared with other chips even if the unnecessary internal power supply for one chip is turned off. ing.

[0003]

In this case, since power is still applied to the output circuit, the output circuit is
The output current of the other chip in the N state flows as a through current, causing a malfunction.

The present invention has been made to solve the above problems, and an object thereof is to prevent a through current from flowing in an output circuit of a chip whose power is turned off.

[0005]

According to another aspect of the present invention, there is provided a semiconductor device comprising: an internal circuit to which a first power source is supplied; and a second power source independent of the first power source. An output that includes an output transistor that outputs data to the outside according to an output signal of the circuit, and that turns off the output transistor when the supply of the first power supply is stopped and the second power supply is supplied. And a circuit.

According to a second aspect of the present invention, in the output circuit, the transistor forming the output transistor is a P-type MOS.
In the case of a transistor, the same potential as that of the second power source is P
When the transistor forming the output transistor is an N-type transistor, the ground potential is applied to the gate electrode of the N-type MOS transistor.

According to a third aspect of the present invention, there is provided a semiconductor mounting device, wherein an internal circuit to which a first power source is supplied and a second power source independent of the first power source are supplied, and the output of the internal circuit is output. An output transistor for outputting data to the outside in response to a signal is included, and when the supply of the first power supply is stopped and the second power supply is supplied, the output transistor is turned on.
First and second semiconductor devices each including an output circuit for setting an FF state are mounted, a first power source of the first semiconductor device is supplied from a first external power source, and a second power source of the second semiconductor device is supplied. The first power source is supplied from a second external power source, and the second power sources of the first and second semiconductor devices are supplied from a third external power source.

According to a fourth aspect of the present invention, the first and second gold conductor devices are mounted in the same package, and the pins of the package for supplying the second power source to the first and second semiconductor devices are common. Is.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment FIG. 2 shows the appearance of a package P1 to which the present invention is applied, in which two semiconductor chips A and B are mounted. The internal configuration is the same as in FIG. Moreover, in FIG.
The circuit configuration of the inverter is a logic device
INV11 etc. have been added. The chip B also has the same circuit configuration as this.

For example, the chip A is a flash memory and the chip B is a pseudo SRAM (which has a DRAM structure but can be used as an SRAM for refreshing internally), and is unnecessary for reducing current consumption. It is often used to turn off the tip.

The package P1 has a pin P_VDD1 for connecting to the internal power supply VDD1 of the chip A and a pin P_VDD2 for connecting to the internal power supply VDD2 of the chip B.
, And a shared pin P_VDDQ1 for connecting to the output (input / output) power supply VDDQ1 shared by both chips A and B, and a data input / output pin P_DQ1 shared by both chips A and B.
Equipped with.

The output circuits of the chips A and B may be provided with dedicated power supply pins (P_VDDQ1 and P_VDDQ2 as shown in FIG. 1), and both pins may be connected to each other outside the package.
Further, the data input / output pin may be individually provided for each chip. Further, the data input / output pin may be a dedicated data output pin.

In the circuit configuration of FIG. 3, the internal circuit 1 is supplied with power from the internal power supply VDD1 and the transistors Q11, Q12, Q13 and the inverter IN which form the output circuit.
V11 is supplied with power from the output power supply VDDQ1, and the output circuit of the chip B is also supplied with power from this output power supply VDDQ1.

The operation of this output circuit section will be described below.
In order to suspend the chip A, the internal power supply V for the chip A
When only DD1 is turned off, after a predetermined time, the electric charge is removed from the node of the internal circuit 1 of chip A and
The potential becomes D, and the illustrated nodes N11, N12, and N14 are also GND.
The potential is applied, and the transistor Q12 is turned off. Since the inverter INV11 is powered, this inverter I
"H" (that is, the same potential as the power supply VDDQ1) is output from NV11. Since the "H" is supplied to the gate of the transistor Q11, the transistor Q11 is also turned off.

If the transistor Q11 is the N channel, "L" (that is, the GND potential) is output from the inverter INV11 when the power source of the internal circuit 1 is turned off.

More precisely, the transistor Q1
When 1 is a P-channel, (output power supply voltage-gate potential of the transistor) is equal to or higher than the threshold value of the transistor Q11, and when the transistor Q11 is an N-channel, the gate potential of the transistor Q11 is set to the transistor Q11. It is set to be equal to or less than the threshold value of Q11.

Thus, when the power supply VDD1 of the internal circuit 1 is turned off, the transistors Q11 and Q12 in the output section are turned on.
Are both turned off and are in a high impedance state. Therefore, even if the output power supply VDDQ1 is on, the voltage flowing to the output part of the other chip B does not flow to the output part of this chip A as a through current. .

Of course, when the power supply VDD1 is OFF, the node N
If 11 is less than the threshold value of the transistor Q13, node N14 is less than the threshold value of the transistor Q12, and node N13 is more than the threshold value of the transistor Q11, the transistor Q1
1, Q12, Q13 can be turned off.

Embodiment 2 FIG. 4 shows the appearance of a package P2 on which the three chips A, B and C are mounted, and FIG. 5 shows the internal structure thereof. P_VDD1,
P_VDD2 and P_VDD3 are pins for the internal power supply for the chips A, B and C, respectively, and PVDDQ1 is a pin for the output power supply of the chip A, and PVDDQ2 is for example the chips B and C. It is a pin for the power supply for output that is shared by. The output circuits of the three chips A, B, and C can be shared by one output power supply.

Even when three or more chips are mounted in this way, the transistor in the output section of the chip whose internal circuit is powered off can be turned off.
No through current flows through the output section.

Conventionally, the power supply pin for the output circuit is taken out from the package for each chip. For this reason, it is possible to turn off the power supply of the output circuit for each chip, and by doing so, the problem of shoot-through current in the output circuit can be solved. However, each chip requires a power supply pin for an output circuit. By using the output circuit of the present invention, even if a plurality of chips share the power supply pin of the output circuit, the problem of shoot-through current in the output circuit does not occur. This can reduce the number of pins.

[0022]

According to the invention of a semiconductor device of claim 1, a second power source is supplied from an internal circuit to which a first power source is supplied, and data is output to the outside according to an output signal of the internal circuit. An output circuit that includes an output transistor for outputting, and that turns off the output transistor when the second power source is supplied after the supply of the first power source is stopped.
When the supply of the first power supply is stopped and the second power supply is supplied, it is possible to prevent the through current from flowing through the output transistor.

According to a second aspect of the present invention, in the output circuit, the transistor forming the output transistor is a P-type MOS.
In the case of a transistor, the same potential as the second power source is applied to the P
When the transistor forming the output transistor is an N-type transistor, the ground potential is supplied to the gate electrode of the N-type MOS transistor. With this configuration, the output transistor is stably turned off. It can be put into a state and a through current can be eliminated.

According to a third aspect of the invention of semiconductor mounting, an internal circuit supplied with a first power supply and a second power supply different from the first power supply are supplied, and data is output to the outside according to an output signal of the internal circuit. Mounting a first and a second semiconductor device including an output transistor, and an output circuit that turns off the output transistor when the supply of the first power is stopped and the second power is supplied. , A first power source of the first semiconductor device is supplied from a first external power source, a first power source of the second semiconductor device is supplied from a second external power source, and the first and second Since the second power source of the semiconductor device is supplied from the third external power source, even if the first power source of the first or second semiconductor device is stopped, a through current flows through the output transistor. There is no.

According to a fourth aspect of the present invention, the first and second gold conductor devices are mounted in the same package, and the pins of the package for supplying the second power source to the first and second semiconductor devices are common. Therefore, even if the pins are shared in this way, a through current does not flow in the output transistor.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration inside a package of a semiconductor integrated circuit.

FIG. 2 is an external view of a package of a semiconductor integrated circuit according to the first embodiment of the present invention.

FIG. 3 is a diagram showing a configuration inside a package of the semiconductor integrated circuit of FIG.

FIG. 4 is an external view of a package of a semiconductor integrated circuit according to a second embodiment of the present invention.

5 is a diagram showing a configuration inside a package of the semiconductor integrated circuit of FIG.

[Explanation of symbols]

1 Internal circuit, Q transistor, INV11 inverter, A, B semiconductor chip, VDDQ1 output power supply,
VDD1, VDD2 Internal circuit power supply, P package

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI Theme Coat (reference) H03K 19/0175 (72) Inventor Koubun Takatsuka 2-3-3 Marunouchi, Chiyoda-ku, Tokyo Sanryo Electric Co., Ltd. In-house (72) Inventor Hirotoshi Sato 2-3-3 Marunouchi, Chiyoda-ku, Tokyo Sanryo Electric Co., Ltd. F-term (reference) 5F038 DF17 EZ20 5F064 BB07 BB28 CC12 DD32 DD34 FF07 5J055 AX27 BX16 CX00 DX13 DX14 DX22 DX72 EZ07 GX01 5J056 AA04 BB19 CC00 DD13 DD28 EE11

Claims (4)

[Claims] 1. An internal circuit supplied with a first power supply, and an output transistor supplied with a second power supply independent of the first power supply and outputting data to the outside according to an output signal of the internal circuit. And a output circuit for turning off the output transistor when the supply of the first power supply is stopped and the second power supply is supplied. 2. In the output circuit, when the transistor forming the output transistor is a P-type MOS transistor, the same potential as that of the second power supply is applied to the gate electrode of the P-type MOS transistor, and the output transistor is 2. The semiconductor device according to claim 1, wherein when the transistor to be formed is an N-type transistor, the ground potential is applied to the gate electrode of the N-type MOS transistor. 3. An internal circuit supplied with a first power supply and an output transistor supplied with a second power supply independent of the first power supply and outputting data to the outside according to an output signal of the internal circuit. The supply of the first power supply is stopped,
And first and second output circuits that turn off the output transistor when the second power is supplied.
The semiconductor device is mounted, the first power source of the first semiconductor device is supplied from a first external power source, the first power source of the second semiconductor device is supplied from a second external power source, A semiconductor mounting device, wherein the second power source of the first and second semiconductor devices is supplied from a third external power source. 4. The first and second gold conductor devices are mounted in the same package, and the pins of the package for supplying the second power source to the first and second semiconductor devices are common. The semiconductor mounting device described.