JP2003283317A - Semiconductor circuit and power-on-reset unit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a power-on-reset unit including a semiconductor circuit configured on the reduced number of elements in a small layout area without employing capacitors and resistors. <P>SOLUTION: In a power-on-reset unit generating a signal at the time of the power rise in a power source unit, an output means 1 is provided for notifying of a source voltage VDD having reached a sufficient value for operating a P-channel MOS transistor Mp and an N-channel MOS transistor Mn. Further, without inclusion of resistor elements and capacitor elements, other elements such as, for example, transistor elements M1, M3, M2, etc., configure a means for notifying of the source voltage VDD having reached the value for operating the P-channel MOS transistor Mp and the N-channel MOS transistor Mn. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor circuit of various portable devices using a secondary battery and a power-on reset device having the semiconductor circuit.

[0002]

2. Description of the Related Art Conventionally, as a power-on reset circuit for automatically resetting when powering on electronic equipment,
There is one in which a resistor and a capacitor are connected in series between a power source and a ground, and a reset output line is connected to the midpoint of the resistor and the capacitor via a buffer. When the power was turned on, the potential at the midpoint was increased based on the time constants of the resistor and capacitor, and when the potential became constant, the reset signal was output from the buffer to the output line. .

However, in order to increase the time constant, it is necessary to use high resistance. In the case of high resistance,
If there is noise, it may malfunction. In addition, the reset signal may become unstable due to fluctuations in the power supply. Therefore, in order to stably generate the reset signal, for example, a power-on reset circuit described in Japanese Patent Laid-Open No. 2001-292054 has been proposed.

As shown in FIG. 2, the power-on reset circuit described in the above publication has a detection circuit composed of transistors N1 and N2 instead of a resistor and a capacitor, and a flip-flop circuit (inverters Np and Nm and a capacitor Cp,
Cm) and. In FIG. 2, when the power is turned on, the power supply voltage VDD sequentially rises to a saturation value, the MOS transistor N1 is turned on, and the capacitor Cp is turned on.
Is discharged to the ground VSS through the MOS transistors N1 and N2, the input voltage V1 of the flip-flop circuit decreases and the output voltage Pr of the flip-flop Pr.
Switches from L level to H level. As described above, in the circuit of FIG. 2, the stable state is inverted when the detection levels of the detection circuits N1 and N2 reach a constant value, so that the reset signal can be reliably obtained.

However, in the circuit shown in FIG. 2, when the power supply voltage rises, the output is changed in the same manner as in the conventional case. However, the operation becomes critical due to the capacitance ratio, and the transistors of the flip-flop circuits Np and Nm are turned on. Since it is initialized by the capacitors Cp and Cm when the power is turned on, a layout area for the capacitors Cp and Cm is required.

[0006]

As described above, in the conventional power-on reset device, the reset signal is not output until the voltage at which the transistor operates sufficiently, or the capacitor as in the technique described in the above publication. There is a problem that a large layout area for capacitors and resistors is required by using the and resistors. Therefore, if possible, it is desirable to reduce the layout area by reducing the number of constituent elements of the power-on reset device. In addition, it is necessary to prevent malfunction even when noise is added without using a high resistance.

Therefore, an object of the present invention is to solve these conventional problems, to provide a semiconductor circuit having a small number of constituent elements and a reduced layout area and a power-on reset device for the same, without using a capacitor or a resistor. To provide.

[0008]

In order to achieve the above object, a power-on reset device having a semiconductor circuit according to the present invention is characterized by notifying that a power supply voltage at which a transistor is operable has reached a value. . Also,
The semiconductor circuit of the present invention is characterized by achieving the characteristics of a power-on reset device without including a resistance element and a capacitance element. Further, it is characterized in that it notifies that the power supply voltage at which the transistor is operable has reached a value and enables specific control when the power supply voltage is zero.

Further, it is characterized in that the above characteristics are achieved without including a resistance element and a capacitance element. Further, it is characterized by comprising P-channel MOS transistors M1 and MP, N-channel MOS transistors M3 and Mn, and depletion MOS transistor M2 (see FIG. 1).

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a circuit diagram of a power-on reset device having a semiconductor circuit according to an embodiment of the present invention. As shown in FIG. 1, the circuit configuration of this embodiment has a P-channel MOS transistor M between a power source 2 and a ground 3.
1, depletion MOS transistor M2, and N
A series circuit including a channel MOS transistor M3,
It has a configuration in which an inverter circuit including a P-channel MOS transistor MP and an N-channel MOS transistor Mn is connected in parallel. And P channel M
The power-on reset output line 1 is provided on the source side of the OS transistor MP and the source side of the N-channel MOS transistor Mn.

In this embodiment, an inverter circuit of P-channel MOS transistor MP and N-channel MOS transistor Mn which receives the voltage of Pr0 as a gate input, and Pr.
P-channel MOS transistor M1 and N-channel MOS whose gate inputs are voltage 00 and voltage Pr0, respectively.
The transistor M3 forms a flip-flop, and the P-channel MOS transistor M1 and the N-channel MOS transistor M3, which are connected in series with the depletion MOS transistor M2, make the time constant similar to the series connection of the resistance element and the capacitance element. It forms the operating element.

The operation will be described below. P channel MOS
Since the gate of the transistor M1 is the drain Pr00 of the depletion MOS transistor M2 and the gate of the N-channel MOS transistor M3 is the source Pr0 of the depletion MOS transistor M2 higher than the voltage of Pr00, the power-on reset output line 1 To Pr0 until the power supply voltage VDD reaches a specific level.
The voltage level of 2 becomes an intermediate level between the power supply 2 and the ground 3, and when the power supply voltage VDD above the specific level is supplied, it outputs almost the same'H 'level as the power supply voltage VDD.

The inverter composed of the P-channel MOS transistor MP and the N-channel MOS transistor Mn uses the P-channel M transistor so that the voltage higher than the intermediate level of Pr0 is used as the input voltage threshold.
The transistor size values of the OS transistor MP and the N-channel MOS transistor Mn are set. That is, the output (Pr) 1 of the inverter is Pr0 of the input.
When it is at an intermediate level, it outputs an'H 'level, and when it reaches or exceeds the specific level, it outputs an'L' level.

Since the depletion MOS transistor M2 is provided to suppress the current consumption and to cause a voltage drop, it is possible to replace the transistor M2 with a resistance element or the like. When used in a power supply device having a standby mode, a transistor that is turned off during standby can be added as a component element between the depletion MOS transistor M2 and the ground 3.

In this way, the power-on reset output 1
Can detect that the power supply voltage VDD has reached a specific level or higher. Therefore, in the circuit of this embodiment, the number of constituent elements is small and the layout area is reduced.
A power-on reset signal can be generated.

A first feature of the present invention is that, in a power-on reset device that generates a signal when the power supply of the power supply device rises, the value of the power supply voltage becomes a value at which the P-channel MOS transistor and the N-channel MOS transistor can operate. That is to have an output means for notifying the user. According to the first feature, the circuit can be brought into a reset state at a low voltage level at which the power supply voltage is insufficient to operate the circuit element, so that when the power supply rises to a voltage sufficient to operate the transistor. It is possible to prepare an initial state in the above, and as a result, an uncertain operation is not caused.

A second feature of the present invention is that, in the semiconductor circuit described above, the P-channel MOS transistor and the N-channel MOS transistor whose power supply voltage is not included in the resistive element and the capacitive element are provided by other elements such as a transistor element. It is to configure means for notifying that the value becomes operable. According to the second feature, since the function of the first feature can be produced with a small number of transistor constituent elements without including a resistance element and a capacitive element, the layout area of the constituent elements can be reduced.

A third feature of the present invention is that in a semiconductor device for controlling charging / discharging of a secondary battery, the fact that the value of the power supply voltage at which the transistor is operable is reached is notified, and the specific control is performed when the power supply voltage is zero. It is to have a means to do. In a semiconductor device that operates using a secondary battery as a power source,
A predetermined initial state can be generated even when the voltage of the secondary battery is zero to the voltage at which the transistor included in the circuit of the semiconductor device can operate.

A fourth feature of the present invention is to achieve the above characteristics in the semiconductor circuit having the above third feature without including a resistance element and a capacitance element. The fifth feature of the present invention is to achieve the above characteristics by the circuit configuration shown in FIG. According to the fourth and fifth characteristics, the same effect as the above matters can be obtained.

[0020]

As described above, according to the present invention,
It is possible to realize a semiconductor circuit having a small number of constituent elements and a reduced layout area and a power-on reset device thereof without using a capacitor or a resistor. In addition, the circuit can be reset at a voltage level that is low enough to operate the circuit elements, so prepare an initial state when the power supply rises to a voltage sufficient to operate the transistor. There is an effect that it can be set and does not cause an uncertain operation. Further, since the above-described action can be produced with a small number of transistor constituent elements, the layout area of the constituent elements can be reduced. Further, in a semiconductor device that operates using a secondary battery as a power source, a predetermined initial state must be generated even when the secondary battery is zero and a voltage at which a transistor included in a circuit of the semiconductor device is operable. There is an effect that can be.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram of a power-on reset device having a semiconductor circuit according to an embodiment of the present invention.

FIG. 2 is a circuit configuration diagram of a conventional power-on reset circuit.

[Explanation of symbols]

1 ... Power-on reset output line, 2 ... Power supply, 3 ... Ground, M1, Mp ... P-channel MOS transistor, M
3, Mn ... N-channel MOS transistor, M2 ... Depletion MOS transistor, VDD ... Power supply voltage, V
SS ... Ground voltage, Pr0 ... Inverter circuit input voltage, Pr00 ... Gate input voltage of P-channel MOS transistor M1.

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H01L 27/04 H01L 27/08 102J 27/088 H03K 17/687 F term (reference) 5B015 HH05 JJ37 KB91 NN02 QQ03 5B054 BB01 DD01 DD11 DD21 EE05 5F038 DF01 DT12 EZ20 5F048 AA01 AB03 AB04 AB08 AB10 AC02 AC03 BB03 5J055 AX57 BX41 DX13 DX14 DX22 DX82 EX07 EY21 FX12 GX01

Claims (5)

[Claims] 1. A power-on reset device that generates a signal when the power supply of the power supply device rises, comprising output means for notifying that the power supply voltage has reached a value at which a transistor as a constituent element can operate. Power-on reset device having a semiconductor device. 2. A means for notifying externally that the power supply voltage has reached a value at which the transistor element can be operated by the other transistor element without including the resistance element and the capacitance element in the semiconductor circuit. A semiconductor circuit having a structure. 3. A semiconductor device for controlling charging and discharging of a secondary battery, which means to externally notify that a transistor has reached a value of a power supply voltage at which it can operate and to perform a specific control when the power supply voltage is zero. A semiconductor circuit comprising: 4. The semiconductor circuit according to claim 3, wherein the control means achieves the above characteristics by being configured by an element other than the resistive element and the capacitive element without including the resistive element and the capacitive element. Semiconductor circuit. 5. A first P-channel MOS transistor, a depletion MOS transistor, and a first N-channel MOS transistor are connected in series between a power supply and a ground, and the drain of the first N-channel MOS transistor. An inverter circuit comprising a second P-channel MOS transistor and a second N-channel MOS transistor, which has an output and a source output of the depletion MOS transistor as gate inputs, and a source of the second P-channel MOS transistor A power-on reset device having a semiconductor circuit, wherein an output terminal is provided between the sources of the second N-channel MOS transistor.