JP3770824B2 - Power-on reset circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a power-on reset circuit that generates a reset signal for initializing a predetermined circuit when power is turned on.
[0002]
[Prior art]
In general, electric devices such as mobile phones, personal computers, and audio devices are provided with a power-on reset circuit that generates a reset signal for initializing a predetermined circuit (logic circuit or the like) when the power is turned on. Here, the conventional power-on reset circuit is roughly divided into three methods (method using an RC time constant circuit, method using a comparison circuit between a voltage varying with a power supply voltage and a threshold voltage, and a method using a CMOS logic circuit). Regardless of which method is employed, it is possible to generate a reset signal when the power is turned on.
[0003]
[Problems to be solved by the invention]
However, in the case of using a RC time constant circuit to output a reset signal after a predetermined period from power-on (Japanese Patent Laid-Open No. 5-299993, etc.), in order to prevent malfunction due to power noise or power interruption, The capacity or both of them must be increased to extend the discharge time of the RC time constant circuit, and the level that can be handled with very small resistors and capacitors that can be integrated in semiconductor devices has been extremely limited.
[0004]
Further, in the case of a method of generating a reset signal by comparing a voltage that changes according to a power supply voltage and a threshold voltage (Japanese Patent Laid-Open No. 5-335915, etc.), several tens to several numbers after the reset signal is output due to its circuit configuration. There was a problem that a constant current of 100 μA continued to flow. Therefore, this method is extremely disadvantageous for portable devices (such as a mobile phone using a battery as a power source) in which current consumption is reduced.
[0005]
In the case of a method using a CMOS logic circuit (Japanese Patent Laid-Open No. 9-83327, etc.), the initial value of the logic is unstable in a transient state immediately after the power is turned on. Alternatively, when biased toward the ground side, there is a problem that noise margin is reduced and resistance to noise is reduced.
[0006]
In view of the above problems, an object of the present invention is to provide a power-on reset circuit that can satisfy all of circuit integration, steady-state current elimination, and noise resistance improvement.
[0007]
[Means for Solving the Problems]
In order to achieve the above object, a power-on reset circuit according to the present invention is a power-on reset circuit that generates a reset signal for initializing a predetermined circuit when power is turned on, and rises until the power supply voltage reaches a threshold value. A voltage generating means for generating an output voltage that changes to a predetermined value when the power supply voltage reaches the threshold value, and an output state changes when the output voltage of the voltage generating means changes to the predetermined value. Latching means, means for interrupting current supply to the voltage generating means when the output voltage of the voltage generating means changes to the predetermined value and the output state of the latching means changes, and the voltage generating means Means for transitioning the output voltage to the predetermined value.
[0008]
As a specific example of the power-on reset circuit, first and second resistors having one end connected to the power supply voltage line, a first switch having one end connected to the other end of the first resistor, and one end A second switch connected to the other end of the second resistor, a diode having an anode connected to the other end of the first switch, a base connected to the cathode of the diode, and a collector connected to the other end of the second switch The npn transistor whose emitter is connected to the reference voltage line, one end connected to the first connection node connecting the second switch and the collector of the npn transistor, and the other end connected to the reference voltage line. A third switch, a first inverter circuit whose input terminal is connected to the first connection node, a set terminal is connected to the output terminal of the first inverter circuit, and a reset terminal is the first connection An RS latch circuit connected to the node and having an output terminal connected to each control terminal of the first, second and third switches, one end connected to the output terminal of the RS latch circuit, and the other end connected to the reference voltage line And a second inverter circuit whose input terminal is connected to the output terminal of the RS latch circuit and whose output terminal is connected to the reset terminal of the predetermined circuit. When the npn-type transistor is turned on and the npn transistor is turned on, the output voltage of the first connection node changes to the L level, and when the output voltage of the RS latch circuit becomes the H level later, the first and second It is preferable that the second switch is turned off and the third switch is turned on.
[0009]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a circuit diagram showing a configuration example of a power-on reset circuit according to the present invention. The power-on reset circuit 1 is a circuit that initializes the logic circuit 2 by generating a reset signal when the power is turned on. As shown in this figure, resistors R1, R2, switches S1, S2, S3, diodes D1, npn-type bipolar transistor Q1, inverter circuits I1, I2, and I3, NAND circuits N1, N2, and N3, and a capacitor C1.
[0010]
First, the configuration of the power-on reset circuit 1 will be described. One ends of the resistors R1 and R2 are respectively connected to the power supply voltage line L1, and the power supply voltage Vcc is applied when the power is turned on. The other end of the resistor R1 is connected to the anode of the diode D1 via the switch S1, and the cathode of the diode D1 is connected to the base of the transistor Q1. The other end of the resistor R2 is connected to the collector of the transistor Q1 via the switch S2. The emitter of the transistor Q1 is connected to the reference voltage line L2. In the present embodiment, the reference voltage line L2 is set to the ground potential GND.
[0011]
A connection node A between the switch S2 and the transistor Q1 is connected to one input terminal of the NAND circuit N1, and is also connected to the reference voltage line L2 via the switch S3. The connection node A is also connected to the other input terminal of the NAND circuit N1 and one input terminal of the NAND circuit N2 via the inverter circuits I1 and I2. The output terminal of the NAND circuit N1 is connected to one input terminal of the NAND circuit N3, and the output terminals of the NAND circuits N2 and N3 are connected to the other input terminals of each other. That is, the inverter circuit I2 and the NAND circuits N1, N2, and N3 constitute a set priority RS latch circuit L1.
[0012]
The input terminal of the inverter circuit I2 corresponds to the set terminal S of the RS latch circuit L1, and one input terminal of the NAND circuit N1 corresponds to the reset terminal R of the RS latch circuit L1. The output terminal of the NAND circuit N2 corresponds to the output terminal Q of the RS latch circuit L1.
[0013]
The output terminal of the NAND circuit N2 is connected to the reset terminal of the logic circuit 2 through the inverter circuit I3, and is also connected to the reference voltage line L2 through the capacitor C1. The output terminal of the NAND circuit N2 is also connected to the control terminals of the switches S1, S2, and S3.
[0014]
In the power-on reset circuit 1 of the present embodiment, the above-described switches S1 and S2 are configured by p-channel MOS transistors, and the switch S3 is configured by an n-channel MOS transistor.
[0015]
Next, the operation of the power-on reset circuit 1 having the above configuration will be described. In the transition period immediately after the power supply to the power-on reset circuit 1 is turned on, the RS latch circuit L1 has priority to set, and the control terminals (gate terminals) of the switches S1, S2, and S3 are all set according to the charge conservation law of the capacitor C1. L level. Accordingly, the switches S1 and S2 are both turned on and the switch S3 is turned off.
[0016]
When the power supply voltage Vcc starts to be applied to the power supply voltage line L1 in this state, the voltage at the connection node A (hereinafter referred to as the output voltage A) is between the time when the power supply voltage Vcc reaches the threshold value and the transistor Q1 is turned on. It rises as the power supply voltage Vcc rises. At this time, voltages applied to the set terminal S and the reset terminal R of the RS latch circuit L1 (hereinafter referred to as input voltages S and R) are L level and H level, respectively, so that the output terminal Q of the RS latch circuit L1. (Hereinafter referred to as the output voltage Q) remains at the L level. Therefore, the output voltage of inverter circuit I3 (hereinafter referred to as output voltage B) rises as the power supply voltage Vcc rises. The switches S1, S2, and S3 maintain the initial state.
[0017]
However, immediately after the power is turned on, the output voltage Q may be unintentionally set to the H level during the period when the logic of the RS latch circuit L1 is indeterminate. In such a state, the switches S1 and S2 are turned off and the switch S3 is turned on, so that the power-on reset circuit 1 becomes inoperable. Therefore, the power-on reset circuit 1 of the present embodiment has a configuration in which a capacitor C1 is connected to the output terminal Q of the RS latch circuit L1.
[0018]
With such a configuration, even when the output voltage Q becomes H level during the period when the logic of the RS latch circuit L1 is indeterminate, the switches S1, S2,. The voltage applied to the control terminal of S3 can be maintained at the L level. Therefore, if the capacitance value of the capacitor C1 is set so that the charging time of the capacitor C1 is longer than the logic determination time of the RS latch circuit L1, the above-described problem that the power-on reset circuit 1 becomes inoperable can be avoided. Can do. Further, compared to a power-on reset circuit having a conventional configuration in which the threshold voltage is biased toward the power supply side or the ground side in order to determine the initial value of the CMOS logic, the resistance to noise can be greatly improved.
[0019]
Note that the logic uncertain period of the RS latch circuit L1 is a very short period at the beginning of power supply startup. Since the power supply voltage Vcc is still low during this period, the current supply capability of the NAND circuit N2 output is very low, and charging takes time even if the capacitor C1 has a small capacity. Therefore, the logic of the RS latch circuit L1 is sufficiently determined. It is possible to create a state. For example, if the capacitance value of the capacitor C1 is set to about several pF to several tens pF, the power supply rise time can correspond to about 100 ms. Therefore, it is sufficiently possible to integrate the power-on reset circuit 1 including the capacitor C1 in the semiconductor device.
[0020]
When the power supply voltage Vcc further rises and the transistor Q1 is turned on, the connection node A becomes conductive with the reference voltage line L2, so that the output voltage A changes to the reference voltage (L level). At this time, since the input voltages S and R become H level and L level, respectively, the output voltage Q becomes H level and the output voltage B changes to the reference voltage (L level). The falling edge of the output voltage B is used as a reset signal for the logic circuit 2.
[0021]
Here, the power-on reset circuit 1 of the present embodiment is configured to turn off the switches S1 and S2 when the output voltage A changes to the L level and the output voltage Q becomes the H level later. With such a configuration, after the reset signal is generated, a steady current does not flow from the power supply voltage line L1 to the reference voltage line L2, so that the static current consumption can be reduced.
[0022]
Furthermore, the power-on reset circuit 1 of the present embodiment is configured to turn on the switch S3 at the same time as turning off the switches S1 and S2. With this configuration, the output voltage A is held at the L level even after the switches S1 and S2 are turned off. Therefore, the logic of the RS latch circuit L1 remains fixed, and the output voltage B is maintained at the L level.
[0023]
Further, as described above, the power-on reset circuit 1 of the present embodiment has a configuration in which the capacitor C1 is connected to the output terminal Q of the RS latch circuit L1, and a predetermined delay is given to the state change of the output voltage Q. Yes. Therefore, in the power-on reset circuit 1 of the present embodiment, the on / off control of the switches S1, S2, and S3 is performed after the transistor Q1 is turned on and the output voltage A is reliably at the L level. The reset signal can be generated reliably.
[0024]
Next, the operation of the power-on reset circuit 1 of the present embodiment when the power supply voltage Vcc is momentarily interrupted will be described. FIG. 2 is a circuit diagram showing the internal configuration of the NAND circuit N2 and its peripheral portion.
[0025]
As shown in FIG. 5A, when the power supply voltage Vcc is steady, both input voltages to the NAND circuit N2 are at L level. Therefore, the output voltage Q is at the H level, and the capacitor C1 is charged.
[0026]
Here, focusing on the P-channel MOS transistors P1 and P2 constituting the NAND circuit N2, the potential of the power supply voltage Vcc is lower than the potential at the Q point of the capacitor C1 when the power supply voltage Vcc is momentarily interrupted. As shown in FIG. 4B, the power is discharged to the power supply voltage line through the drains of the transistors P1 and P2. Therefore, in the power-on reset circuit 1 of the present embodiment, even when the power supply voltage Vcc is momentarily interrupted, if the capacitor C1 is sufficiently discharged, it is possible to perform almost the same operation as when the power is turned on. .
[0027]
If the discharge capacity of the transistors P1 and P2 is insufficient, a necessary number of P-channel MOS transistors P3,..., Pn having their gate electrodes connected to the power supply voltage line may be added as shown in FIG. . These transistors P3,..., Pn are off because the gate potential is the power supply voltage Vcc when the power supply voltage Vcc is steady, but when the power supply voltage Vcc is momentarily interrupted, the potential difference between the Q point potential and the power supply voltage Vcc is the same as described above. A discharge path is formed.
[0028]
【The invention's effect】
As described above, the power-on reset circuit according to the present invention is a power-on reset circuit that generates a reset signal for initializing a predetermined circuit when power is turned on, and changes according to the rise until the power supply voltage reaches a threshold value. And a voltage generating means for generating an output voltage that changes to a predetermined value when the power supply voltage reaches the threshold value, and a latch whose output state changes when the output voltage of the voltage generating means changes to the predetermined value. And means for interrupting current supply to the voltage generating means when the output voltage of the voltage generating means changes to the predetermined value and the output state of the latch means changes, and the output voltage of the voltage generating means And a means for making a transition to the predetermined value.
[0029]
With such a configuration, it is possible to provide a power-on reset circuit that can satisfy all of circuit integration, steady-state current elimination, and noise resistance improvement.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing an example of a power-on reset circuit according to the present invention.
FIG. 2 is a circuit diagram showing an internal configuration of a NAND circuit N2 and its peripheral part.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Power-on reset circuit 2 Logic circuit R1, R2 Resistor S1, S2, S3 Switch D1 Diode Q1 npn type bipolar transistor I1, I2, I3 Inverter circuit N1, N2, N3 NAND circuit FF1 SR flip-flop circuit C1 Capacitor L1 Power supply voltage line (Vcc)
L2 reference voltage line (GND)
P1, P2, P3,..., Pn P channel MOS transistor

Claims (3)

In a power-on reset circuit that generates a reset signal for initializing a predetermined circuit when power is turned on,
Until the power supply voltage reaches a threshold value, the voltage generation means generates an output voltage that changes according to the rise of the power supply voltage and changes to a predetermined value when the power supply voltage reaches the threshold value, and the output voltage of the voltage generation means is the predetermined voltage Latch means for changing the output state when it changes to a value, delay means for delaying the output state change of the latch means, and the output voltage of the voltage generating means changes to the predetermined value and the output state of the latch means changes A power-on reset circuit, comprising: means for interrupting current supply to the voltage generation means; and means for transitioning the output voltage of the voltage generation means to the predetermined value. 2. The power-on reset circuit according to claim 1, wherein the delay unit is a capacitor connected to an output terminal of the latch unit. 3. The power-on reset circuit according to claim 2, further comprising means for discharging the electric charge of the capacitor when the power supply voltage is momentarily interrupted.

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