JP2003283300A - Frequency regulation circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a frequency regulation circuit which is built in a mobile telephone and accurately operates for different reference clock signals. <P>SOLUTION: The frequency regulation circuit includes a frequency divider 28 which divides a reference clock signal 21, a reference filter 29 which sets a phase difference to the output signal of the frequency divider 28, a multiplication circuit 30 which multiplies the output signal of the reference filter 29 and the output signal of the frequency divider 28, and a low pass filter 31 connected to the output of the multiplication circuit. It is composed in that a selector 24 of the frequency divider 28 in the frequency regulation circuit 20 changes frequency division ratio of a plurality of the different reference clock signals 21 and makes it to be unified to the cutoff frequency of the reference filter 29, in the frequency regulation circuit 20 which carries out negative feedback to the reference filter 29 as the output voltage of the low pass filter 31 and the cutoff frequency of the reference filter 29 become constant. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency adjusting circuit for adjusting the frequency with respect to variations in filters formed on the same semiconductor substrate.

[0002]

2. Description of the Related Art Conventionally, in communication equipment and AV equipment, in order to favorably perform demodulation processing of a digitally modulated signal, a filter having a high cutoff frequency and excellent reproducibility is used. FIG.
The configuration of the frequency adjusting circuit 1 will be described. A reference clock signal 2 made of a crystal oscillator or the like is input to the frequency adjusting circuit 1 through an input terminal 3. The frequency adjusting circuit 1 comprises a reference filter 4, a multiplying circuit 5, and a low-pass filter 6 corresponding to the reference clock signal 2 and is outputted from the low-pass filter 6 so that the phase difference between the input and output signals of the reference filter 4 becomes constant. A phase control loop for performing negative feedback control of the control voltage is formed to set the characteristics of the frequency adjusting circuit 1 with high accuracy and reproducibility.

This control voltage is applied to the baseband filter 14
An analog-to-digital converter (hereinafter referred to as ADC) that removes unnecessary frequency signals of the digital modulation signal converted to the baseband frequency band received by the baseband amplifier 13 and received from the antenna by the baseband filter 14
The signal is quantized in order to demodulate the signal by inputting to 15 and digital processing.

The reference clock signal 2 is the reference clock signal 7
When it changes to, the frequency adjustment circuit 9 is used to use the reference filter 10 and the multiplication circuit 11 corresponding to the reference clock signal 7.
And the low-pass filter 12, and the negative-feedback control of the control voltage output from the low-pass filter 12 is performed so that the phase difference between the input and output signals of the reference filter 10 becomes constant. It is set.

This control voltage is applied to the baseband filter 14
Is applied to the baseband amplifier 13 to remove the unnecessary frequency signal of the digital modulation signal converted to the baseband frequency band received from the antenna by the baseband filter 14 and input to the ADC 15 to demodulate the signal by digital processing. Is being quantized.

In this way, the circuit is designed by designing individual filters corresponding to a plurality of reference clock signals.

As described above, there is a problem in that the individual frequency adjusting circuits 1 and 9 corresponding to a plurality of reference clock signals must be prepared, and the shape of the constituent devices becomes large.

[0008]

However, the frequency of the reference clock signal used in the mobile phone differs depending on the manufacturer and model, and there are a plurality of reference clock signals. Therefore, there is a problem that each company must manufacture a dedicated frequency adjustment circuit for each type of mobile phone.

It is an object of the present invention to provide a frequency adjusting circuit which can accommodate a reference clock signal even if it is built in a mobile phone having a different reference clock signal.

[0010]

According to a first aspect of the present invention, there is provided a frequency dividing circuit for dividing a reference clock signal, a reference filter for setting a phase difference in an output signal of the frequency dividing circuit, The output signal of the reference filter is multiplied by the output signal of the frequency divider circuit, and a low-pass filter connected to the output of the multiplication circuit is provided. The output voltage from the low-pass filter is the cut-off frequency of the reference filter. In a frequency adjustment circuit in which negative feedback is applied to the reference filter so as to be constant, the cutoff frequency of the reference filter is constant by changing the division ratio of a plurality of different reference clock signals with the selector of the frequency divider circuit in one frequency adjustment circuit. The frequency adjusting circuit having the above-mentioned configuration can handle a plurality of reference clock signals with one frequency adjusting circuit, and the receiver can be downsized.

The invention according to claim 2 of the present invention is the frequency adjusting circuit according to claim 1, wherein the control circuit controls the selector by the output signal of the frequency detection circuit connected to the reference clock signal. , It is possible to detect a plurality of reference clock signals and automatically set the division ratio.

According to a third aspect of the present invention, the control circuit controls the selector by the output signal of the frequency detection circuit connected to the frequency-divided signal of the reference clock signal. The frequency detection circuit automatically detects the frequency of the signal obtained by dividing the reference clock signal frequency and controls the selector, so the division ratio can be set automatically without external control. .

The invention according to claim 4 of the present invention is the frequency adjusting circuit according to claim 1, wherein the control circuit controls the selector by a digital signal supplied from the outside. The frequency division ratio can be set by controlling the selector with a digital signal.

The invention according to claim 5 of the present invention is the frequency adjusting circuit according to claim 4, wherein the digital signal is supplied from a microprocessor for controlling the mobile telephone. Since a digital signal is given by, the division ratio can be set without adding a dedicated microprocessor.

The invention according to claim 6 of the present invention is the frequency adjusting circuit according to claim 4, wherein the digital signal is applied by powering or grounding the terminal of the control circuit. The division ratio can be set without adding a circuit to give a digital signal.

The invention according to claim 7 of the present invention is the frequency adjusting circuit according to claim 1, wherein the phase difference between the input and output signals of the reference filter is 90 °. Even when different reference clock signals are input according to different frequencies, more accurate frequency adjustment becomes possible.

According to the eighth aspect of the present invention, a DC voltage correction circuit is connected between the output of the multiplication circuit and the baseband filter, and the DC voltage is corrected for different reference clock signal frequencies. Claims 1 to 7
In the frequency adjusting circuit according to any one of the above, by correcting the DC voltage, more accurate frequency adjustment becomes possible.

According to a ninth aspect of the present invention, the control circuit sets the correction amount of the DC voltage by the output signal of the frequency detection circuit connected to the reference clock signal. This is an adjusting circuit, and the frequency detecting circuit automatically detects the reference clock signal frequency and sets the correction amount of the DC voltage, so that the correction amount can be automatically set without external control.

According to a tenth aspect of the present invention, the control circuit sets the correction amount of the DC voltage by the output signal of the frequency detection circuit connected to the frequency-divided signal of the reference clock signal. The frequency adjustment circuit according to Item 8, wherein the frequency detection circuit automatically detects the frequency obtained by dividing the reference clock signal frequency and sets the DC voltage correction amount, so the correction amount is automatically set without external control. can do.

The invention according to claim 11 of the present invention is the frequency adjusting circuit according to claim 8, wherein the control circuit sets the correction amount of the DC voltage by a digital signal given from the outside. The correction amount of the DC voltage can be set by the digital signal given by

A twelfth aspect of the present invention is the frequency adjusting circuit according to the eleventh aspect of the present invention, wherein the digital signal is provided from a microprocessor that controls the mobile telephone. Since a digital signal is given by, the correction amount of the DC voltage can be set without adding a dedicated microprocessor.

The thirteenth aspect of the present invention is the frequency adjusting circuit according to the eleventh aspect, wherein the digital signal is applied by powering or grounding the terminal of the control circuit. Since a digital signal is given, the correction amount of the DC voltage can be set without adding a circuit.

[0023]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) In FIG. 1, the frequency adjusting circuit 20 has a system driving clock frequency of 13.5 MHz at one input terminal 22 of a frequency dividing circuit 28 for a portable telephone.
The reference clock signal 21 is input. The input reference clock signal 21 enters the selector 24, and the selector 24 selects the ½ frequency divider 25 according to the signal from the control circuit 23. The frequency of the reference clock signal 21 is divided by the frequency divider 25 into 6.75 MHz. Further, this frequency-divided signal is frequency-divided by the frequency divider 27 into 3.375 MHz. In this way, the frequency from the frequency dividing circuit 28 is 3.375 MHz.
The output signal of z is input to the reference filter 29.

The phase frequency characteristic of the reference filter 29 is as shown in FIG. The input frequency of the reference filter 29 is plotted on the horizontal axis, and the input / output phase difference of the reference filter 29 is plotted on the vertical axis, showing the phase characteristics with respect to the frequency of the reference filter 29.

From FIG. 2, if there is a frequency signal input to the reference filter 29 between the frequencies f1 and f2, the multiplication circuit 30 can detect the phase difference between the signals, so the reference filter 2
9 phase control is possible.

The output of the multiplication circuit 30 is the signals Acos ωt and Bcos (ωt +) having the phase difference φ at the inputs.
φ) is input, AB [cos (φ) -cos
(2ωt + φ)] / 2 is output. ABcos here
(Φ) / 2 represents a DC voltage, and ABcos (2ωt +
φ) / 2 is an unnecessary AC signal having a doubled frequency.

By removing this AC signal with the low-pass filter 31, a DC voltage ABcos having a correlation with the phase difference is obtained.
(Φ) / 2 can be obtained.

Since the phase difference is expressed by the cos function, the phase difference can be uniquely detected between 0 and 180 °, and the phase difference is 90 °.
It is possible to control the phase of the reference filter 29.

As is apparent from FIG. 2, the reference filter 29
In the output signal having a frequency of 3.375 MHz, a signal having a phase difference of approximately 90 degrees at the initial control voltage is generated. An output signal with a frequency of 3.375 MHz provided with this phase and a frequency of 3.375 M divided by the frequency dividing circuit 28.
The output signal of Hz is multiplied by the multiplication circuit 30 and the output voltage corresponding to the phase difference is output. Next, the AC signal, which is an unnecessary frequency component incidental to this output voltage, is removed by the low-pass filter 31 and a control voltage is applied to the control terminal of the reference filter 29 to adjust the phase difference of the reference filter 29 to 9
A phase control loop for setting 0 ° is formed. This control voltage is applied to the baseband filter 33, the unnecessary frequency signal of the digital modulation signal converted into the baseband frequency band received from the antenna by the baseband amplifier 32 is removed by the baseband filter 33, and is input to the ADC 34 for digital processing. Quantize the signal to demodulate it.

Next, the system drive clock frequency is 1
In a mobile phone of 9.998 MHz, a signal having a system drive clock frequency of 19.998 MHz is input as the reference clock signal 21. The inputted reference clock signal 21 enters the selector 24, and the selector 24 selects the frequency divider 26 according to the signal from the control circuit 23. Then, the reference clock signal 21 is divided by a frequency divider 26 into a frequency of 6.66 MHz, and further divided by a frequency divider 27 into a frequency of 3.33 MHz. This frequency divider 2
An output signal having a frequency of 3.33 MHz from 8 is input to the reference filter 29.

In this case, as shown in FIG.
Since MHz is between f1 and f2, the reference filter 29
A phase control loop is formed to bring the phase difference of 90 ° to 90 ° at 3.333 MHz.

In this way, in a mobile phone having a plurality of different system drive clock frequencies, these system drive clock frequencies are used as the reference clock signal 21, and the frequency division is performed by the selector 24 and the frequency dividers 25 and 27 and the frequency divider 26. The circuit 28 converts the reference clock signal 21 into the reference filter 2
The reference filter 29, the multiplication circuit 30, which are configured in the frequency adjustment circuit 20 by dividing the frequency into the frequency adjustable range of 9,
The negative feedback loop including the low-pass filter 31 operates normally, and one frequency adjusting circuit 20 can handle a plurality of reference clock signals, and a predetermined control voltage can be applied to the baseband filter 33.

The frequency division ratio is the reference filter 2 described this time.
Needless to say, the present invention is not limited to the phase and frequency of 9 and can be applied to various filter characteristics.

In FIG. 3, the circuit block described in FIG. 1 is provided with a frequency detection circuit 35. In FIG. 3, first, the frequency of the reference clock signal 21 is 13.5 MHz.
The case will be described. 13.5MHz is input terminal 2
When input to 2, the frequency detection circuit 35 connected to the input terminal 22 detects the frequency. The detection result is transmitted to the control circuit 23. The selector 24 receiving the signal from the control circuit 23 selects the 2 frequency divider 25, and the 13.5 MHz signal is divided by the 2 frequency divider 25 and the 2 frequency divider 27 into the 3.375 MHz signal and the reference filter 29. Entered in. After that, the cutoff frequencies of the reference filter 29 and the baseband filter 33 are adjusted in the same manner as in the first embodiment.

Next, the frequency of the reference clock signal 21 is 1
The case of 9.998 MHz will be described. 19.99
When 8 MHz is input to the input terminal 22, the input terminal 22
The frequency detection circuit 35 connected to detects the frequency and transmits the detection result to the control circuit 23. The selector 24 receiving the signal from the control circuit 23 selects the 3 frequency divider 26, so that the 19.998 MHz signal is divided by the 3 frequency divider 26 and the 2 frequency divider 27 and the 3.333 MHz signal is converted to the reference filter 29. Entered in. After that, the cutoff frequencies of the reference filter 29 and the baseband filter 33 are adjusted in the same manner as in the first embodiment.

In FIG. 4, when there is no input to the frequency detection circuit 35, the control circuit 23 causes the selector 24 to change the frequency divider 2 to 2.
5 is selected. A case where the frequency of the reference clock signal 21 is 13.5 MHz will be described. Entered 1
The 3.5 MHz signal is divided by the frequency divider 25 to 6.75.
The MHz signal is input to the frequency detection circuit 35. The frequency detection circuit 35 detects the frequency of 6.75 MHz, determines that the frequency of the reference clock signal 21 is 13.5 MHz, and transmits the result to the control circuit 23. The control circuit 23 determines that switching of the selector 24 is unnecessary and does not perform switching control. As a result, the 13.5MHz signal is divided by 25.
Then, the 3.375 MHz signal divided by the frequency divider 27 is input to the reference filter 29. After that, the reference filter 29 and the baseband filter 33 are the same as in the first embodiment.
The cutoff frequency is adjusted.

Next, the frequency of the reference clock signal 21 is 1
The case of 9.998 MHz will be described. The input 19.998 MHz is divided by 2 by the frequency divider 25 to 9.9.
The 99 MHz signal is input to the frequency detection circuit 35.
The frequency detection circuit 35 detects the frequency 9.999 MHz, determines that the frequency of the reference clock signal is 19.998 MHz, and transmits the result to the control circuit 23. The control circuit 23 determines that the selector 24 needs to be switched and performs switching control. As a result, since the control circuit 23 selects the 3 frequency divider 26, the 19.998 MHz signal is divided by the 3 frequency divider 26 and the 2 frequency divider 27, and the 3.333 MHz signal is input to the reference filter 29. After that, the cutoff frequencies of the reference filter 29 and the baseband filter 33 are adjusted in the same manner as in the first embodiment.

In FIG. 5, the microprocessor 36 is used to control the electronic circuit of the mobile phone 37. The selector 24 can be switched by using the microprocessor 36 as the control of the digital signal.

FIG. 6 shows an example in which 13.5 MHz is input as the reference clock signal 21. By grounding the input terminal 38 to which a digital signal is input, the control circuit 23 controls the selector 24 to select the ½ frequency divider 25. As a result, the 13.5 MHz signal is divided by the frequency divider 25 and the frequency divider 27, and the 3.375 MHz signal is input to the reference filter 29.

Next, when 19.998 MHz is input as the reference clock signal 21, the input terminal 38 is connected to the power supply side so that the control circuit 23 controls the selector 24 and the frequency divider 26. select.

After that, the cutoff frequencies of the reference filter 29 and the baseband filter 33 are adjusted in the same manner as in the first embodiment.

In FIG. 7, the external control circuit 41 is shown in FIG.
And a digital-analog converter (hereinafter referred to as DAC) 40 that outputs an analog voltage based on a control signal from the control circuit 41 and a DC voltage correction circuit 39.

Next, an example of the relationship between the input frequency of the reference filter 29 and the control voltage to the reference filter 29 in the frequency adjusting circuit 20 is shown in FIG.

Since the baseband filter 33 is designed so that a desired frequency characteristic can be obtained when V0 is applied, the input frequency to the reference filter 29 is 3.3.
In the case of 75 MHz, V0 is output from the DC voltage correction circuit 39 and the baseband filter 33 obtains a desired frequency characteristic. At this time, from the DAC 40 to the DC voltage correction circuit 39
The voltage applied to is 0V by the control circuit 41.

When the input frequency is 3.333 MHz, V0 'is output from the DC voltage correction circuit 39. At this time D
Since the control circuit 41 applies V0-V0 'to the voltage applied from the AC 40 to the DC voltage correction circuit 39, the DC voltage correction circuit 39 applies V0 to V0 to the baseband filter 33.
A desired frequency characteristic can be obtained by adding the.

Thus, by inserting the DC voltage correction circuit 39 between the multiplication circuit 30 and the baseband filter 33 according to the reference clock signal 21 to correct the DC voltage, accurate frequency correction can be performed.

The DC voltage correction circuit 39 can be easily constructed by an operational amplifier or the like.

In FIG. 9, first, the reference clock signal 21
The case where the frequency is 13.5 MHz will be described. 1
When 3.5 MHz is input to the input terminal 22, the frequency detection circuit 35 connected to the input terminal 22 detects the frequency. The detection result is transmitted to the control circuit 23. Control circuit 2
3 selects the frequency divider 25, and the 13.5 MHz signal is divided by the frequency divider 25 and the frequency divider 27, and the 3.375 MHz signal is input to the reference filter 29. After that, the cutoff frequencies of the reference filter 29 and the baseband filter 33 are adjusted in the same manner as in the first embodiment.

At the same time, the control circuit 41 outputs a voltage of almost 0 V from the DAC 40 and inputs it to the DC voltage correction circuit 39.
The DC voltage correction circuit 39 adds the control voltage V01 from the frequency adjustment circuit 20 and the voltage of approximately 0 V supplied from the DAC 40, and adds the control voltage V01 to the baseband filter 33.
To control.

Next, the frequency of the reference clock signal 21 is 1
The case of 9.998 MHz will be described. 19.99
When 8 MHz is input to the input terminal 22, the input terminal 22
The frequency detection circuit 35 connected to detects the frequency.
The detection result is transmitted to the control circuit 23. Since the control circuit 23 selects the 3 frequency divider 26, the 19.998 MHz signal is divided by the 3 frequency divider 26 and the 2 frequency divider 27 to obtain 3.333 M.
The Hz signal is input to the reference filter 29. After that, the cutoff frequencies of the reference filter 29 and the baseband filter 33 are adjusted in the same manner as in the first embodiment.

At the same time, the control circuit 41 controls the DAC 40 to V0.
The voltage of 1-V02 is output and input to the DC voltage correction circuit 39. The DC voltage correction circuit 39 controls the control voltage V02 from the frequency adjustment circuit 20 and V01− supplied from the DAC 40.
V02 is added to control the baseband filter 33 with the control voltage V01. Therefore, the reference clock signal 21 is 1
V0 for both 3.5MHz and 19.998MHz
Since the cutoff frequency of the baseband filter 33 can be controlled by 1, the error can be brought close to 0.

In FIG. 10, it is assumed that the selector 24 selects the divide-by-2 frequency divider 25 by the control circuit 23 when there is no input to the frequency detection circuit 35. Reference clock signal 2
The case where the frequency of 1 is 13.5 MHz will be described.
The input 13.5 MHz signal is divided into two by the frequency divider 25, and the 6.75 MHz signal is input to the frequency detection circuit 35. The frequency detection circuit 35 has a frequency of 6.75 MHz.
Is detected and the frequency of the reference clock signal 21 is 13.5 MHz.
z is determined and the result is transmitted to the control circuit 41. The control circuit 41 outputs a voltage of almost 0 from the DAC 40 and inputs it to the DC voltage correction circuit 39. The DC voltage correction circuit 39 adds the control voltage V01 from the frequency adjustment circuit 20 and the voltage of approximately 0 V supplied from the DAC 40 to control the baseband filter 33 with the control voltage V01.

Next, the frequency of the reference clock signal 21 is 1
The case of 9.998 MHz will be described. The input 19.998 MHz is divided by 2 by the frequency divider 25 to 9.9.
The 99 MHz signal is input to the frequency detection circuit 35.
The frequency detection circuit 35 detects the frequency of 9.999 MHz, determines that the frequency of the reference clock signal 21 is 19.998 MHz, and transmits the result to the control circuit 41. Control circuit 4
1 outputs the voltage of V01-V02 from the DAC 40 and inputs it to the DC voltage correction circuit 39. The DC voltage correction circuit 39 uses the control voltage V02 from the frequency adjustment circuit 20 and the DAC 40.
The voltage of V01-V02 supplied from is added to control the baseband filter 33 with the control voltage V01. Therefore, the reference clock signal 21 is 13.5 MHz, 19.9 MHz.
Since the cutoff frequency of the baseband filter 33 can be controlled by V01 in both cases of 98 MHz, the error can be made close to zero.

In FIG. 11, the microprocessor 36 is used to control the electronic circuit of the mobile phone 37. By using the digital signal from the microprocessor 36 for the control of the control circuit 23, the selector 24 can be switched and the voltage of the DAC 41 can be set. In this way, the reference clock signal 21.
In both cases of 5 MHz and 19.998 MHz, since the cutoff frequency of the baseband filter 33 can be controlled by V01, the error can be brought close to zero.

FIG. 12 shows an example in which 13.5 MHz is input as the reference clock signal 21. The control circuit 23 controls the selector 24 to select the ½ frequency divider 25 by grounding the input terminal 38 to which a digital signal is input, and the input terminal 42 is grounded to output almost 0 V to the DAC 40.

19.998 MHz is the reference clock signal 2
When it is input as 1, the input terminal 38 is connected to the power supply, so that the control circuit 23 controls the selector 24 to select the frequency divider 26 and connect the input terminal 42 to the power supply side. As a result, the voltage of V01-V02 is output to the DAC 40. Therefore, the reference clock is 13.5M
Since the cutoff frequency of the baseband filter 33 can be controlled by V01 in both cases of Hz and 19.998 MHz, the error can be brought close to zero.

[0058]

As described above, according to the present invention, a frequency adjusting circuit for realizing different reference signals is realized, and the frequency adjusting circuit can be operated even if it is built in a mobile phone having different reference clock signals. Can be realized.

[Brief description of drawings]

FIG. 1 is a block diagram of a frequency adjusting circuit according to a first embodiment of the present invention.

FIG. 2 is a graph of phase frequency characteristics of the frequency adjusting circuit according to the first embodiment of the present invention.

FIG. 3 is a block diagram of another frequency adjusting circuit according to the first embodiment of the present invention.

FIG. 4 is a block diagram of another frequency adjusting circuit according to the first embodiment of the present invention.

FIG. 5 is a block diagram of another frequency adjusting circuit according to the first embodiment of the present invention.

FIG. 6 is a block diagram of another frequency adjusting circuit according to the first embodiment of the present invention.

FIG. 7 is a block diagram of another frequency adjusting circuit according to the first embodiment of the present invention.

FIG. 8 is a graph showing an input frequency and a control voltage of the frequency adjusting circuit according to the first embodiment of the present invention.

FIG. 9 is a block diagram of another frequency adjustment circuit according to the first embodiment of the present invention.

FIG. 10 is a block diagram of another frequency adjusting circuit according to the first embodiment of the present invention.

FIG. 11 is a block diagram of another frequency adjustment circuit according to the first embodiment of the present invention.

FIG. 12 is a block diagram of another frequency adjusting circuit according to the first embodiment of the present invention.

FIG. 13 is a block diagram showing a configuration of a conventional frequency adjustment circuit.

[Explanation of symbols]

20 Frequency adjustment circuit 21 Reference clock signal 22, 38, 42 input terminals 23,41 Control circuit 24 selector 25,27 2 frequency divider 26 3 frequency divider 28 frequency divider 29 Standard filter 30 multiplication circuit 31 Low-pass filter 32 baseband amplifier 33 Baseband filter 34 ADC 35 Frequency detection circuit 36 microprocessors 37 mobile phones 39 DC voltage correction circuit 40 DAC

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Yasuo Oba             1006 Kadoma, Kadoma-shi, Osaka Matsushita Electric             Sangyo Co., Ltd. (72) Inventor Takeshi Fujii             1006 Kadoma, Kadoma-shi, Osaka Matsushita Electric             Sangyo Co., Ltd. (72) Inventor Ippei Jinno             1006 Kadoma, Kadoma-shi, Osaka Matsushita Electric             Sangyo Co., Ltd. F-term (reference) 5J098 AB15 AB25 AB26 AB31 AC02                       AC09 AD14 CB03

Claims (13)

[Claims] 1. A frequency dividing circuit for dividing a reference clock signal, a reference filter for setting a phase difference in an output signal of the frequency dividing circuit, an output signal of the reference filter and an output signal of the frequency dividing circuit. It is composed of a multiplication circuit for multiplying and a low-pass filter connected to the output of this multiplication circuit, and a frequency adjustment circuit in which the output voltage from the low-pass filter is negatively fed back to the reference filter so that the cut-off frequency of the reference filter becomes constant. In the frequency adjusting circuit, a plurality of different reference clock signals are changed in one frequency adjusting circuit by a selector of a frequency dividing circuit so that the cutoff frequency of the reference filter becomes constant. 2. The frequency adjusting circuit according to claim 1, wherein the control circuit controls the selector by an output signal of the frequency detecting circuit connected to the reference clock signal. 3. The frequency adjusting circuit according to claim 1, wherein the control circuit controls the selector by the output signal of the frequency detecting circuit connected to the frequency-divided signal of the reference clock signal. 4. The frequency adjusting circuit according to claim 1, wherein the control circuit controls the selector by a digital signal given from the outside. 5. The structure according to claim 4, wherein the digital signal is supplied from a microprocessor controlling the mobile phone.
The frequency adjustment circuit described in. 6. The frequency adjusting circuit according to claim 4, wherein the digital signal is applied by powering or grounding a terminal of the control circuit. 7. The phase difference between the input and output signals of the reference filter is 9
The frequency adjusting circuit according to claim 1, wherein the frequency adjusting circuit has a 0 ° phase configuration. 8. A DC voltage correction circuit is connected between the output of the multiplication circuit and the baseband filter to correct the DC voltage for different reference clock signal frequencies. The frequency adjustment circuit according to any one of the above. 9. The frequency adjusting circuit according to claim 8, wherein the control circuit sets the correction amount of the DC voltage by the output signal of the frequency detecting circuit connected to the reference clock signal. 10. The frequency adjusting circuit according to claim 8, wherein the control circuit sets the correction amount of the DC voltage by the output signal of the frequency detecting circuit connected to the frequency-divided signal of the reference clock signal. 11. The frequency adjusting circuit according to claim 8, wherein the control circuit sets the correction amount of the DC voltage by a digital signal given from the outside. 12. The frequency adjusting circuit according to claim 11, wherein the digital signal is supplied from a microprocessor for controlling the mobile phone. 13. The frequency adjusting circuit according to claim 11, wherein the digital signal is provided by powering or grounding a terminal of the control circuit.