JP2003282899A - Solar battery element - Google Patents

Solar battery element

Info

Publication number
JP2003282899A
JP2003282899A JP2002078195A JP2002078195A JP2003282899A JP 2003282899 A JP2003282899 A JP 2003282899A JP 2002078195 A JP2002078195 A JP 2002078195A JP 2002078195 A JP2002078195 A JP 2002078195A JP 2003282899 A JP2003282899 A JP 2003282899A
Authority
JP
Japan
Prior art keywords
solar cell
surface side
semiconductor substrate
cell element
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2002078195A
Other languages
Japanese (ja)
Other versions
JP4146656B2 (en
Inventor
Hiroaki Takahashi
宏明 高橋
Kenji Fukui
健次 福井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP2002078195A priority Critical patent/JP4146656B2/en
Publication of JP2003282899A publication Critical patent/JP2003282899A/en
Application granted granted Critical
Publication of JP4146656B2 publication Critical patent/JP4146656B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00Energy generation through renewable energy sources
    • Y02E10/50Photovoltaic [PV] energy

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that superposing the output deriving portion of a solar battery element and its each collector portion for a screen printing to bake them and form an electrode causes the cell-crack of the solar battery element which starts from their superimposed portion has been generated conventionally. <P>SOLUTION: In a semiconductor substrate 1 of the solar battery element, different conductive regions from each other are so formed on its one principal- surface side and its other-principal surface side as to form respectively a front- surface electrode 4 and rear-surface electrodes on its one and other principal- surface sides. The rear-surface electrodes comprise a strip-like output deriving portion 5 formed on the other principal-surface side and collector portions 6 formed in the nearly whole region of the other principal-surface side wherefrom the formed region of the output deriving portion 5 is excluded. Further, in this solar battery element, each collector portion 6 is so provided as to superimpose it on the peripheral edge portion of the output deriving portion 5. Moreover, cell-crack preventing layers 7 are provided in the peripheral edge portions of the semiconductor substrate 1 which are existent near the output deriving portion 5. <P>COPYRIGHT: (C)2004,JPO

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は太陽電池素子に関
し、特に裏面電極を帯状の出力取出部と集電部とで構成
した太陽電池素子に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solar cell element, and more particularly to a solar cell element having a back electrode composed of a strip-shaped output extraction portion and a current collecting portion.

【0002】[0002]

【従来の技術】従来のシリコン太陽電池を図3に示す。
図3に示すように、P型半導体基板1の表面近傍全面に
一定の深さまでN型不純物を拡散させてN型を呈する拡
散層2を形成するとともに、この拡散層2の表面に反射
防止膜3を形成したものである。また、表面側には表面
電極4が形成され、裏面側には出力取出部5と集電部6
から成る裏面電極5、6が形成されている。
2. Description of the Related Art A conventional silicon solar cell is shown in FIG.
As shown in FIG. 3, an N type diffusion layer 2 is formed by diffusing N type impurities to a certain depth all over the surface of the P type semiconductor substrate 1, and an antireflection film is formed on the surface of the diffusion layer 2. 3 is formed. Further, the front surface electrode 4 is formed on the front surface side, and the output extracting portion 5 and the current collecting portion 6 are formed on the rear surface side.
Are formed on the back electrodes 5 and 6.

【0003】この裏面電極5、6の形成方法について
は、特開平5−326990号公報、あるいは特表平6
−509910号公報に開示されているように、半導体
基板1の裏面の一領域に銀ペースト(5)を塗布して乾
燥した後、その領域の周辺部の一部に重なるようにアル
ミニウムペースト(6)を塗布して乾燥して同時に焼成
する方法、すなわち同時焼成法(一段階焼成)が用いら
れている。この従来の太陽電池素子では、裏面電極の出
力取出部5は10μm程度の厚みに形成され、集電部6
は50μm程度の厚みに形成され、重なり部は60μm
程度の総厚に形成される。
A method for forming the back electrodes 5 and 6 is described in Japanese Patent Laid-Open No. 5-326990 or Japanese Patent Publication No.
As disclosed in Japanese Patent No. 509910, a silver paste (5) is applied to one region on the back surface of the semiconductor substrate 1 and dried, and then an aluminum paste (6) is formed so as to partially overlap the peripheral portion of the region. ) Is applied, dried and simultaneously fired, that is, a simultaneous firing method (one-step firing) is used. In this conventional solar cell element, the output extracting portion 5 of the back electrode is formed to have a thickness of about 10 μm, and the current collecting portion 6 is formed.
Is formed to a thickness of about 50 μm, and the overlapping portion is 60 μm
It is formed to a total thickness of about.

【0004】このようにして製造された太陽電池素子で
は、複数の素子同士を配線材を用いて直列に接続して電
圧を昇圧して使用するのが一般的である。この素子間の
接続にははんだが必要となるため、表面電極4と裏面電
極5、6にはんだコーティングを行っている。このとき
裏面電極の出力取出部5にはんだ濡れ性が良好な素材を
用いてこれに配線材(不図示)をはんだ付けしている。
In the solar cell element manufactured as described above, it is general that a plurality of elements are connected in series by using a wiring material to boost the voltage for use. Since solder is required for connection between these elements, the front surface electrode 4 and the back surface electrodes 5 and 6 are coated with solder. At this time, a material having good solder wettability is used for the output extraction portion 5 of the back surface electrode, and a wiring material (not shown) is soldered thereto.

【0005】[0005]

【発明が解決しようとする課題】ところが、上記のよう
な裏面電極5、6の構造では、出力取出部5と集電部6
を同時焼成するときに、集電部6の成分が出力取出部5
の一部に拡散して合金層(不図示)が形成されるが、こ
の合金層は焼結による収縮率が大きいため、これと接合
する半導体基板1との界面で引張り応力が発生し、半導
体基板1の一部に応力集中が起こる。そのため、焼成後
の工程で出力取出部5と集電部6の重なり部を起点とす
るセル割れが多発するという問題があった。
However, in the structure of the back electrodes 5 and 6 as described above, the output extraction portion 5 and the current collection portion 6 are provided.
When co-firing, the components of the current collector 6 are
An alloy layer (not shown) is formed by diffusing into a part of the semiconductor layer. However, since this alloy layer has a large shrinkage rate due to sintering, a tensile stress is generated at the interface with the semiconductor substrate 1 bonded to the alloy layer, and Stress concentration occurs in a part of the substrate 1. Therefore, there has been a problem that cell cracking from the overlapping portion of the output extracting portion 5 and the current collecting portion 6 frequently occurs in the process after firing.

【0006】上記のような問題を回避するために、裏面
電極の出力取出部5の焼成後の厚みを2μm以上6μm
以下にすると有効であることが分かっている。しかし、
裏面電極5、6の出力取出部5の全体の厚みを薄くする
と、出力取出部5と半導体基板1の接着強度が低下する
ため、はんだコーティングやモジュール作成の際に出力
取出部5aが剥離しやすくなるという問題があった。
In order to avoid the above problems, the thickness of the output extraction portion 5 of the back electrode after firing is set to 2 μm or more and 6 μm or more.
The following has been found to be effective: But,
If the entire thickness of the output extraction portion 5 of the back surface electrodes 5, 6 is reduced, the adhesive strength between the output extraction portion 5 and the semiconductor substrate 1 is reduced, so that the output extraction portion 5a is easily peeled off during solder coating or module fabrication. There was a problem of becoming.

【0007】本発明は上記問題に鑑みてなされたもので
あり、出力取出部と集電部を一部重ねてスクリーン印刷
して焼成して電極を形成すると、出力取出部と集電部と
の重なり部分を起点とするセル割れが発生するという従
来の問題点を解消した太陽電池素子を提供することを目
的とする。
The present invention has been made in view of the above problems. When the output extraction part and the current collecting part are partially screen-printed and baked to form an electrode, the output extraction part and the current collecting part are combined. It is an object of the present invention to provide a solar cell element that solves the conventional problem of cell cracking starting from an overlapping portion.

【0008】[0008]

【課題を解決するための手段】上記目的を達成するため
に、請求項1に係る太陽電池素子では、半導体基板の一
主面側と他の主面側に異なる導電領域を形成して、一主
面側に表面電極を形成するとともに、他の主面側に帯状
の出力取出部とこの出力取出部が形成された領域以外の
略全面に形成された集電部とで構成される裏面電極を設
けた太陽電池素子において、前記出力取出部の周縁部と
前記集電部とが重なるように設けるとともに、この出力
取出部近傍の前記半導体基板の周縁部に、セル割れ防止
層を設けたことを特徴とする。
In order to achieve the above object, in a solar cell element according to claim 1, different conductive regions are formed on one main surface side and another main surface side of a semiconductor substrate, A back surface electrode formed with a front surface electrode on the main surface side and a strip-shaped output extraction portion on the other main surface side and a current collection portion formed on substantially the entire surface other than the area where the output extraction portion is formed. In the solar cell element provided with, the peripheral portion of the output extraction portion and the current collecting portion are provided so as to overlap, and a cell crack prevention layer is provided in the peripheral portion of the semiconductor substrate in the vicinity of the output extraction portion. Is characterized by.

【0009】上記太陽電池素子では、前記セル割れ防止
層は、前記出力取出部の長手方向の延長線と交差する方
向に形成されていることが望ましい。
In the above solar cell element, it is desirable that the cell crack prevention layer is formed in a direction intersecting an extension line of the output extraction portion in the longitudinal direction.

【0010】また、上記太陽電池素子では、前記出力取
出部とセル割れ防止層とが銀を主成分として構成される
とともに、前記集電部がアルミニウムを主成分として構
成されることが望ましい。
Further, in the above solar cell element, it is preferable that the output extraction portion and the cell crack prevention layer are made of silver as a main component, and the current collecting portion is made of aluminum as a main component.

【0011】また、上記太陽電池素子では、前記出力取
出部の周縁部上に前記集電部が重なるように形成されて
いることが望ましい。
Further, in the above solar cell element, it is desirable that the current collecting portion is formed so as to overlap the peripheral portion of the output extracting portion.

【0012】[0012]

【発明の実施の形態】以下、本発明の実施形態を詳細に
説明する。本発明の太陽電池素子も基本構造は図3に示
す従来の太陽電池素子の構造と同じである。すなわち、
一導電型例えばP型の半導体基板1の表面近傍全面に一
定の深さまで逆導電型例えばN型不純物を拡散させて逆
導電型例えばN型を呈する拡散層2を形成するととも
に、この拡散層2の表面に反射防止膜3を形成したもの
である。また、表面側には表面電極4が形成され、裏面
側には出力取出部5と集電部6から成る裏面電極5、6
が形成されている。
BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below. The basic structure of the solar cell element of the present invention is the same as the structure of the conventional solar cell element shown in FIG. That is,
A diffusion layer 2 of the opposite conductivity type, for example N type, is formed by diffusing an impurity of the opposite conductivity type, for example N type, to a certain depth all over the surface of the semiconductor substrate 1 of one conductivity type, for example P type, and the diffusion layer 2 is formed. The antireflection film 3 is formed on the surface of the. Further, the front surface electrode 4 is formed on the front surface side, and the rear surface electrodes 5, 6 including the output extracting portion 5 and the current collecting portion 6 are formed on the rear surface side.
Are formed.

【0013】半導体基板1は単結晶もしくは多結晶のシ
リコン基板などで構成される。この半導体基板1はp
型、n型いずれでもよい。単結晶シリコンの場合は引き
上げ法などで形成され、多結晶シリコンの場合は鋳造法
などで形成される。多結晶シリコンは、大量生産が可能
で製造コスト面で単結晶シリコンよりもきわめて有利で
ある。引き上げ法や鋳造法で形成されたシリコンブロッ
クを10cm×10cmもしくは15cm×15cm程
度の大きさに切断してインゴットとし、300μm程度
の厚みにスライスして半導体基板1とする。
The semiconductor substrate 1 is composed of a monocrystalline or polycrystalline silicon substrate or the like. This semiconductor substrate 1 is p
Type or n-type may be used. In the case of single crystal silicon, it is formed by a pulling method, and in the case of polycrystalline silicon, it is formed by a casting method. Polycrystalline silicon can be mass-produced and is extremely advantageous over single crystal silicon in terms of manufacturing cost. A silicon block formed by a pulling method or a casting method is cut into a size of about 10 cm × 10 cm or 15 cm × 15 cm to form an ingot, and the semiconductor block 1 is sliced to a thickness of about 300 μm.

【0014】半導体基板1の表面側には、逆導電型半導
体不純物が拡散された拡散層2が形成されている。この
逆導電型半導体不純物が拡散された拡散層2は、半導体
基板1内に半導体接合部を形成するために設けるもので
あり、例えばn型の不純物を拡散させる場合、POCl
3を用いた気相拡散法、P25を用いた塗布拡散法、お
よびP+イオンを電界で基板1に直接導入するイオン打
ち込み法などで形成される。この逆導電型半導体不純物
を含有する拡散層2は0.3〜0.5μm程度の深さに
形成される。
A diffusion layer 2 in which semiconductor impurities of opposite conductivity type are diffused is formed on the surface side of the semiconductor substrate 1. The diffusion layer 2 in which the semiconductor impurities of the opposite conductivity type are diffused is provided to form a semiconductor junction in the semiconductor substrate 1. For example, when diffusing n-type impurities, POCl
It is formed by a vapor phase diffusion method using 3 , a coating diffusion method using P 2 O 5 , and an ion implantation method in which P + ions are directly introduced into the substrate 1 by an electric field. The diffusion layer 2 containing the opposite conductivity type semiconductor impurities is formed to a depth of about 0.3 to 0.5 μm.

【0015】また、半導体基板1の表面側には、反射防
止膜3が形成されている。この反射防止膜3は、半導体
基板1の表面で光が反射するのを防止して、半導体基板
1内に光を有効に取り込むために設ける。この反射防止
膜3は半導体基板1との屈折率差等を考慮して屈折率が
2程度の材料で構成され、厚み500〜2000Å程度
の窒化シリコン膜や酸化シリコン(SiO2)膜などで
構成される。
An antireflection film 3 is formed on the surface side of the semiconductor substrate 1. The antireflection film 3 is provided to prevent light from being reflected on the surface of the semiconductor substrate 1 and to effectively take in the light into the semiconductor substrate 1. The antireflection film 3 is made of a material having a refractive index of about 2 in consideration of a difference in refractive index with the semiconductor substrate 1, and is made of a silicon nitride film or a silicon oxide (SiO 2 ) film having a thickness of about 500 to 2000Å. To be done.

【0016】半導体基板1の裏面側には、一導電型半導
体不純物が高濃度に拡散されたBSF層(不図示)を形
成することが望ましい。この一導電型半導体不純物が高
濃度に拡散されたBSF層は、半導体基板1の裏面近く
でキャリアの再結合による効率の低下を防ぐために、半
導体基板1の裏面側に内部電界を形成するものである。
On the back surface side of the semiconductor substrate 1, it is desirable to form a BSF layer (not shown) in which one conductivity type semiconductor impurity is diffused at a high concentration. The BSF layer in which the one-conductivity-type semiconductor impurity is diffused at a high concentration forms an internal electric field on the back surface side of the semiconductor substrate 1 in order to prevent a decrease in efficiency due to recombination of carriers near the back surface of the semiconductor substrate 1. is there.

【0017】つまり、半導体基板1の裏面近くで発生し
たキャリアがこの電界で加速される結果、電力が有効に
取り出されることとなり、特に長波長の光感度が増大す
ると共に、高温における太陽電池特性の低下を軽減でき
る。このように一導電型半導体不純物が高濃度に拡散さ
れたBSF層が形成された半導体基板1の裏面側のシー
ト抵抗は15Ω/□程度になる。
That is, the carriers generated near the back surface of the semiconductor substrate 1 are accelerated by this electric field, and as a result, electric power is effectively taken out, the photosensitivity particularly at long wavelength is increased, and the solar cell characteristics at high temperature are improved. The decrease can be reduced. As described above, the sheet resistance on the back surface side of the semiconductor substrate 1 on which the BSF layer in which the one-conductivity-type semiconductor impurity is diffused at a high concentration is formed is about 15 Ω / □.

【0018】半導体基板1の表面側および裏面側には、
表面電極4および裏面電極5、6が形成されている。こ
の表面電極4および裏面電極5、6は主にAg紛、バイ
ンダー、ガラスフリットなどからなるAgペーストをス
クリーン印刷して焼成し、その上にはんだ層を形成す
る。表面電極4は、例えば幅200μm程度に、またピ
ッチ3mm程度に形成される多数のフィンガー電極(不
図示)と、この多数のフィンガー電極を相互に接続する
2本のバスバー電極で構成される。この表面電極4は厚
み10〜30μm程度に形成される。
On the front surface side and the back surface side of the semiconductor substrate 1,
The front surface electrode 4 and the back surface electrodes 5 and 6 are formed. The front surface electrode 4 and the back surface electrodes 5 and 6 are formed by screen-printing an Ag paste mainly composed of Ag powder, a binder, a glass frit, etc. and firing it to form a solder layer thereon. The surface electrode 4 is composed of, for example, a large number of finger electrodes (not shown) formed with a width of about 200 μm and a pitch of about 3 mm, and two bus bar electrodes that connect the large number of finger electrodes to each other. The surface electrode 4 is formed to have a thickness of about 10 to 30 μm.

【0019】裏面電極は、例えば半導体基板1の略全長
にわたって例えば幅10mm程度に形成された帯状の出
力取出部5とこの出力取出部5以外の略全面にわたって
形成された集電部6とで構成される。この出力取出部5
は焼成後の厚みで10μm程度、集電部6は焼成後の厚
みで50μm程度に形成される。
The back surface electrode is composed of, for example, a strip-shaped output extracting portion 5 formed to have a width of, for example, about 10 mm over substantially the entire length of the semiconductor substrate 1, and a current collecting portion 6 formed over substantially the entire surface other than the output extracting portion 5. To be done. This output extraction unit 5
Is about 10 μm in thickness after firing, and the current collector 6 is formed in about 50 μm in thickness after firing.

【0020】本発明の太陽電池素子では、図1よび図2
に示すように、帯状の出力取出部5とこの出力取出部5
が形成された領域以外の略全面に形成された集電部6と
から成る裏面電極5、6を、この集電部6が出力取出部
5の周縁部に重なるように設けている。また、この出力
取出部5近傍の半導体基板1の周縁部に、セル割れ防止
層7を設けている。このセル割れ防止層7は、出力取出
部5の長手方向の延長線と交差する方向に形成されてい
る。すなわち、出力取出部5に連続して出力取出部5と
T字状をなすように形成したり、出力取出部5とは非連
続に出力取出部5とT字状をなすように形成したり、基
板1の周縁部の全周にわたって形成する。
In the solar cell element of the present invention, as shown in FIGS.
As shown in FIG. 5, the strip-shaped output extracting unit 5 and the output extracting unit 5
The back surface electrodes 5 and 6 each including a current collecting portion 6 formed on substantially the entire surface other than the region where the current collecting portion is formed are provided so that the current collecting portion 6 overlaps the peripheral portion of the output extracting portion 5. Further, a cell crack preventing layer 7 is provided on the peripheral portion of the semiconductor substrate 1 near the output extraction portion 5. The cell crack prevention layer 7 is formed in a direction intersecting the extension line of the output extraction portion 5 in the longitudinal direction. That is, it may be formed so as to be continuous with the output take-out portion 5 so as to form a T-shape with the output take-out portion 5, or be formed so as to have a T-shape with the output take-out portion 5 discontinuously with the output take-out portion 5. , Is formed over the entire circumference of the peripheral portion of the substrate 1.

【0021】このようなセル割れ防止層7を設けると、
出力取出部5と集電部6を一部重ねてスクリーン印刷し
て焼成しても、基板1の周縁部がセル割れ防止層7で機
械的に補強されていることから、後工程において出力取
出部5と集電部6との重なり部分を起点とするセル割れ
が発生することを防止できる。
When such a cell crack preventing layer 7 is provided,
Even if the output extracting portion 5 and the current collecting portion 6 are partially overlapped with each other and screen-printed and baked, the peripheral portion of the substrate 1 is mechanically reinforced by the cell crack preventing layer 7, so that the output extracting portion can be extracted in a later step. It is possible to prevent the occurrence of cell cracks starting from the overlapping portion of the portion 5 and the current collecting portion 6.

【0022】このセル割れ防止層は、銀などから成り、
出力取出部5と同時にパターニングされて同時に焼き付
けられる。
The cell crack prevention layer is made of silver or the like,
It is patterned at the same time as the output take-out portion 5 and baked at the same time.

【0023】また、出力取出部5にはんだ塗れ性のよい
銀を用いることで配線材のはんだ付けを容易にすると共
に、集電部6にアルミニウムを用いることで、焼成時に
半導体裏面にP+層を形成してキャリア再結合を防ぎ、
セル特性を向上させることができる。
Further, by using silver having good solder coatability for the output extraction portion 5 to facilitate soldering of the wiring material, and for using aluminum for the current collecting portion 6, a P + layer is formed on the back surface of the semiconductor during firing. To prevent carrier recombination,
The cell characteristics can be improved.

【0024】次に、本発明に係る太陽電池素子の形成方
法を説明する。まず、図3(a)のように一導電型例え
ばP型半導体基板を準備する。そして、図3(b)に示
すように半導体基板1を逆導電型例えばN型不純物雰囲
気中で熱処理などして、半導体基板1の表面近傍全面に
一定の深さまでN型不純物を拡散させてN型を呈する拡
散層2を形成する。次に、図3(c)に示すように、半
導体基板1の表面にプラズマCVD法などで反射防止膜
3を形成する。
Next, a method for forming the solar cell element according to the present invention will be described. First, as shown in FIG. 3A, one conductivity type, for example, a P-type semiconductor substrate is prepared. Then, as shown in FIG. 3B, the semiconductor substrate 1 is heat-treated in an atmosphere of an opposite conductivity type, for example, an N-type impurity, to diffuse the N-type impurities to a certain depth all over the surface near the surface of the semiconductor substrate 1 to form an N-type impurity. A diffusion layer 2 having a mold is formed. Next, as shown in FIG. 3C, the antireflection film 3 is formed on the surface of the semiconductor substrate 1 by a plasma CVD method or the like.

【0025】次に、拡散層2を分離した後、表面電極4
を印刷して乾燥させる。その後に、図1(a)に示した
出力取出部5とセル割れ防止層7のパターンにガラスフ
リットを含む銀ペーストを印刷して乾燥させ、さらにそ
の一部と重なるようにアルミニウムペースト(6)をス
クリーン印刷して焼成することにより、図3(d)に示
すような太陽電池素子を得ることができる。なお、セル
割れ防止層7とアルミニウムペースト(6)は重ならな
いように形成してもよい。
Next, after separating the diffusion layer 2, the surface electrode 4 is formed.
Print and dry. After that, a silver paste containing glass frit is printed on the pattern of the output extraction portion 5 and the cell crack preventing layer 7 shown in FIG. 1A and dried, and the aluminum paste (6) is further overlapped with a part thereof. By screen-printing and baking, a solar cell element as shown in FIG. 3 (d) can be obtained. The cell crack prevention layer 7 and the aluminum paste (6) may be formed so as not to overlap with each other.

【0026】その後、半導体基板1をベルト炉等の焼成
炉において焼成することによって、表面電極4および裏
面電極5、6が同時に形成される。このとき、アルミニ
ウムから成る集電部6からアルミニウムが銀から成る出
力取出部5に拡散してAg/Al合金層7が形成され
る。その後、各電極4、5、6が形成された半導体基板
1をはんだ槽に浸漬して表面電極4と裏面電極の出力取
出部5にはんだコーティング層(不図示)を形成する。
Then, the front surface electrode 4 and the back surface electrodes 5 and 6 are formed at the same time by baking the semiconductor substrate 1 in a baking furnace such as a belt furnace. At this time, aluminum diffuses from the current collector 6 made of aluminum to the output take-out portion 5 made of silver to form the Ag / Al alloy layer 7. Then, the semiconductor substrate 1 on which the electrodes 4, 5 and 6 are formed is dipped in a solder bath to form a solder coating layer (not shown) on the front electrode 4 and the output extraction portion 5 of the back electrode.

【0027】本発明は上記実施形態に限定されるもので
はなく本発明の範囲内で上記実施形態に多くの修正およ
び変更を加えうることはもちろんである。例えばアルミ
ニウムペーストに代わる金属ペーストとして、ガリウ
ム、インジウムをベースとした金属ペーストを使用する
ことも可能である。また銀ペーストに代わる金属ペース
トとして銅、金、白金をベースとした金属ペーストを使
用することも可能である。また、図1の裏面電極パター
ンは例であって、この形状に制限されるものではない。
It is needless to say that the present invention is not limited to the above embodiment, and many modifications and changes can be made to the above embodiment within the scope of the present invention. For example, a metal paste based on gallium or indium can be used as the metal paste instead of the aluminum paste. It is also possible to use a metal paste based on copper, gold or platinum as a metal paste instead of the silver paste. Further, the back surface electrode pattern of FIG. 1 is an example, and the shape is not limited to this shape.

【0028】[0028]

【実施例】以下に本発明の実施例を示す。図1(a)に
示すように半導体基板として15cm角で厚さ0.3m
m、比抵抗1.5Ω・cmのP型シリコン基板を準備し
た。そして図1(b)に示すように熱拡散法でオキシ塩
化リン(POCl3)を拡散源として、深さ0.5μm
のN型拡散層を形成した。
EXAMPLES Examples of the present invention will be shown below. As shown in FIG. 1A, the semiconductor substrate is 15 cm square and has a thickness of 0.3 m.
A P-type silicon substrate having m and a specific resistance of 1.5 Ω · cm was prepared. Then, as shown in FIG. 1B, a depth of 0.5 μm was obtained by using phosphorus oxychloride (POCl 3 ) as a diffusion source by a thermal diffusion method.
The N-type diffusion layer of was formed.

【0029】次に、表面にプラズマCVD法で窒化シリ
コンの反射防止膜を800Åの厚さで形成した後、拡散
層を分離した。
Next, an antireflection film of silicon nitride was formed on the surface by plasma CVD to a thickness of 800 Å, and then the diffusion layer was separated.

【0030】次に、図1(a)〜(c)に示す構造で裏
面に出力取出電極部5とセル割れ防止層7をAgを主体
とした金属ペーストでスクリーン印刷し、この出力取出
電極部5の一部を覆うように集電電極6をアルミニウム
ペーストでスクリーン印刷した。また、表面にも銀ペー
ストをスクリーン印刷して焼成することで電極を形成し
た。このとき、銀から成る出力取出部5とアルミニウム
から成る集電部6の重なりは0.5mmで形成された。
その後、200℃のはんだ浴槽に上記基板1を浸漬して
引き上げることで、表面電極4と裏面電極の出力取出部
5およびセル割れ防止層7をはんだ被覆して太陽電池素
子を作成した。また、その太陽電池素子を用いて太陽電
池モジュールを作成した。この太陽電池素子の電極焼成
後の全後工程におけるセル割れの発生率および光電変換
効率を従来の方法と比較して表1に示す。
Next, in the structure shown in FIGS. 1A to 1C, the output extraction electrode portion 5 and the cell crack preventing layer 7 are screen-printed on the back surface with a metal paste mainly containing Ag, and the output extraction electrode portion is formed. The collector electrode 6 was screen-printed with an aluminum paste so as to cover a part of 5. An electrode was also formed by screen-printing a silver paste on the surface and firing it. At this time, the output extracting portion 5 made of silver and the current collecting portion 6 made of aluminum were overlapped with each other by 0.5 mm.
Then, the substrate 1 was dipped in a solder bath at 200 ° C. and pulled up to cover the front electrode 4, the output extraction portion 5 of the back electrode, and the cell crack prevention layer 7 with a solder to prepare a solar cell element. Moreover, the solar cell module was created using the solar cell element. Table 1 shows the occurrence rate of cell cracking and the photoelectric conversion efficiency in all the post-processes after firing the electrodes of this solar cell element in comparison with the conventional method.

【0031】[0031]

【表1】 [Table 1]

【0032】表1に示すとおり、本発明の構造を用いた
場合は、従来に比べて焼成後に発生するセル割れを軽減
することができた。また、これらの太陽電池素子の光電
変換効率は従来の方法を用いた場合とほぼ同等であっ
た。
As shown in Table 1, when the structure of the present invention was used, cell cracks generated after firing could be reduced as compared with the conventional case. In addition, the photoelectric conversion efficiency of these solar cell elements was almost the same as when the conventional method was used.

【0033】[0033]

【発明の効果】以上のように、本発明に係る太陽電池素
子によれば、裏面電極の集電部を出力取出部の周縁部に
重なるように設けるとともに、この出力取出部近傍の半
導体基板の周縁部にセル割れ防止層を設けたことから、
この重なり部分を起点とする太陽電池素子の割れを防止
できるとともに、裏面電極と半導体基板との間に十分な
接着強度が強固となって裏面電極の剥離を防止すること
もできる。また、太陽電池素子の光電変換効率を損なう
こともない。
As described above, according to the solar cell element of the present invention, the collector portion of the back electrode is provided so as to overlap the peripheral portion of the output extraction portion, and the semiconductor substrate in the vicinity of the output extraction portion is provided. Since a cell crack prevention layer is provided at the peripheral edge,
It is possible to prevent cracking of the solar cell element starting from this overlapping portion, and it is also possible to prevent peeling of the back surface electrode due to sufficient adhesive strength between the back surface electrode and the semiconductor substrate. Further, the photoelectric conversion efficiency of the solar cell element is not impaired.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明に係る太陽電池素子の裏面電極パターン
を説明するための図である。
FIG. 1 is a diagram for explaining a back electrode pattern of a solar cell element according to the present invention.

【図2】本発明に係る太陽電池素子の形成方法の工程を
説明するための図である。
FIG. 2 is a diagram for explaining steps of a method for forming a solar cell element according to the present invention.

【図3】従来の太陽電池素子を示す図である。FIG. 3 is a diagram showing a conventional solar cell element.

【符号の説明】[Explanation of symbols]

1・・・半導体基板、2・・・n型拡散層、2a・・・
接合分離部、3・・・反射防止膜、4・・・表面電極、
5・・・出力取出部、6・・・集電部、7・・・セル割
れ防止層
1 ... Semiconductor substrate, 2 ... N-type diffusion layer, 2a ...
Junction separating part, 3 ... Antireflection film, 4 ... Surface electrode,
5 ... Output extraction part, 6 ... Current collecting part, 7 ... Cell crack prevention layer

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 半導体基板の一主面側と他の主面側に異
なる導電領域を形成して、一主面側に表面電極を形成す
るとともに、他の主面側に帯状の出力取出部とこの出力
取出部が形成された領域以外の略全面に形成された集電
部とで構成される裏面電極を設けた太陽電池素子におい
て、前記出力取出部の周縁部と前記集電部とが重なるよ
うに設けるとともに、この出力取出部近傍の前記半導体
基板の周縁部に、セル割れ防止層を設けたことを特徴と
する太陽電池素子。
1. A semiconductor substrate having one main surface side and another main surface side having different conductive regions to form surface electrodes on the one main surface side, and a strip-shaped output extraction portion on the other main surface side. In a solar cell element provided with a back electrode composed of a current collector formed on substantially the entire surface other than the region where the power output is formed, a peripheral portion of the power output and the current collector are A solar cell element, wherein the solar cell element is provided so as to overlap with each other, and a cell crack preventing layer is provided on a peripheral portion of the semiconductor substrate near the output extraction portion.
【請求項2】 前記セル割れ防止層は、前記出力取出部
の長手方向の延長線と交差する方向に形成されているこ
とを特徴とする請求項1に記載の太陽電池素子。
2. The solar cell element according to claim 1, wherein the cell crack prevention layer is formed in a direction intersecting a longitudinal extension line of the output extraction portion.
【請求項3】 前記出力取出部とセル割れ防止層とが銀
を主成分として構成されるとともに、前記集電部がアル
ミニウムを主成分として構成されることを特徴とする請
求項1または2に記載の太陽電池素子。
3. The output extraction part and the cell crack prevention layer are mainly composed of silver, and the current collection part is mainly composed of aluminum. The solar cell element described.
【請求項4】 前記出力取出部の周縁部上に前記集電部
が重なるように形成されていることを特徴とする請求項
1ないし3のいずれかに記載の太陽電池素子。
4. The solar cell element according to claim 1, wherein the current collecting portion is formed so as to overlap the peripheral portion of the output extraction portion.
JP2002078195A 2002-03-20 2002-03-20 Solar cell element Expired - Fee Related JP4146656B2 (en)

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Country Status (1)

Country Link
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006041309A (en) * 2004-07-29 2006-02-09 Kyocera Corp Connection structure of solar-cell element and solar-cell module containing its connection structure

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006041309A (en) * 2004-07-29 2006-02-09 Kyocera Corp Connection structure of solar-cell element and solar-cell module containing its connection structure
JP4557622B2 (en) * 2004-07-29 2010-10-06 京セラ株式会社 Solar cell element connection structure and solar cell module including the same

Also Published As

Publication number Publication date
JP4146656B2 (en) 2008-09-10

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